KR101179726B1 - Self-ionized and inductively-coupled plasma for sputtering and resputtering - Google Patents

Abstract

Disclosed are a magnetron sputter reactor 410 and a method of using a magnetron sputter reactor in which SIP sputtering and ICP sputtering are facilitated. In another chamber 412, an array of auxiliary magnets is disclosed disposed along sidewalls 414 of the magnetron sputter reactor on one side from the target toward the substrate. Preferably the magnetron 436 has a stronger external magnetic pole 442 with a first polarity surrounding the weaker internal magnetic pole 440 with a second polarity, where both the internal and external magnetic poles are yoke ( 444, the magnetron 436 rotates about the axis 438 of the chamber using the rotating means 446, 448, 450. Preferably the auxiliary magnets 462 have a first polarity to attract the unbalanced magnetic field 460 towards the substrate 424, the substrate 424 being on the pedestal 422 to which the power 454 is supplied. . Argon 426 is supplied through valve 428. The target 416 is supplied with power 434.

Description

Self-ionizing and inductively coupled plasma for sputtering and resputtering {SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING}

This application is partly pending application of pending application 09 / 685,978, filed October 10, 2000, and divided application of 09 / 414,614, filed October 8, 1999 (patented as US Pat. No. 6,398,929); And some continuing applications of pending application 10 / 202,778, filed on July 25, 2002 (priority applications 60 / 316,137, filed August 30, 2001, and 60 / 342,608, filed December 21, 2001). ; And some pending applications of pending application 09 / 993,543, filed November 14, 2001, which is incorporated herein by reference.

The present invention relates generally to sputtering and resputtering. In particular, the present invention relates to sputter deposition of material and resputtering of deposited material in the formation of semiconductor integrated circuits.

Semiconductor integrated circuits typically include multiple levels of metallizagtion to provide electrical connections between a plurality of active semiconductor devices. In particular, improved integrated circuits for microprocessors may include five or more metallization levels. In the past, aluminum has been the preferred metallization, but copper has been developed as the metallization for improved integrated circuits.

Typical metallization levels are shown in the cross sectional view of FIG. Lower level layer 110 includes conductive feature 112. If lower level layer 110 is a lower level dielectric layer, such as silica or other insulating material, conductive feature 112 may be a lower level copper metallization, where the vertical portion of the upper level metallization is the two vertical portions of the metallization. These are called vias because they interconnect the levels. If lower level layer 110 is a silicon layer, conductive feature 112 may be a doped silicon region, and the vertical portion of the upper level metallization formed in one hole is called a contact because it is in electrical contact with silicon. . Upper level dielectric layer 114 is deposited on lower level dielectric layer 110 and lower level metallization 112. There are several shapes for the holes including lines and trenches. Also, in dual damascene and similar interconnect structures, as will be described below, the holes have a complex shape. In some applications, the holes may not extend through the dielectric layer. The following discussion is made only for via holes, but in most circumstances the discussion is equally applicable to several types of holes with some variations well known in the art.

Typically, the dielectric is silicon oxide formed by plasma enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS) as a precursor. However, other compositions of low-k and deposition techniques may be considered. Some low k dielectrics developed are characterized as silicates, such as nitrided silicate glass. Afterwards, the silicate (oxide) dielectric is described directly, however, it is contemplated that other dielectric compositions may be used.

Via holes are typically etched into the top level dielectric layer 114 using a nitrogen based plasma etch process for the silicate dielectric. In improved integrated circuits, the via holes may have widths as small as 0.18 μm or less. Since the thickness of the dielectric layer 114 is generally at least 0.7 μm, and sometimes twice this, the aspect ratio of the holes may be 4: 1 or more. 6: 1 and more aspect ratios are proposed. In addition, in most circumstances, the via hole should have a vertical profile.

The liner layer 116 may be deposited on the bottom and sides of the hole and the dielectric layer 114. Liner 116 may perform some functions. The liner layer can act as an adhesion layer between the dielectric and the metal because the metal films tend to peel off the oxides. The liner layer can act as a barrier to internal diffusion between the oxide based dielectric and the metal. The liner layer acts as a seed and nucleation layer to nucleate uniform deposition and growth, possibly cold reflow for the deposition of metal filling the holes and uniform growth of each seed layer. . One or more liner layers may be deposited, where one liner layer may first act as a barrier layer and other liner layers may preferentially function as attachment, seed or nucleation layers.

An interconnect layer 118 of a conductive metal, such as copper, is then deposited on the liner layer 116 to fill the holes and cover the top of the dielectric layer 114. Typical aluminum metallizations are patterned into horizontal interconnections by selective etching of the flat portion of the metal layer 118. However, copper metallization technology, so-called dual damascene, forms a hole in the dielectric layer 114 into two connected portions, the first portion being narrow biases through the lower portion of the dielectric layer and the second portion interconnecting the bias. Wider trenches in the surface portion. After metal deposition, chemical mechanical polishing (CMP) is performed to remove the relatively soft copper exposed on the dielectric oxide but stop on the harder oxide. As a result, the multiple copper fill trenches of the upper level similar to the next lower level conductive feature 112 are insulated from each other. Copper filled trenches operate as horizontal interconnects between copper filled biases. The combination of double damascene and CMP eliminates the need to etch copper. Some layer structures and etching sequences have been developed for dual damascene and other metallization structures have similar manufacturing requirements.

Lining and filling via holes and similar high aspect ratio structures as occurring in dual damascene face ongoing challenges as their aspect ratios continue to increase. Aspect ratios of 4: 1 are common and the value will increase further. Aspect ratio as used herein is generally defined as the ratio of the depth of the hole to the narrowest width of the hole near the top surface of the hole. Via widths of 0.18 μm are common and the value will further decrease. For improved copper interconnects formed in oxide dielectrics, the formation of the barrier layer will clearly separate from the nucleation and seed layer. The diffusion barrier may be formed from a bilayer of Ta / TaN, W / WN, or Ti / TiN, or other structures. Barrier thicknesses of 10 to 50 nm are typical. For copper interconnects, it has been found useful to deposit one or more copper layers to perform nucleation and seed functions.

Conventional physical vapor deposition (PVD), the deposition of liner layers or metallization by so-called sputtering, is relatively fast. The DC magnetic sputtering reactor consists of a metal to be sputter deposited and has a target powered by a DC electric source. The magnet is scanned near the back of the target and projects its magnetic field into the reactor portion near the target to increase the plasma density and thus the sputtering rate. However, conventional DC sputtering (called PVD in contrast to the various types of sputtering introduced) mainly sputter neutrons. Typical ion densities in PVD are less than 10 ⁹ cm ^-3 . PVD distributes atoms at a wide angle that is cosine dependent on the target normal. This wide dispersion may be undesirable for filling deep and narrow via holes 122 as shown in FIG. 2, where barrier layer 124 has already been deposited. Multiple off-angle sputter particles cause layer 126 to preferentially deposit around the upper edges of hole 122 to form overhangs 128. Large overhangs further limit the entrance to the hole 122, resulting in inadequate coverage of the sidewalls 130 and the bottom 132 of the hole 122. In addition, the overhangs 128 may form bridges in the holes 122 before being filled and form voids 134 of metallization in the holes 122. Once voids 134 are formed, it is often difficult to reflow the metallization again by heating the metallization near the melting point. Even small voids can lead to reliability problems. If the second metallization deposition step is intended to be plated by electroplating, the bridge overhang makes later deposition more difficult.

One way to ameliorate the overhang problem is long throw sputtering where the sputtering target is relatively far from the wafer or other substrate to be sputter coated. For example, the target to wafer spacing is at least 50%, preferably at least 90%, and more preferably at least 140% of the wafer diameter. As a result, the off-angle portion of the sputtering dispersion is preferentially directed to the chamber wall, while the center angle portion is mostly directed towards the wafer. The truncated angular dispersion causes more of the sputter particles to be deeply directed towards the hole 122, reducing the range of overhang 128. Similar effects can be achieved by placing a collimator between the target and the wafer. Since the collimator has multiple holes of high aspect ratio, the off angle sputter particles hit the side walls of the collimator and the center angle particles pass through. Long throw targets and collimators typically reduce the flux of sputter particles that reach the wafer and reduce the sputter deposition rate. The decrease is more pronounced when the throws are tightened to accommodate through holes of aspect ratios with longer or collimating increases.

In addition, the length by which long throw sputtering can be increased can be limited. In the few millitorrs of argon often used for PVD sputtering, there is a greater possibility of argon sputtering sputtered particles as the target to wafer spacing increases. Thus, the geometric selection of the forward particles can be reduced. Other problems with both long throw and collimation not only reduce the production rate, but also lead to longer deposition periods that tend to increase the maximum temperature experienced by the wafer during sputtering. In another problem, long throw sputtering can decrease on a hang and provide good coverage in the middle and upper portions of the sidewalls, but the lower sidewall and lower coverage are not satisfactory.

Another technique for deep hole lining and filling is to sputter using high density plasma (HDP) in a sputtering process called ionized metal plating (IMP). Typical high density plasmas have an average plasma density of at least 10 ¹¹ cm ⁻³ and preferably at least 10 ¹² cm ⁻³ across the plasma, except for the plasma sheath. In IMP deposition, each plasma source region is formed in an area away from the wafer, for example by inductively coupling RF power to the plasma from an electrical coil wound around the plasma source region between the target and the wafer. The plasma formed in this way is called inductively coupled plasma (ICP). The HDP chamber with this structure is commercially available from Santa Clara Applied Materials, California, as an HDP PVD reactor. Higher power not only ionizes the argon working gas, but also significantly increases the ionization portion of the sputtered atoms. That is, metal ions are generated. The wafer is self charged to negative potential or RF biased to control the DC potential. Metal ions are accelerated across the plasma sheath as they approach the negatively biased wafer. As a result, the angular dispersion peaks strongly in the forward direction, leading deeper into the via hole. Overhangs are much less problematic in IMP sputtering, and the lower coverage and lower sidewall coverage are relatively high.

IMP sputtering using remote plasma is generally performed at higher pressures of 30 millitorr or higher. Higher pressures and high density plasma produce a large number of argon ions that are accelerated across the plasma enclosure towards the surface to be sputter deposited. Argon ion energy is often consumed by heating directly to the film to be formed. Copper is dewed from tantalum nitride and other barrier materials even at elevated temperatures experienced in IMP, ie even at temperatures between 50 and 75 ° C. In addition, argon tends to be embedded in the developing film. IMP can deposit a copper film as shown at 136 in the cross section of FIG. 3 with a rough or discontinuous surface structure. If so, the film may not encourage filling the hole, especially when the liner is used as an electrode for electroplating.

Other techniques for depositing metals are described in U.S. Patent Application 08 / 854,008, filed May 8, 1997 by Fu et al., And U.S. Patent 6,183,614 B1, Serial No. 09 / 373,097, filed August 12,1999 by Fu et al. There is a sustained self sputtering (SSS) as described by, which patent documents are incorporated herein by reference in their entirety. For example, at a sufficiently high plasma density near a copper target, a sufficiently high density of copper ions develops that the copper ions resputter a copper target with a production rate on the unit. The supply of argon working gas can be removed while the copper plasma remains or is reduced to very low pressure. It is believed that aluminum is not easily affected by SSS. Some other materials, such as Pd, Pt, Ag, and Au, may experience SSS.

Depositing copper or other metals by self-maintaining sputtering of copper has a number of advantages. Sputtering speed is high in SSS. There is a large portion of copper ions that can be accelerated toward the biased wafer across the plasma sheath, increasing the directionality of the sputter flux. Chamber pressure can be very low, often limited by the leakage of backside cooling gas, reducing wafer heating from argon ions and reducing scattering of metal particles by argon.

Techniques and reactor structures have been developed to promote self-maintaining sputtering. It has been observed that the sub unity sputters form an advantage from these same techniques and structures, assuming that some sputter materials are not affected by SSS due to partial self sputtering which causes partial self ionizing plasma (SIP). In addition, it is desirable to sputter copper with low but limited argon pressure, although often SSS without any argon working gas can be achieved. Thus, SIP sputtering is the preferred term for many common sputtering processes involving reduced or zero pressure of the working gas such that the SSS is SIP type. SIP sputtering is described in US Pat. No. 6,290,825 to Fu et al. And US Patent Application 09 / 414,614 to Chiang et al. Filed Oct. 8, 1999, which is incorporated herein by reference.

SIP sputtering uses various modifications to conventional capacitively coupled magnetic sputter reactors to generate high density plasma (HDP) adjacent to the target, to expand the plasma and to guide metal ions towards the wafer. A relatively high amount of DC power is applied to the target, for example 20 to 40 kW for a chamber designed for a 200 mm wafer. In addition, the magnet has a relatively small area so that the target power is concentrated in the smaller area of the magnet, increasing the power density supplied to the HDP area adjacent to the magnet. Small region magnets are placed on the center side of the target and rotate near the center to provide more uniform sputtering and deposition.

In one form of SIP sputtering, the magnet has unbalanced poles. That is, the magnetic field lines diverging from the stronger magnetic poles of one magnet polarity surrounding the weaker inner magnetic poles of the other polarity are separated into a vertical magnetic field extending toward the wafer as well as a conventional horizontal magnetic field adjacent to the target plane. Vertical field lines extend toward the wafer and also guide metal ions to the wafer. Moreover, vertical magnetic lines close to the chamber wall serve to prevent the diffusion of electrons from the plasma into the grounded shield. Reduced electron loss is particularly effective in increasing the plasma density and spreading the plasma over the processing space.

SIP sputtering may be performed without the use of an RF coil. The small HDP area is sufficient to ionize with a substantial proportion of the metal ions, estimated to be between 10 and 25%, which effectively sputter coats into deep holes. In particular, at high ionization rates, the ionized sputtered metal atoms concentrate again on the target and further sputter the metal atoms. As a result, the working pressure of argon may be reduced without losing the plasma. Thus, argon heating to the wafer is less problematic, which reduces ion density and randomizes metal ion sputtering patterns.

An additional advantage of the unbalanced magnetrons used in SIP is that electric fields from stronger external annular poles are injected deep into the plasma processing region towards the wafer. This input field has the advantage of providing a strong plasma over much of the plasma processing region and guiding ionized sputter particles to the wafer. Wei Wang, US Patent Application No. 09 / 612,861, filed on July 10, 2000, discloses the use of a coaxial electromagnetic coil that wraps the main portion of the plasma process region to produce a magnetic component that extends from the target toward the wafer. do. Magnetic coils are particularly effective for applying SIP sputtering to long-throw sputter reactors, ie reactors with large spaces between the target and wafer because the auxiliary magnetic field assists the plasma and further guides ionized sputter particles. Lai discloses a small coil in the vicinity of the target in US Pat. No. 5,593,551.

However, SIP sputtering can still be improved. The fundamental problem in this regard is the limited number of variables available for optimizing the magnetic field structure. The magnetron should be small to maximize the target power density, but the target needs to be sputtered uniformly. The magnetic field must have a strong horizontal component near the target to maximize electron trapping. Certain components of the magnetic field are introduced from the target toward the wafer to guide the ionized sputter particles. Wang's coaxial magnetic coil addresses only some of these problems. Horizontally arranged permanent magnets, disclosed in US Pat. No. 5,593,551, do not address this effect in detail.

The metal may be deposited by chemical vapor deposition (CVD) using a metallo-organic precursor such as Cu-HFAC-VTMS, which is an additional adhesive commercially available under the name CupraSelect under the name Schumacher. Thermal CVD processes can be used with such precursors, as is known in the art, but plasma CVD (PECVD) is also available. The CVD process can be used to deposit almost uniform films even in high aspect ratio holes. For example, the film may be deposited by CVD as a thin seed layer, and PVD or other techniques may be used for final hole filling. However, it is found that CVD copper seed layers often become rough. The roughness can be reduced by using it as a seed layer and more specifically as a draw layer that promotes low temperature draw of copper deep into the hole after deposition. The roughness also indicates that a CVD copper layer with a relative thickness on the order of 50 nm is needed to reliably coat the continuous seed layer. For the narrower via holes considered, a CVD copper seed layer of predetermined thickness can almost fill the holes. However, complete filling performed by CVD suffers from central seam, which affects device reliability.

Another related technique uses IMP sputtering, sometimes called flash deposition, to deposit thin copper nucleation layers, with thicker CVD copper seed layers deposited on the IMP layer. However, as shown in Figure 3, the IMP layer 136 may be rough, and the CVD layer usually tends to roughen the substrate. Thus, the CVD layer over the IMP layer tends to be rough.

Electrochemical plating (ECP) is another copper deposition technique to be developed. In this way, the wafer is immersed in a copper electrolyzer. The wafer is electrically biased against the electrolyzer and is then electrochemically deposited on the wafer in a conventional conformal process. Radioless plating techniques are also available. Electroplating and related processes are advantageous because they can be performed with simple equipment at atmospheric pressure, deposition rates are high, and liquid processing is coordinated with continuous chemical physical polishing.

However, electroplating has its own requirements. Seed and adhesive layers are typically provided on top of a barrier layer, such as Ta / TaN, to nucleate the electroplated copper and adhere it to the barrier material. Moreover, conventional insulating structures surrounding the via holes 122 require that an electroplating electrode be formed between the dielectric layer 114 and the via holes 122. Tantalum and other barrier materials are typically relatively low electrical conductors, and conventional nitride sublayers of the barrier layer 124 facing the via holes 122 (containing copper electrolyte) have long transverse current paths required for electroplating. It is much less conductive than Thus, good conductive seeds and adhesive layers are often deposited to facilitate electroplating, which effectively fills the bottom of the bottom hole.

The copper seed layer deposited over the barrier layer 124 is typically used as an electroplating electrode. However, continuous, flat and uniform membranes are preferred. Otherwise, the electroplating current will only be directed to the portion covered with copper and preferentially to the area covered with thick copper. Depositing a copper seed layer has its own problems. The IMP deposited seed layer provides good bottom coverage in the high aspect ratio holes, but its side coverage can be as small as the final thin film and discontinuous. Thin CVD deposited seeds may also be rough. Thick CVD deposited seed layers or CVD copper over IMP copper may require a significantly thick seed layer to achieve the required continuity. In addition, the electroplated electrodes can operate on the entire hole sidewall such that essentially high sidewall coverage is required. Long throws provide adequate sidewall coverage, but lower coverage may not be sufficient.

One embodiment of the invention sputters liner materials such as tantalum or tantalum nitride by combining long-throw sputtering, magnetic ion plasma (SIP) sputtering, inductive couple plasma (ICP) sputtering, and coil sputtering in one chamber. It is about depositing. Long-throw sputtering is characterized by a relatively high ratio of target-to-substrate distance and substrate diameter. Long-throw SIP sputtering is ionized and promotes deep hole coating of neutral deposition material components. ICP sputtering can reduce the thickness of the bottom layer coverage of deep holes to reduce contact resistance. During ICP sputtering, ICP coil sputtering can deposit a protective layer on an area, such as near the hole opening, that does not require thinning by sputtering.

Another feature of the invention relates to sputter deposition of interconnect materials such as copper by combining long-throw sputtering, self-ionized plasma (SIP) sputtering, and SIP resputtering in one chamber. In addition, long-throw SIP deposition promotes deep hole coating of ionized neutral copper components. SIP resputtering can be redistributed to promote good lower edge coverage of deep holes.

SIP tends to be enhanced by low pressures of 5 millitorr or less, especially 2 millitorrs or less, more preferably 1 millitorr or less. Particularly at such low pressures, SIP is promoted by magnetrons with relatively small areas to improve target power density, allowing magnetic fields to penetrate more towards the substrate by using magnetrons with asymmetric magnets. This process can be used to deposit seed layers, which are useful for promoting nucleation or seeding of layers to be deposited later and for forming particularly narrow deep vias or contacts through the dielectric layer. Additional layers can be deposited by electrochemical plating (ECP). In another embodiment, additional layers are deposited by chemical vapor deposition (CVD).

One embodiment includes an array of auxiliary magnets in a magnetron sputter reactor, which is disposed in a chamber proximate the wafer and has a first vertical magnetic field polarity. The magnet may be a permanent magnet or an array of electromagnets with a coil axis along the center side of the chamber.

In one embodiment, the rotatable magnet with a strong external pole of the first magnet polarity surrounds the weak pole of the opposite polarity. The auxiliary magnet is preferably placed in half of the processing space near the wafer to attract the unbalanced portion of the magnetic field from the external magnetic pole towards the wafer.

Resputtering in the SIP chamber may be promoted in multiple embodiments in which the biasing of the wafer is increased during deposition. Alternatively, power to the target may be reduced during deposition to redistribute deposition to the bottom edges of vias and other holes.

There are further features of the present invention to be described below. Accordingly, the foregoing is a summary of some of the embodiments and features of the present invention. Further embodiments and features of the invention are mentioned below. Various modified embodiments can be made without departing from the scope of the present invention. Accordingly, the foregoing summary does not limit the spirit of the invention. The spirit of the invention is determined by the appended claims.

1 is a cross-sectional view of vias filled with metallization covering the top of a dielectric as in the prior art.
2 is a cross sectional view of the via during filling with a metal process clogging over the via;
3 is a cross-sectional view of a via having a rough seed layer deposited by ionized metal plating.
4 is a schematic diagram of a sputtering chamber usable in an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating electrical interconnection of various components of the sputtering chamber of FIG. 4. FIG.
6-9B are schematic diagrams of via liner and metal processing and forming processes for via liner and metal processing in accordance with one embodiment of the present invention.
10 is a cross-sectional view of a sputter reactor including an auxiliary magnet array of the present invention.
FIG. 11 is a bottom plan view of the upper magnet in the sputter reactor of FIG.
12 is an orthographic view of an embodiment of an assembly supporting an auxiliary magnet array.
13 is a schematic cross-sectional view of a sputter reactor in which the auxiliary magnet array comprises an array of electromagnets.
14A and 14B are cross-sectional views of a via seed layer and via seed layer formation process in accordance with an embodiment of the present invention.
Figure 15 is a schematic diagram of another sputtering chamber usable in the present invention.
FIG. 16 is an exploded view of FIG. 15 detailing a target, shield, insulator and target o-ring; FIG.
17 is a graph showing the relationship between the length of the floating shield and the minimum pressure for supporting the plasma.
18 is a cross sectional view of a via metal process in accordance with the present invention.
19 and 20 are graphs showing ion current across the wafer for two different magnets and different operating conditions.
Figure 21 is a cross sectional view of a via metal process in accordance with an embodiment of the present invention.
Figure 22 is a cross sectional view of a via metal process in accordance with another embodiment of the present invention.
Figure 23 is a flow chart of a plasma ignition sequence that reduces the heating of the wafer.
24 is a cross-sectional view of a via metal process formed in accordance with another embodiment of the present invention.
25 is a schematic diagram of a sputtering chamber according to another embodiment of the present invention.
FIG. 26 is a schematic diagram of electrical interconnection of various components of the sputtering chamber of FIG. 25. FIG.
Figure 27 is a schematic diagram of an integrated processing tool to be implemented of the present invention.

The distribution between the sidewalls and the bottom coverage in a DC magnet sputtering reactor can be applied to form a metal layer, such as a liner layer, having the properties required for holes or vias in the dielectric layer. Sputter deposited SIP films with high aspect ratio vias can have adequate sidewall coverage and tend not to span. Preferred bottom coverage may be thinned or removed by ICP sputtering of the underside of the rain. According to one aspect of the invention, the advantages of both sputtering types can be obtained in a reactor combining selected features of SIP and CIP plasma generation techniques that can be implemented in each step. An example of such a reactor is described as 150 in FIG. In addition, the upper portion of the liner layer sidewalls can be protected from resputtering by sputtering an ICP coil 151 disposed in the chamber to deposit coil material onto the substrate.

Reactor 150 may also be used to sputter deposit metal layers, such as barrier or liner layers, preferably in combination but also optionally in combination with both SIP and ICP generated by plasma. The distribution between the ionized neutral atom flux in the DC magnetron sputtering reactor can be tailored to form a coating in the hole or in the dielectric layer. As already mentioned, a sputter deposited SIP film with high aspect-ratio may have desirable top sidewall coverage and does not form an overhang. On the other hand, the ICP generated plasma may have a bottom and a base corner coverage where the sputter deposited film in the hole is good. According to another aspect of the present invention, the advantages of the two types of sputtering can be obtained in a reactor such as reactor 150 that combines with an aspect selected from two deposition techniques. In addition, the coil material can be sputtered so as to be distributed in the deposition layer if necessary.

Reactor 150 and various processes for forming liners, barriers, and other layers are described in pending U.S. Pat. Patent Application No. 10 / 202,778 (Agent No. 4044), which is incorporated by reference in its entirety. As described herein, the reactor 150 of the illustrated embodiment is a DC magnetron type reactor based on a variant of Endura PVD Reactor, available from Applied Materials, Inc. of Santa Clara, California. This reactor includes a vacuum chamber 152 electrically grounded and sealed through a target insulator 154, usually made of metal, to a PVD target 156 having at least a surface portion of material to be sputter deposited onto the wafer 158. do. Although the target sputtering surface is shown planar in the figures, the target sputtering surface (s) can have a variety of forms, including rounded ceilings and cylindrical. Wafers can have different sizes, including 150,200,300,450 mm. The illustrated reactor 150 may be self-ionized sputtering (SIP) in long-throw mode. This SIP mode may be used in one embodiment where coverage primarily affects the sidewalls of the holes. SIP mode can also be used to achieve good base coverage.

The reactor 150 also includes an RF coil 151 that inductively couples RF energy into the interior of the reactor. The RF energy provided by the coil 151 may use a precursor such as argon to maintain plasma to ionize the sputtered deposition material to resputter the deposition layer using ionized argon to thin the base coverage or to improve the base coverage. Ionize the gas. In one embodiment, rather than maintaining the plasma at a relatively high pressure such as 20-60 mTorr during high density IMP processing, the pressure is substantially lower than 1 mTorr during deposition of tantalum nitride or 2.5 mTorr during deposition of tantalum. Is maintained at. However, pressures in the range of 0.1 to 40 mTorr may be appropriate depending on the application. As a result, the ionization rate in reactor 150 will be substantially lower than conventional high density IMP treatment. Such plasma may be used to resputter the deposited layer or to ionize the sputtered deposition material or both. Moreover, the coil 151 may be sputtered to provide a protective coating on the wafer or to provide additional deposition material while resputtering the deposited material onto the wafer for areas where it is undesirable to thin the deposited material. Can be.

In one embodiment, good top sidewall coverage and bottom corner coverage may be achieved in a multi-step process in which little or no RF power is provided to the coil in one step. Thus, in one step, ionization of the sputtered target deposition material will occur primarily as a result of self-ionization. Thus, good top sidewall coverage will be achieved. In the same chamber, preferably in the second step, RF power may be provided to the coil 151, but the pressure is provided to the target low or not at all. In this embodiment, the material is little or no sputtered from the target 156 but ionization of the precursor gas occurs primarily as a result of RF energy inductively coupled to the coil 151. ICP plasma can thin or remove base coverage by etch or resputtering to reduce barrier layer resistance at the bottom of the hole. In addition, the coil 151 may be sputtered to deposit a protective material that is not desirable to be thinned. In one embodiment, the pressure can be kept relatively low so that the plasma density is relatively low to reduce ionization of the sputtered deposition material from the coil. As a result, the sputtered coil material can remain mostly neutral to be deposited primarily over the top sidewall to protect the top sidewall portions from thinning.

Since the illustrated reactor 150 can be self-ionized sputtering, the deposition material can be ionized by sputtering of the target 156 as well as the result of the plasma being held by the RF coil 151. If it is desirable to deposit the layer with good base coverage, the combined SIP and ICP ionization treatments provide sufficiently ionized material for good base and base corner coverage. However, the low ionization rate of the low pressure plasma provided by the RF coil 151 leaves enough neutral sputtering material unionized to deposit over the top sidewall. Thus, the combined source of ionized deposition material can provide both good top sidewall coverage as well as bottom corner coverage, as described in detail below.

In alternative embodiments, good top sidewall coverage, bottom coverage and bottom corner coverage may be achieved in a multi-step process in which little or no RF power is provided to the coil in one step. Thus, in one step, ionization of the deposition material will occur primarily as a result of self-ionization. As a result, good top sidewall coverage can be achieved. In the same chamber, preferably in the second step, RF power may be provided to the coil 151. In addition, in one embodiment, the pressure may rise substantially to maintain a high density plasma. As a result, good base and base corner coverage can be achieved in the second step.

Wafer clamp 160 holds wafer 158 over pedestal electrode 162. The resistive heater, the refrigerant channel, and the heat transfer gas cavity in the pedestal 162 are provided such that the temperature of the pedestal is controlled below -40 degrees Celsius so that the wafer temperature is similarly controlled.

To obtain a deep hole coating with partially neutral flux, the distance between the target 156 and the wafer 158 can be increased to work in a long-throw mode. In this case, the target-to-substrate spacing is typically greater than half the substrate diameter. In the illustrated embodiment, the spacing is greater than 90% of the wafer diameter (190 mm spacing on a 200 mm wafer and 290 mm spacing on a 300 mm wafer), but 80 to greater than 100% and greater than 140% of the substrate diameter. Intervals greater than% may be appropriate. In many applications, a target-to-substrate spacing of 50 to 1000 mm may be appropriate. The long throw of conventional sputtering reduces the sputter deposition rate, but the ionized sputter particles do not significantly decrease.

Darkspace shield 164 and chamber shield 166, separated by second dielectric shield insulator 168, are in chamber 152 to protect chamber wall 152 from sputtered material. Is held. In the illustrated embodiment, dark space shield 164 and chamber shield 166 are grounded. However, in some embodiments, the shield may be floating or biased at the ungrounded level. The chamber shield 166 also functions as an anode ground plane facing the cathode target 156, thereby capacitively supporting the plasma. If the dark space shield is to be electrically floated, some electrons may be deposited over the dark space shield 164 to form a negative charge. The negative potential not only causes the electrons to bounce off so that they are deposited, but also traps the electrons in the main plasma region, thereby reducing electron loss, maintaining low-pressure sputtering and increasing plasma density as needed.

Coil 151 is maintained on shield 164 by a number of coil standoffs 180 that electrically insulate coil 151 from support shield 164. In addition, the standoff 180 causes the conductive material to be repeatedly deposited from the target 110 onto the coil standoff 180 but a complete conductive path of the deposited material from the coil 151 to the shield 164 is formed to form a coil. 151 has a labyrinthine passageway that prevents short circuit to shielding 164 (typically grounded).

To enable the use of a coil, such as a circuit path, RF power passes through the vacuum chamber wall and shield 164 to the coil 151 end. A vacuum feedthrough (not shown) extends through the vacuum chamber to provide RF current from a generator located outside the vacuum pressure chamber. RF power is provided by a feedthrough standoff 182 (FIG. 5) through the shield 164 to the coil 151, where the feedthrough standoff 182 is similar to the coil standoff 180 and the coil It has an entangled passageway to prevent the formation of a path of deposited material from the coil 151 to the shield 164 which may short the 151 with the shield 164.

The plasma dark space shield 164 generally has a cylindrical shape. Plasma chamber shield 166 includes a generally circumferentially oriented wall 190 having a bowl-shape and with standoffs 180 and 182 attached to support coil 151 insulated.

5 schematically shows the electrical connection of the plasma generating apparatus in the illustrated embodiment. To attract ions generated by the plasma, target 156 is negatively biased by variable DC power source 200 at a DC power of, for example, 1-40 kW. Source 200 negatively biases target 156 to about -400 to -600 VDC with respect to chamber shield 166 to ignite and maintain the plasma. Typically target powers between 1 and 5 kW are used to ignite the plasma, but powers greater than 10 kQ are preferred for the SIP sputtering described herein. For example, a target power of 24 kW can be used to deposit tantalum nitride by SIP sputtering and a target power of 20 kW can be used to deposit tantalum by SIP sputtering. During ICP resputtering, the target power can be reduced to, for example, 100-200 watts so that the plasma remains uniform. Optionally, if target sputtering is desired during ICP resputtering, the target power may be maintained at a high level or may be turned off completely if necessary.

Pedestal 162 and wafer 158 may be left electrically floating, but a negative DC self-bias may be formed over the substrate. Optionally, pedestal 162 may be negatively biased at −30 v DC by source 202 to negatively bias substrate 158 to attract ionized deposition material to the substrate. Another embodiment may provide an RF bias to pedestal 162 to control the negative DC bias formed over the substrate. For example, the bias power supply 202 may be an RF power supply operating at 13.56 MHz. In SIP deposition, RF power can be supplied for 20 mm wafers, for example in the range of 10 watts to 5 kW, more preferably in the range of 150 to 300 watts.

One end of the coil 151 passes through the shield 166 by a feedthrough standoff 182 and is insulated coupled to an RF source such as the output of the amplifier and the matching network 204. The input of the matching network 204 is coupled to the RF generator 206, which in this embodiment provides RF power at approximately 1 or 1.5 kW for ICP plasma generation. For example, a power of 1.5 kW for tantalum nitride deposition and a power of 1 kW for tantalum deposition are preferred. Preference is given to a range of 50 watts to 10 kW. During SIP deposition, RF power to the coil can be turned off if necessary. Optionally, RF power can be supplied during SIP deposition if desired.

The other end of the coil 151 is also insulatively coupled to ground through the shield 166 by a similar feedthrough standoff 182 to maintain a DC bias with respect to the coil 151, and is preferably variable. Coupled through blocking capacitor 208, which may be a capacitor. The DC bias and coil sputtering ratio for the coil 151 may be controlled through a DC power source 209 coupled to the coil 151 as disclosed in US Pat. No. 6,375,810. Suitable DC power ranges for ICP plasma generation and coil sputtering include 50 watts to 10 kW. The preferred value during coil sputtering is 500 watts. DC power to coil 151 can be turned off during SIP deposition if desired.

The above mentioned power level may vary depending on the particular application. Computer-based controller 224 may be programmed to control power levels, voltages, currents, and frequencies from various sources, depending on the particular application.

The RF coil 151 may be positioned relatively low in the chamber such that the material sputtered from the coil has a low slope when striking the wafer. As a result, the coil material can be preferably deposited on the upper corners of the holes to protect portions of the holes when the hole base is resputtered by the ICP plasma. In the illustrated embodiment, the coil is preferably located closer to the wafer than the target when the main function of the coil is to generate a plasma to resputter the wafer and provide a protective coating during resputtering. For many applications, coil to wafer spacing of 0 to 500 mm is desirable. However, the actual location may change depending on the specific application. The main function of the coil is in applications where plasma is generated to ionize the deposition material, the coil may be located closer than the target. In addition, as disclosed in detail in U.S. Patent No. 6,368,469 (Attorney Document 1390-CIP / PVD / DV), filed on July 10, 1996, assigned to the assignee of Applicant entitled Plasma Generation Sputtering Coil, It may be located to improve the uniformity of the deposited layer with the sputtered coil material. In addition, the coil may have multiple turns formed of helix or spiral and may have as few turns as one turn to reduce complexity and cost and to facilitate cleaning.

Various coil support standoffs and feedthrough standoffs can be used to insulate the coils. Dielectric insulators typically isolate differently biased portions because sputtering at high power levels, particularly with respect to SSS, SIP, ICP, involves high voltages. Therefore, it is desirable to protect the insulator from metal deposition.

The internal structure of the standoff is entangled and is disclosed in detail in co-pending U.S. Pat. It is. The portion of the standoff directly exposed to the coil 151 and the plasma is made of the same material as the material being deposited. Thus, if the material to be deposited is made of tantalum, the outer part of the standoff is also made of tantalum. To facilitate adhesion of the deposited material, the exposed surface of the metal can be treated by bead blasting to reduce the flow of particles from the deposited material. In addition to tantalum, the coil and target may be made of various deposition materials including copper, aluminum and tungsten. The entanglement should be large enough to prevent the formation of a complete conductive path from the coil to the shield. This conductive path can be formed when the conductive deposition material is deposited over the coil and the standoffs. Depending on the particular application, the size, shape and number of tangled passageways may vary. Factors affecting the tangled structure include the type of material being deposited and the number of depositions needed before the standoff is cleaned or replaced. Suitable feedthrough standoffs can be constructed in a similar manner, except that RF power is applied to the bolt or other conductive member extending to the standoffs.

Coil 151 has overlapping but spaced ends. In this arrangement the feedthrough standoffs 182 at each end are stacked in a direction parallel to the plasma chamber central axis between the vacuum chamber target 156 and the substrate holder 162 as shown in FIG. 4. As a result, RF paths from one end of the coil to the other end of the coil can similarly overlap to avoid voids on the wafer. Such overlapping batches are believed to be able to improve the uniformity of plasma generation, ionization and deposition, as disclosed in co-pending application 09 / 039,695, filed March 16, 1998 and assigned to the assignee of the present application.

Support standoffs 180 are distributed around the remaining coils to provide adequate support. In the described embodiments, the coils have three hub members 504 disposed on each outer surface at 90 degree intervals. It should be appreciated that the number and spacing of standoffs may vary depending on the particular application.

The coils 151 of the described embodiments are each made of 2 × 1/4 inch sturdy bead blast tantalum or copper ribbons formed from a single rotating coil. However, other highly conductive materials and forms may be used. For example, the thickness of the coil may be reduced to 1/16 inch and the width may be increased to 2 inches. Also, in the case where wafer cooling is required, cavity piping may be used in particular.

Suitable RF generators and matching circuits are well known to those skilled in the art. For example, an RF generator such as the ENI Genesis Series with a matching circuit and frequency tracking capability for best frequency matching with the antenna is suitable. The frequency of the generator that generates the RF power in the coil is preferably 2 MHz, but for example 1 A to 200 MHz and other A.C. It is anticipated that the range may vary in frequency. These components may also be controlled by the programmable controller 224.

Returning to FIG. 4, the lower cylinder portion 296 of the chamber shield 166 continues to rise downwards behind the top of the pedestal 162 supporting the wafer 158. And chamber shield 166 extends radially inward at ball portion 302 and is radially spaced outwardly of pedestal 162 at the height of wafer 158 at the deepest cylindrical portion 151 and vertically upwards. Extend.

The shields 164 and 166 are generally made of stainless steel, the inner side of which is bead blasted or roughened to promote adhesion of the sputter deposited material thereon. However, at some point during prolonged sputtering, the deposited material builds up to a thickness that is more likely to peel off, causing harmful particles. Before reaching this point, the shields must be cleaned or replaceable with new ones. However, more expensive insulators 154 and 168 do not need to be replaced in most durations. Moreover, the duration is determined not by the short of the insulators but by the peeling of the shields.

The gas source 314 supplies the sputtering working gas, typically chemically inert rare gas argon, through the mass flow meter 316 to the chamber 152. The working gas is at the top of the chamber or through the gap 318 between the bottom of the shield chamber shield 166 or the chamber shield 166, the wafer clamp 160 and the pedestal 162 as shown. It may be housed in a chamber bottom having one or more inlet pipes through the device. Vacuum pump system 320 connected to chamber 152 via wide pump port 322 maintains the chamber at low pressure. Although the base pressure may be maintained at about 10 ⁻⁷ Torr or lower, the pressure of the working gas is typically maintained at about 1 to 1000 milliTorr in conventional sputtering and less than about 5 milliTorr in SIP sputtering. Computer-based controller 224 controls the reactor including DC target power source 200, bias power source 202 and mass flow meter 316.

To provide effective sputtering, a magnetron 330 is placed behind the target 156. The magnetron 330 faces the magnets 332, 334 connected and supported by the magnetic yoke 336. The magnets form a magnetic field adjacent to the magnetron 330 in the chamber 152. The magnetic field traps electrons and the ion density also increases with respect to the neutral charge, forming a high density plasma region 338. The magnetron 330 is usually rotated about the center 340 of the target 156 by the motor drive shaft 342 to achieve full coverage in the sputtering of the target 156. In order to achieve high density plasma 338 of sufficient ionization density to enable self-maintaining sputtering, the power density delivered to the region adjacent to magnetron 330 may be high. This may be accomplished by increasing the power level delivered from the DC power source 200 and reducing the area of the magnetron 330, for example in the form of a triangle or track, as disclosed by Fu and Chiang in the cited patent above. The 60 degree triangular magnetron whose tip is nearly coincident with the target center 340 at any time covers only about one sixth of the target. In conventional reactors capable of SIP sputtering, a quarter of coverage is the desired maximum.

In order to reduce the electron loss, the inner magnetic poles represented by the inner magnet 332 and the magnetic pole surface should be surrounded by the outer magnetic poles 334 and the continuous outer magnetic poles represented by the pole surface without significant holes. In addition, in order to guide the ionized sputter particles to the wafer 158, the external stimulus must generate a much higher magnetic flux than the internal stimulus. The extending magnetic field lines trap electrons and expand the plasma closer to the wafer 158. The flux ratio should be at least 150%, preferably greater than 200%. Two embodiments of Fu's triangular magnetrons have six or ten inner magnets and twenty-five outer magnets of equal intensity but opposite polarity. Although described in conjunction with a two-dimensional target surface, various unbalanced magnetrons can be used in various target shapes to generate a self-ionizing plasma. The magnets may have shapes other than triangles, including circular or other shapes.

When argon is received in the chamber, the DC voltage difference between the target 156 and the chamber shield 166 burns argon in the plasma, and positively charged argon ions are attracted to the negatively charged target 156. The ions impinge upon the target 156 with significant energy causing the target atoms or atomic clusters to be sputtered from the target 156. Some of the target particles are deposited by impinging on the wafer 158, thereby forming a film of the target material. In reactive sputtering of metal nitride, nitrogen is further received from source 343 into the chamber, which reacts with the sputtered metal atoms to form metal nitride on wafer 158.

6-9B show a continuous cross sectional view of the liner layer formation according to one aspect of the present invention. Referring to FIG. 6, an interlayer dielectric 345 (eg, silicon dioxide) is deposited on the first metal layer (eg, first copper layer 347a) of interconnect 348 (FIG. 9B). Vias 349 are then etched into interlayer dielectric 345 to expose first copper layer 347a. The first metal layer may be deposited using CVD, PVD, electrolytic plating or other known metal deposition methods, and is connected by contact through a dielectric layer to a device formed in the underlying semiconductor wafer. The first copper layer may be moved, such as when a wafer is moved from an etching chamber in which the oxide plating the first copper layer is etched to form a hole for forming a via between the first copper layer and the second copper layer on which the metal layer is deposited. Once 347a is exposed to oxygen, it is easy to form an insulating / high resistance copper oxide layer 347a'on it. Thus, to reduce the resistance of the copper interconnect 348, any copper oxide layer 347a ′ and any processing byproducts in the vias 349 are removed.

Prior to removing the copper oxide layer 347a ′, a barrier layer 351 is deposited over the interlayer dielectric 345 and over the exposed first copper layer 347a (eg, in the sputtering chamber of FIG. 4). The barrier layer 351, which preferably comprises tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride, then prevents the deposited copper layers from bonding to the interlayer dielectric 345 and deteriorating (as previously described).

For example, if the sputtering chamber 152 is configured for deposition of a tantalum nitride layer, a tantalum target 156 is employed. In general, both argon and nitrogen gas enter the sputtering chamber 152 through a gas inlet 360 (a number of inlets, one for each gas, can be used), while the DC power source 200 supplies the target 156 to the target 156. The power signal is applied. Optionally, the power signal may also be applied to the coil 151 by the first RF power source 206. During steady state processing, nitrogen reacts with the tantalum target 156 to form a nitride film on the tantalum target 156 so that tantalum nitride is sputtered. In addition, non-tantalum nitride atoms are also sputtered from the target, and the atoms combine with nitrogen to form tantalum nitride on a staircase or on a wafer (not shown) supported by pedestal 162.

In operation, a throttle valve effectively connected to the outlet 362 is placed in a central position to maintain the deposition chamber 152 at a desired low vacuum level of about 1 × 10 ⁻⁸ before the processing gas (es) enter the chamber. To begin processing in the sputtering chamber 152, a mixture of argon and nitrogen gas is introduced into the sputtering chamber 152 through the gas inlet 360. DC power is applied to the tantalum target 156 by the DC power supply 200 (while the gas mixture continues to enter the sputtering chamber 152 by the gas inlet 360 and is discharged therefrom by the pump 37). ). DC power applied to the target 156 causes the argon / nitrogen gas mixture to form a SIP plasma and is attracted to the target 156 to impinge on the target 156 causing the target material (eg tantalum and tantalum nitride) to be discharged therefrom and Generate nitrogen ions. The discharged target material is transferred to and deposited on the wafer 158 supported by the pedestal 162. In accordance with the SIP process, the plasma generated by the unbalanced magnetron ionizes some of the sputtered tantalum and tantalum nitride. By adjusting the RF power signal applied to the substrate support pedestal 162, a negative bias can be formed between the substrate support pedestal 162 and the plasma. A negative bias between the substrate support pedestal 162 and the plasma generates tantalum ions, tantalum nitride ions, and argon ions to accelerate towards the pedestal 162 and any wafer supported thereon. Thus, neutral and ionized tantalum nitride is deposited on the wafer, providing good sidewall and top sidewall coverage due to SIP sputtering. In addition, if RF power is selectively applied to the ICP coil, tantalum nitride material from the target 156 may be deposited on the wafer while the wafer may be sputter-etched by argon ions (ie, simultaneous deposition / sputter-etching). ).

Following deposition of the barrier layer 351, if it is desired to thin or remove the bottom, a portion of the barrier layer 351 at the bottom of the via 349 and the copper oxide layer 347a 'underneath (and any treatment) Residue) can be sputter-etched or resputtered by an argon plasma as shown in FIG. 7. It is preferable to generate argon plasma mainly at this stage by applying RF power to the ICP coil. During sputter-etching in the sputtering chamber 152 (FIG. 4) in this embodiment, the power applied to the target 156 may be at a low level (eg, 100 or less) to inhibit or prevent significant deposition from the target 156. 200 W) is preferably moved or reduced. Lower target power levels than target-free power can provide a more uniform plasma and are currently desirable.

ICP argon ions are driven by an electric field (e.g., an RF signal applied to the substrate support pedestal 162 by the second RF power supply 41 of FIG. 4, which causes a negative magnetic bias to form on the pedestal). A portion of barrier layer 351 that is accelerated toward barrier layer 351 and impinges upon barrier layer 351 and sputters barrier layer material from the base of the via hole due to propulsion transfer and coats the sidewall of via 349. Redistribute along. Argon ions are attracted in a direction almost perpendicular to the substrate. As a result, sputtering of the via sidewall hardly occurs and significant sputtering of the via base occurs. To facilitate resputtering, the bias applied to the pedestal and the wafer is, for example, 400 watts.

Specific values of the resputtering process parameters may vary depending on the particular application. Co-pending application or pending application No. 08 / 768,058; 09 / 126,890; 09 / 449,202; 09 / 846,581; 09 / 490,026; And 09 / 704,161 disclose a resputtering process, the entirety of which is incorporated herein by reference.

According to another feature of the invention, the ICP coil 151 is formed and sputtered in the same manner as the target 156 and sputtered to deposit tantalum nitride on the wafer and at the same time the via bottom is resputtered. Due to the relatively low pressure during the resputtering process, the ionization rate of the deposited material sputtered from the coil 151 is relatively low. Therefore, the sputtering material deposited on the wafer is mainly neutral material. In addition, the coil 151 surrounds the wafer in the chamber and is positioned relatively low.

Thus, the trajectory of the material sputtered from the coil 151 tends to have a relatively small angle of incidence. Therefore, the material sputtered from the coil 151 tends to deposit on the layer 364 around the wafer surface and the openings of the holes or vias in the wafer rather than depth in the wafer holes. This deposition material from coil 151 is used to provide some protection from resputtering so that the barrier layer becomes thinner by resputtering the bottom of the hole rather than over the sidewalls and around the hole opening where it is undesirable to thin the barrier layer.

When barrier layer 351 is sputter-etched from the via base, argon ions impinge upon the copper oxide layer 347a ', the oxide layer is sputtered to redistribute the copper oxide layer material from the via base, and some or all of the sputtering material Is deposited along a portion of the barrier layer 351 that coats the sidewalls of the vias 349. Copper atoms 347a ″ also coat barrier layers 351 and 364 disposed on the sidewalls of vias 349. However, the originally deposited barrier layer 351, which causes redistribution from the via base to the via sidewalls, may be coated with copper atoms ( Since it is a diffusion barrier for 347a ", the copper atoms 347a" are almost floating within the barrier layer 351 and are inhibited from reaching the interlayer dielectric layer 345. Thus, copper atoms 347a deposited on the sidewalls ") Generally does not generate via to via leakage current when redistributed on uncoated sidewalls.

Thereafter, a second liner layer 371 of a second material, such as tantalum, is deposited on the previous barrier layer 351 in the same chamber 152 or similar chamber having both SIP and ICP capabilities (FIG. 8). The tantalum liner layer provides good adhesion between the underlying tantalum nitride barrier layer and the metal interconnect layer of the conductor, such as deposited copper. However, in some applications it may be desirable to deposit only the barrier layer or only the liner layer prior to seed layer or hole filling.

The second liner layer 371 may be deposited in the same manner as the first liner layer 351. That is, tantalum liner 371 may be deposited in a second SIP step where plasma is first generated by the target magnetron 330. However, nitrogen does not allow tantalum other than tantalum nitride to be deposited. According to SIP sputtering, good sidewall and top sidewall coverage can be achieved. RF power to the ICP coil 151 can be reduced or eliminated if desired.

After deposition of the tantalum liner layer 371, the liner layer 371 portion (and any treatment residues) at the bottom of the underlying via 349 is desired to be thinned or removed from the bottom, as shown in FIG. 9A, a liner layer. Sputter-etched or re-sputtered by an argon plasma in the same manner as the bottom of 351. Argon plasma is preferably generated at this stage preferentially by applying RF power to the ICP coil. Again, upon sputtering-etching in the sputtering chamber 152 (FIG. 4), the power applied to the target 156 is removed or reduced to a low level (e.g., 500W) to reduce the bottom coverage of the second liner layer 371. During thinning or removal, many depositions to the target 156 can be stopped or prevented. In addition, the coil 151 is preferably sputtered to deposit the liner material 374 while re-sputtering the layer bottom with argon plasma to prevent the liner sidewalls and tops from becoming nearly thin during bottom re-sputtering. .

In the above embodiment, SIP deposition of the target material on the sidewalls of the via is performed preferentially in one step, and ICP re-sputtering of the via bottoms and ICP deposition of the coil 151 are performed first in sequential steps. If desired, it should be understood that deposition of the target material and coil material on the sidewalls of the via 349 may be performed simultaneously. Also, it should be understood that if desired, ICP sputtering-etching of the deposited material on the bottom of the via 349 may be performed concurrently with the deposition of the coil material of the target and sidewalls. Simultaneous deposition / sputter etching may be performed with the chamber 152 of FIG. 4 by adjusting power signals applied to the coil 151, the target 156, and the pedestal 162. Since the coil 151 can be used to maintain the plasma, the plasma can sputter onto the wafer with a low relative bias on the wafer (less than necessary to maintain the plasma). When the sputtering threshold is reached, the ratio of RF power ("RF coil power") applied to the wire coil 151 as compared to the DC power ("DC target power") applied to the target 156 for a particular wafer is It affects the relationship between sputtering-etching and deposition. For example, due to increasing ionization into the wafer and sequentially increasing ion bombardment, the higher the RF: DC power ratio will result in more sputtering-etching. Increasing the wafer bias (eg, increasing the RF power supplied to the support pedestal 162) increases the energy of the input ions, which increases the sputtering yield and etch rate. For example, increasing the voltage level of the RF signal applied to the pedestal 162 increases the ion energy generated on the wafer while increasing the duty cycle of the RF signal applied to the pedestal 162. Increasing the duty cycle increases the number of generated ions.

Thus, both the voltage level and duty cycle of the wafer bias can be adjusted to control the sputtering rate. Maintaining the DC target power also reduces the amount of barrier material available for deposition. Zero DC target power results only in sputtering-etching. The low DC target power coupled with the high RF coil power and wafer bias allows simultaneous via sidewall deposition and via bottom sputtering. Thus, processing for materials and geometries can be coordinated. For vias of typically 3: 1 aspect ratio on 200mm wafers, tantalum or tantalum nitride is used as barrier material, and DC target power of 500W to 1kW, RF coil power of 2 to 3kW or more, and wafer bias of 250W to 400W are applied simultaneously. Once generated (eg, 100% duty cycle), barrier deposition on wafer sidewalls and removal of material from the via bottom can occur. Lowering the DC target power results in less material deposited on the sides. Higher DC target power requires more RF coil power and / or wafer bias power to sputter the bottom of the via. A 2 kW RF coil power level on coil 151 and a 250 W RF wafer power level with 100% duty cycle on pedestal 162 may be used, for example, to perform deposition / sputtering-etching simultaneously. Initially during simultaneous deposition / sputtering-etching (e.g., a few seconds or depending on specific geometries / materials) so as to prevent contaminants of the sidewalls by sputter-etched material from the via bottom through sufficient via sidewall coverage. It may be desirable not to apply any wafer bias).

For example, if no wafer bias is initially applied during simultaneous deposition / sputtering-etching of vias 349, it facilitates the formation of an initial barrier layer on the sidewalls of interlayer dielectric 345, and sputtered copper atoms. To prevent contamination of the interlayer dielectric 345 during subsequent deposition / sputtering-etching operations. Optionally, the deposition / sputtering-etch may be performed “sequentially” in the same chamber, or deposit the barrier layer 351 in the first processing chamber and separate a second processing chamber (eg, Applied Materials). May be performed "sequentially" by sputter-etching the barrier layer 351 and the copper oxide layer 374a 'in a sputter-etching chamber, such as a Preclean II chamber.

After deposition of the second liner layer 371 and thinning of the bottom coverage, a second metal layer 347b is deposited to form the copper interconnect 348 (FIG. 9B). The second copper layer 347b is coated or copper plug 347b 'over the second liner layer 371 and over the portion of the first copper layer 347a exposed at the base of each via, as shown in FIG. 9B. Can be deposited as. The copper layer 347b may include a copper seed layer. Since the first and second copper layers 347a, 347b are in direct contact rather than contacting through the barrier layer 351 or the second liner layer 371, the resistance of the copper interconnect 348 may be reduced. And via-to-via leakage current can be reduced. However, it should be understood that in some applications, it may be desirable to leave both coatings on the bottom of the liner layer or barrier layer or vias.

If the interconnect is formed of a conductor metal different from the liner layer or layers, the interconnect layer may be deposited in a sputtering chamber having a target of a different conductor metal. The sputter chamber may be of SIP type or ICP type. However, the deposition of current copper seed layers is preferably done in a chamber of the type described below in connection with FIG. 10. The metal interconnect may be deposited in other ways in other types of chambers and apparatus, including CVD and electrochemical plating.

The copper seed layer may be deposited by another plasma sputtering reactor 410 as shown in the conceptual cross sectional view of FIG. 10. Reactor 410 and various processes for forming seed and other layers are disclosed in co-application serial number 09 / 993,543 (attorney docket No. 6265), filed November 14, 2001, which is incorporated by reference in its entirety. It is included in the present invention. As described in this application, the vacuum chamber 412 includes generally cylindrical sidewalls 414, which sidewalls 414 are electrically grounded. Typically, grounded replaceable shields, not shown, are disposed inside the sidewalls 414 to prevent the sidewalls 414 from being sputter coated, but the shields act as chamber sidewalls except for vacuum retention. do. The sputter target 416 composed of the metal to be sputtered is sealed to the chamber 412 through the electrical insulator 418. The pedestal electrode 422 supports the substrate 424 to be sputter coated opposite the target 416 in parallel. Processing space is defined between the target 416 and the substrate 424 inside the shields.

The sputtering working gas, preferably argon, is metered into the chamber from the gas supply 426 via a mass flow controller 428. A vacuum pumping system, not shown, typically maintains inside the chamber 412 at a very low base pressure of 10 ⁻⁸ Torr or less. During plasma ignition, the argon pressure is supplied in an amount that produces a chamber pressure of approximately 5 milliTorr, but as described below, this pressure is then reduced. DC power source 434 negatively biases target 416 to approximately -600 VDC such that the argon working gas is excited with a plasma containing electrons and positive argon ions. Positive argon ions are attracted to the negatively biased target 416 and sputter metal atoms from the target.

The present invention is particularly useful for SIP sputtering in which a small nested magnetron 436 is supported on an unshown back plate behind the target 416. Chamber 412 and target 416 are generally circular symmetric about central axis 438. SIP magnetron 436 includes an inner stimulus 440 with a first vertical magnetic polarity and an outer stimulus 442 surrounding the circumference with a second vertical magnetic polarity opposite. Both magnetic poles are supported by a magnetic yoke 444 and are magnetically coupled through the magnetic yoke 444. The yoke 444 is secured to a rotation arm 446 supported on a rotation axis 448 extending along the central axis 438. Motor 450 coupled to shaft 448 causes magnetron 436 to rotate about central axis 438.

In an unbalanced magnetron, the integrated total magnetic flux over the area produced by the external magnetic pole 442 is greater than that generated by the internal magnetic pole 440, and preferably of at least 150% of magnetic strength. Has a ratio. Opposing magnetic poles 440, 442 form a magnetic field inside chamber 412, which forms a high density plasma at the face of the target to increase the sputtering rate and increase the ionization rate of the sputtered metal atoms, It is semi-toroidal with strong components parallel to the face of the target 416. Since the outer stimulus 442 is magnetically stronger than the inner stimulus 440, the magnetic field portion from the outer stimulus 442 is not looped back behind the outer stimulus 442 to complete the magnetic circuit. It protrudes away toward the pedestal 422.

For example, an RF power source 454 with a frequency of 13.56 MHz is connected to the pedestal electrode 422 to form a negative self-bias on the substrate 24. The bias attracts positively charged metal atoms across the sheath of the adjacent plasma, thereby coating the sides and bottom of high aspect ratio holes of the substrate, such as inter-level vias.

In SIP sputtering, the magnetron is small, has high magnetic strength, and a high amount of DC power is applied to the target so that the plasma density rises above 10 ¹⁰ cm ⁻³ near the target 416. In the presence of this plasma density, many sputtered atoms are ionized with positively charged metal ions. The metal ion density is high enough to attract a large number of metal ions behind the target to sputter metal ions further away. As a result, the metal ions can at least partially replace argon ions as an effective species in the sputtering process. That is, the argon pressure can be reduced. The reduced pressure has the advantage of scattering and deionization of metal ions. For copper sputtering, under certain conditions it is possible to completely remove argon working gas in a process called sustained self-sputtering (SSS) once the plasma is ignited. For aluminum or tungsten sputtering, SSS is not possible, but the argon pressure can be significantly reduced to, for example, 1 milliTorr or less from the pressure used in conventional sputtering.

In one embodiment of the invention, the secondary array 460 of permanent magnets 462 is disposed around the chamber sidewalls 414 and generally disposed in half of the processing space towards the substrate 424. In this embodiment, the auxiliary magnets 462 have the same first perpendicular magnetic polarity as the external magnetic pole 442 of the inclusion magnetron 436 to pull off the unbalanced portion of the magnetic field from the external magnetic pole 442. In the embodiment described in detail below, there are eight permanent magnets, but any number of four or more distributed around the central axis 438 will similarly provide good results. It is possible to place the auxiliary magnets 462 inside the chamber sidewalls 414 but preferably outside the thin sidewall shield to increase the effective strength in the processing area. However, placement outside the sidewalls 414 is desirable for the overall processing result.

The auxiliary magnet array is disposed generally symmetrically about a central axis 438 to create a circular symmetric magnetic field. On the other hand, the inclusion magnetron 436 has a magnetic field distribution asymmetrically disposed about the central axis 438, which becomes symmetrical when averaged over the rotation time. There are many forms of embedded magnetrons 436. A less desirable but simplest form is one having a button center pole 440 surrounded by a rounded annular external magnetic pole 442, such that the magnetic field is symmetrical about the axis displaced from the chamber axis 438. The inclusion magnetron axis is rotated about the chamber axis 438. The preferred inclusion magnetron, shown in the bottom plan view of FIG. 11, is triangular, has a vertex near the central axis 438 and a base near the outer periphery of the target 416. This form is particularly advantageous because the time average of the magnetic field is more uniform than the circularly embedded magnetron.

The effective magnetic field at a particular moment during the rotation cycle is shown by the dashed line in FIG. The semi-toroidal magnetic field B _M provides a strong horizontal component that is close to the surface of the target 16 and parallel to the surface of the target 16, thereby adjusting the density of the plasma, the sputtering rate, and the ionization rate of the sputtered particles. Increase. The auxiliary magnetic fields B _A1 , B _A2 are the sum of the magnetic fields from the auxiliary magnet array 460 and from the unbalanced portion of the embedded magnetron 436 magnetic field. On the side of the chamber away from the inclusion magnetron 436, component B _A1 from the unbalanced portion of the inclusion magnetron 436 magnetic field prevails, which does not extend far towards the substrate 424. However, near the chamber sidewall 414 on the side of the inclusion magnetron 436, the auxiliary magnet 462 is strongly coupled to the external magnetic pole 442, resulting in magnetic field component B _A2 protruding away toward the substrate 424. do. In the illustrated plane, the magnetic field component is a combination of two components B _A1 , B _A2 .

This structure is due to the alignment of the magnetic polarities of the auxiliary magnets 442 with the strong external magnetic poles 442 and thus the chamber sidewall 414 in the region just below the nested magnetron 436 where a strong vertical magnetic field sweeps around the chamber sidewall. Resulting in near the chamber sidewall 414 along a significant length of < RTI ID = 0.0 > As a result, there is a strong vertical magnetic field on the outer side of the chamber 412 adjacent to the region of the most strongly sputtered target 416. This projecting field is effective in extending the area of the plasma and directing ionized particles to the substrate 424.

The auxiliary magnet array 460 can be implemented using two semicircular magnet carriers 470, one of the magnet carriers being illustrated in orthogonality in FIG. 12. Each carrier 470 includes four recesses 472 facing inside the carrier and sized to receive each magnet assembly 474 including one magnet 462. The magnet assembly 474 includes an arc-shaped upper clamp member 476 and a lower clamp member 478, wherein the clamp members have two screws 480 for the two clamp members 476, 478. When tightened together, it captures a cylindrical magnet 462 into the recesses. Carriers 470 and clamp members 476 and 478 may be formed of a nonmagnetic material such as aluminum. The lower clamp member 478 has a length that fits into the recess 472, but the upper clamp member 476 has ends extending beyond the recess 472, and two penetrations through the upper clamp member 476. Hole 482 is drilled. Two screws 484 pass through respective through holes so that the screw 484 is secured to the tapped holes 486 in the magnet carrier 470, thereby placing the magnet 462 in place on the magnet carrier 470. Fix it. The two semicircular magnet carriers 470 assembled as above are arranged in a ring around the chamber wall 414 and fixed to the chamber wall by conventional fastening means. This structure places the magnets 462 directly adjacent to the exterior of the chamber wall 414.

The solenoid magnetic field formed in Wei Wang's electromagnetic coil is considerably more uniform across the diameter of the reactor chamber than the cylindrical dipole magnetic field formed by the annular array of permanent magnets. However, as shown in the cross-sectional view of FIG. 13, it is possible to form a bipolar magnetic field of similar type by replacing the permanent magnets 462 with an annular array of electromagnetic coils 490 disposed around the perimeter of the chamber wall. . Coils 490 are typically wound spirally about each axis parallel to center axis 438 and are electrically powered to create a nearly identical dipole magnetic field inside the chamber. Such a design has the advantage of allowing quick adjustment of the auxiliary magnetic field strength and the magnetic field polarity.

The present invention has been applied to SIP sputtering of copper. Conventional SIP reactors sputter copper films with a 9% non-uniformity determined by sheet resistance measurements, while auxiliary magnetrons can be optimized to produce only 1% non-uniformity. Improved uniformity can be obtained at the expense of reduced deposition rate, but for the deposition of thin copper seed layers in deep holes, lower deposition rates may be desirable for better process control.

Although the present invention discloses the use of a SIP sputter reactor, the auxiliary permanent magnet array is a SIP * reactor of US Pat. No. 6,251,242, a hollow cathode target of US Pat. No. 6,179,973 or July / August 2000, Cloun et al., J. Vac. Sci Technology's "Ionized Physical-Gas Deposition Using Hollow-Chode Magnetron Sources for Improved Metallization", Inductively Coupled IMP Reactors of U.S. Patent 6,045,547, or "Ion Reflectors, e. Other methods, such as magnetic ion sputtering (SIS) systems, which use ion reflectors to control ion flux to a substrate, as described in "Cu Dual Damasine Treatment for 0.13 Micrometer Technology Generation with Magnetic Ion Sputtering (SIS) It can be preferably applied to the target and the power devices. Other magnetron devices may be used, such as balanced magnetrons and fixed magnetrons. In addition, the polarity of the auxiliary magnets may or may not be parallel to the magnetic polarity of the outer pole of the upper magnetron. Other materials, including Al, Ta, Ti, Co, W and the like, nitrides of some of these refractory metals can be sputtered.

Thus, the secondary low speed array provides additional control of the magnetic field useful for magnetron sputtering. However, in order to achieve deeper hole coating with partially neutral flux, it is desirable to increase the distance between target 416 and wafer 424, ie operate in long-throw mode. . As discussed above in connection with the chamber of FIG. 4, in long-throw, the target-to-substrate spacing is typically greater than half the substrate diameter. When used for SIP copper seed deposition, larger than 140% wafer diameter (eg 290mm spacing) for 200mm wafers, larger than 130% for 300mm wafers (eg 400mm spacing), but 90% of substrate diameter and Intervals greater than 80% are considered appropriate, including greater than 100%. In many applications, it is determined that a target for a wafer spacing of 50 to 1000 mm is suitable. The long-throw of conventional sputtering reduces the sputtering rate, but ionized sputter particles do not cause so much reduction.

One embodiment of a structure that may be formed by the chamber of FIG. 4 and the chamber of FIG. 10 is a via shown in cross-section in FIG. 14A. The seed copper layer 492 is deposited into the chamber of FIG. 10 in the via hole 494 over the liner layers formed in the chamber of FIG. ) And one or more barrier and liner layers, such as Ta liner layers 371 and 374. SIP copper layer 492 may be deposited, for example, with a blanket thickness of 50 to 300 nm, preferably 80 to 200 nm. SIP copper seed layer 492 preferably has a thickness in the range of 2-20 nm, more preferably 7-15 nm, on the via sidewalls. In view of narrow holes, sidewall thicknesses greater than 50 nm may not be optimal for some applications. The quality of the film can be improved in some applications by reducing the pedestal temperature below 0 ° C, preferably below -40 ° C. In such applications, rapid SIP deposition is an advantage.

For example, if the sputtering chamber 410 is configured for deposition of copper layers, a copper target 416 is used. In operation, the throttle valve, which is operated in conjunction with the chamber exhaust outlet, is adapted to maintain the deposition chamber 410 at a desired low vacuum level of about 1 × 10 ⁻⁸ torr, prior to the inlet of the processing gas (s) into the chamber. Is placed in position. Argon gas is introduced into the sputtering chamber 410 through the gas inlet 428 to start processing in the sputtering chamber 410. For the deposition of copper seeds in long throw SIP chambers, very low pressures such as 0-2 mTorr are preferred. In the embodiment shown, a pressure of 0.2 mTorr is suitable. DC power is applied to the copper target 416 through the DC power supply 434 (gas mixture continues to enter the sputtering chamber 410 through the gas inlet 360 and pumped therefrom through a titration pump). The power applied to the target 416 may range from 20-60 kW for a 200 mm wafer, copper target. As an example, the power supply 434 may apply 38 kW to the copper target 416 at a −600 V DC voltage. For large wafers, such as 300 mm wafers, it should be expected that larger values, such as 56 kW, may be suitable. Other values may be used depending on the particular application.

The DC power applied to the target 416 causes argon to form a SIP plasma, generates attached argon ions, and collides with the target 416 such that the target material (eg, copper) is discharged. The ejected target material moves and is deposited on the wafer 424 supported by the pedestal 422. Following SIP treatment, the plasma generated by the unbalanced magnetron ionizes a portion of the sputtered copper. By adjusting the RF power signal applied to the substrate support pedestal 422, a negative bias can be generated between the substrate support pedestal 422 and the plasma.

Power applied to pedestal 422 may range from 0-1200 W for copper seed deposition. As an example, the RF power supply 454 may apply 300 W to the pedestal 422 for a 200 mm wafer. For larger wafers, such as 300 mm wafers, it should be expected that larger values may be suitable. Depending on the particular application, other values may be used.

A negative bias between the substrate support pedestal 422 and the plasma causes copper ions and argon ions to be accelerated toward the pedestal 422 and the wafer supported thereon. Thus, neutral and ionized copper can be deposited on the wafer and can provide good bottom, sidewall and copper sidewall coverage upon SIP sputtering. In addition, the wafer may be sputter-etched by argon ions (ie, simultaneous deposition / sputtering-etch) while copper material is deposited on the wafer from the target 416.

After or during the deposition of the seed layer 492, the portion of the seed layer 492 at the bottom 496 of the via 494 may be sputter-etched through the argon plasma, as shown in FIG. 14B, if desired for redistribution of the bottom. Or re-sputtered. Bottom 496 may be redistributed to increase the coverage thickness of bottom corner regions 498 of the copper seed layer, as shown in FIG. 14B. In many applications, the copper seed layer bottom 496 is preferably not completely removed to provide proper seed layer coverage through the vias.

The argon plasma is preferably generated in this re-sputtering step as a SIP plasma by applying power to the target and pedestal. SIP argon ions are driven by an electric field (eg, an RF signal applied to the substrate support pedestal 422 through the second RF power supply 454 of FIG. 10 to form a negative self bias on the pedestal). Seed layer 492 accelerated toward seed layer 492, impinging on seed layer 492, and due to momentum transition, sputtering the seed layer material from the base of the via opening and coating it to the bottom corners of via 349. Redistribute along portion 498.

Argon ions are attached to the substrate in a direction substantially perpendicular thereto. Thus, there is little sputtering of the via sidewalls, but substantially sputtering of the via base occurs. In this embodiment, during the sputtering of the copper seed layer in the sputtering chamber 410 (FIG. 10), the power applied to the pedestal 422 is increased to a higher value, such as 600-1200 W, or 900 W, for example. , Redistribution of the bottom of a copper seed layer can be made easy. Thus, in this example, the pedestal power is raised from a level below 600W (eg 300W) to a level greater than 600W (eg 900W) to enhance the redistribution effect of re-sputtering.

As another example, the power applied to the target 416 may be reduced to a lower value, such as, for example, 30 kW to 28 kW, to stop deposition from the target 416 to facilitate redistribution of the bottom of the copper seed layer. have. Except for the absence of target power, a lower target power level can provide a more uniform plasma, which is desirable in the embodiments described above where current target power is reduced for seed layer bottom redistribution. Thus, in this example, the target power is lowered from a level above 30000 (eg 39 kW) to a level below 30000 (eg 28 kW) to improve re-sputtering.

As another example, re-sputtering of the bottom of the copper seed layer is performed simultaneously through copper seed layer deposition such that the target and pedestal power levels can be maintained relatively constant (such as 38 kW and 300 W, respectively) during seed layer deposition. Can be. In other embodiments, target power reduction may be optional or may be increased in combination with pedestal power to facilitate seed layer bottom redistribution.

Certain values of the re-sputtering processing parameters may vary depending on the particular application. Co-filed or issued applications 08 / 768,058; 09 / 126,890; 09 / 449,202; 09 / 846,581; 09 / 490,026; And 09 / 740,161 disclose re-sputtering processes, the entirety of which is incorporated herein by reference.

SIP copper seed layer 492 has good bottom and sidewall coverage and has improved bottom corner coverage. After the copper seed layer 492 is deposited, the hole is filled into the copper layer 18, as in FIG. 1, preferably by electrochemical plating, using the seed layer 492 as one of the electroplating electrodes. Optionally, the smooth structure of the SIP copper seed layer 492 also promotes reflow or high temperature deposition of copper by standard sputtering or physical vapor deposition (PVD).

The chambers of FIGS. 4 and 10 utilize ionization and neutral atomic flux. As disclosed in US Pat. No. 6,398,929 (attorney docket No. 3920), which is hereby incorporated by reference in its entirety, the bonsai between ionization and neutral atomic flux in a DC magnetron sputtering reactor can be adjusted to produce the desired layer in the hole of the dielectric layer. . Such layers may be used in combination with or as a copper seed layer deposited by chemical vapor deposition (CVD) on top of the sputtered copper neutron layer. The copper liner layer is particularly useful as a thin seed layer for electroplated copper.

Prior art DC magnetron sputtering reactors have been directed to conventional working gas sputtering or self-maintaining sputtering. The two methods emphasize different forms of sputtering. On the other hand, the reactor for the copper liner preferably combines various prior art features for controlling the distribution between ionized copper atoms and neutrons. As an example the reactor 550 is shown in the conceptual cross sectional view of FIG. 15. The reactors of FIGS. 4, 10 and 13 may utilize these features of the reactor of FIG. 15 based on a modification of the Endura PVD reactor available from Applied Materials, Inc. of Santa Clara, California. The reactor 550 is generally made of metal and electrically grounded to a PVD target 556 having at least a surface portion comprised of copper or a copper alloy which is sputter deposited onto the wafer 558 via the target insulator 554. A vacuum chamber 552 that is sealed. The alloying element is usually less than 5 wt% and pure copper can be used, especially if no suitable barriers are formed. Wafer clamp 560 holds wafer 558 on pedestal electrode 562. Resistive heaters, refrigerant channels, and heat transfer gas cavity of pedestal 562, not shown, allow the temperature of the pedestal to be controlled to a temperature below −40 ° C., thus controlling wafer temperature similarly. Can be.

Floating shield 564 and grounded shield 566 separated from second dielectric shield insulator 568 are retained in chamber 552 to protect chamber wall 552 from sputtered material. The grounded shield 566 also acts as an anode ground plane as opposed to the cathode target 556 to support the plasma capacitively. Certain electrons are deposited on the floating shield 564 to create a negative charge. The negative potential not only pushes additional electrons from being deposited but also limits the electrons in the main plasma region, reduces electron loss, maintains low pressure sputtering, and increases plasma density.

Details of the target and shield are shown in enlarged cross sectional view in FIG. The target 556 includes an aluminum or titanium back plate 570, to which a copper target portion 572 is soldered or diffusion bonded. The flange 573 of the back plate 570 is vacuum and dependent on the vacuum sealed to the target insulator 554 through the polymerization target O-ring 574, which is preferably composed of a ceramic such as alumina. The target insulator 554 relies on a vacuum that is sealed through the adapter O-ring 575 to the chamber 552 and is vacuum and is actually an aluminum adapter sealed to the main chamber body. The metal clamp ring 576 has an annular rim 577 extending upwards on the inner radial surface. Bolts, not shown, secure the metal clamp ring 576 to the shelf 578 extending inwardly of the chamber 552 and capture the flange 579 of the ground shield 566. Thus, ground shield 566 is mechanically and electrically coupled to ground chamber 552.

The shield insulator 568 is freely dependent on the clamp ring 576 and is machined from a ceramic material such as alumina. It is compact but has a relatively large height of approximately 165 mm compared to the smaller width to provide strength during the temperature cycling of the reactor. The lower portion of the shield insulator 568 has an inner annular recess that secures the outside of the rim 577 of the clamp ring 576. The rim 577 serves as the central inner diameter of the shield insulator 568 relative to the clamp ring 576 as well as sliding between the metal shield clamp 576 from reaching the ceramic shield insulator 568 and the main processing area. It serves as a barrier to the dust created at the surface 580.

The flange 581 of the floating shield 564 is freely mounted to the shield insulator 568, and outside the flange 581, a tab or rim extending downward into an annular recess formed at an upper outer corner of the shield insulator 568 ( 582). Accordingly, tab 582 is centered with floating shield 564 relative to target 556 at the outer diameter of shield insulator 568. The shielding tab 582 is small enough to align the plasma dark space from the shielding insulator 568 and is separated by a narrow gap large enough to prevent collision of the shielding insulator 568, and the floating shield 581 is tab Depends on shielded insulator 568 of sliding contact area 583 inside and above 582.

Narrow channel 584 is formed between head 585 and target 556 of floating shield 564. It has a width of approximately 2 mm to serve as plasma dark space. Narrow channel 584 is far radially inward than illustrated as passing through lower protruding ridge 586 of rear plate flange 574 in upper rear gap 584a between shield head 585 and target insulator 554. Continue in a path that extends. The structure and properties of the elements are similar to the structure and properties of US Patent Application 09 / 191,253, disclosed by Tang et al., Filed October 30, 1998. The upper rear gap 584a has a width of approximately 1.5 mm at room temperature. When the shielding elements are temperature cycled, they are susceptible to deformation. The upper rear gap 584a having a smaller width than the narrow channel 584 near the target 556 is sufficient to maintain the plasma dark space in the narrow channel 584. The rear gap 584a extends inwardly and downwardly into the outer chamber body portion 552 with the lower rear gap 584b between the shield insulator 568 and the ring clamp 576. The lower rear gap 584b serves as a cavity to collect ceramic particles produced at the sliding surfaces 580 and 583 between the ceramic shield insulator 568 and the clamp ring 576 and the floating shield 564. The shield insulator 568 also includes a narrow recess 583a in the upper inner corner to collect ceramic particles from the sliding surface 583 over the radial inner surface.

Floating shield 564 extends downward and includes a wide top cylindrical portion 588 extending downward from flange 581, and at the lower end through a transition portion 592 to a narrower cylindrical portion 590. Connected. Similarly, ground shield 566 has a wider upper cylinder 594 on the outside, and is wider than upper cylinder 588 of floating shield 564. Ground upper cylindrical portion 594 is connected to ground shield flange 580 at the upper end and to narrow lower cylindrical portion 596 through a radially extending transition portion 598 of the chamber at the lower end. Ground lower cylinder 596 fixes the outside and is wider than floating lower cylinder 590; However, it is smaller by approximately 3 mm radial separation than the floating top cylinder 590. The two transitions 592, 598 are both offset vertically and horizontally. Thus, a complex narrow channel 600 is formed between the floating and ground shields 564, 566, and the floating upper cylinder 564 does not guarantee a straight line of sight between the ground lower cylinder 576 and the two vertical channel portions. Has an offset between. The purpose of the channel 600 is to electrically insulate the two shields 564, 566 while protecting the clamp ring 576 and the shield insulator 568 from copper deposition.

The lower portion of the channel 600 between the lower cylinder portions 590, 596 of the shields 564, 566 has an aspect ratio of at least 4: 1, preferably at least 8: 1. The lower portion of the channel 600 illustratively has a width of 0.25 cm and a length of 2.5 cm, with preferred ranges of 0.25 to 0.3 cm and 2-3 cm. Thus, scattered copper atoms penetrating the copper ions and channel 600 bounce from the shields several times before finding their way towards the clamp ring 576 and the shield insulator 568, and the ground cylinder ( 594). One bounce creates ions absorbed by the shield. Two adjacent 90 degree turns and bends in the channel 600 between the two transitions 592, 598 also insulate the shield insulator 568 from the copper plasma. Similar and reduced effects are achieved with 60 degree bending or 45 degree bending, but more effective 90 degree bending is easier to form the shielding material. A 90 degree turn is even more effective because the incoming copper particles from any direction have at least one high angle impact, thus increasing the likelihood of stopping at the upper ground cylinder 594 to lose the most energy. The 90 degree turn covers the clamp ring 576 and shielding insulator 568 from being directly radiated by the copper particles. Copper is preferably deposited at either end of one 90 degree turn on the bottom horizontal surface of the floating transition 592 and on the vertical top ground cylinder 594. In addition, the convolut channel 600 collects ceramic particles generated from the shield insulator 568 during processing on the horizontal transition 598 of the ground shield 566. The collected particles are also attached by the collected copper.

Returning to the enlarged view of FIG. 15, the lower cylindrical portion 596 of the ground shield 566 continues downward to the well behind the top of the pedestal 562 supporting the wafer 558. Ground shield 562 extends radially downward of bowl 602 and vertically upward of innermost cylinder 604, while wafer 558 rises approximately, but radially outward of pedestal 562. Away.

Shields 564 and 566 are generally made of stainless steel and the inner surfaces are roughened to increase the adhesion of bead blasted or otherwise deposited copper sputters. At some point during extended sputtering, however, copper is made to the flake thickness, producing harmful particles. Before reaching this point, the shields must be replaced with clean or fresh shields. However, more expensive insulators 554 and 568 do not need to be replaced in most maintenance cycles. In addition, the maintenance circulation is determined by the flaking of the shield, not by the electrical short of the insulators.

As mentioned, floating shield 564 accumulates certain atomic charges and creates a negative potential. Thus, it pushes additional atomic losses to the floating shield 564 and limits the plasma closer to the target 556. Ding et al. Disclosed a similar effect with a structure somewhat similar to US Pat. No. 5,736,021. However, the floating shield 564 of FIG. 16 has a lower cylindrical portion 590 that extends farther than it did in the corresponding portion of Ding et al., Thus limiting the plasma to large volumes. However, floating shield 564 shields ground shield 566 from target 556 so that it does not extend too far from target 556. If it is too long, it is difficult to hit the plasma; If it is too short, atomic loss is increased so that the plasma cannot be maintained at low pressure, and the plasma density drops. The optimal length is as shown in Figure 16, where the lower tip 606 of the floating shield 564 is 6 cm apart from the face of the target 556 with the full axial length of the floating shield 564, which is 7.6 cm. Found in Three different floating shields 564 were tested for the minimum pressure at which copper sputtering was maintained. The results are shown in FIG. 17 at 1 kW and 18 kW of target power. The horizontal axis is expressed as the total shield length, and the separation between the shield tip 606 and the target 556 is no greater than 1.6 cm. The preferred range of separation is 5 to 7 cm and the length is 6.6 to 8.6 cm. Extending the shield length to 10 cm somewhat reduces the minimum pressure, but increases the difficulty of impulsating the plasma.

Referring back to FIG. 15, the selective DC power supply 610 negatively biases the target 556 to approximately -400 to -600 VDC with respect to the ground shield 566 to ignite and maintain the plasma. Target power between 1 and 5 kW is generally used to ignite the plasma, and power above 10 kW is preferred for the SIP sputtering described herein. Generally, pedestal 562 and wafer 558 are left electrically floating, but nevertheless, negative DC self-bias develops on the wafer. On the other hand, certain designs use a controllable power supply 612 that applies a DC or RF bias to the pedestal 562 to control the negative DC bias that is deployed. In the tested configuration, the bias power supply 612 is an RF power supply operating at 13.56 MHz. RF power of 6000 W is supplied and the preferred range is 350-550 W for 200 mm wafers.

Gas source 614 supplies sputtering working gas, generally chemically inert rare gas argon, to chamber 552 via mass flow control system 616. The working gas is received at the top or bottom of the chamber, as shown, and closes the gap 618 between the bottom or ground shield 566 of the ground shield 566 and the wafer clamp 560 and the pedestal 562. One or more inlet pipes penetrating through the openings. The vacuum pump system 620 connected to the chamber 522 via the wide pumping port 622 maintains the chamber at low pressure. While the base pressure can be maintained at approximately 10 ⁻⁷ Torr or less, the pressure of the working gas in conventional sputtering is generally maintained between approximately 1 to 1000 millitorr and less than approximately 5 millitorr in SIP sputtering. to be. Computer-based controller 624 controls the reactor including DC target power supply, bias power supply and mass flow controller 616.

To provide effective sputtering, the magnetron 630 is located behind the target 556. The magnetron has opposing magnets 632, 634 connected and supported by magnetic yoke 636. The magnets create a magnetic field adjacent to the magnetron 630 in the chamber 552. The magnetic field traps electrons, and for neutral charge, the ion density also increases to form the high-density plasma region 638. The magnetron 630 is generally rotated about the center 640 of the target 556 by the motor-drive shaft 642 to achieve complete coverage of the sputtering of the target 556. In order to achieve high-density plasma 638 of sufficient ionization density to maintain self-maintaining sputtering of copper, the power density delivered to the region adjacent to magnetron 630 must be high. This may be achieved as disclosed in the patent by Fu cited above, for example by reducing the area of the magnetron 630 and increasing the power level delivered from the DC power supply 610 in a triangular or racetrack shape. . The triangular magnetron 601, which is rotated with the tip approximately coincident with the target center 640, always covers only one sixth of the target. A quarter of coverage is the desired maximum in commercial reactors capable of SIP sputtering.

In order to reduce the electron loss, the continuous magnetic pole and the unshown pole shown by the outer magnetic pole 634 do not have distinct openings in the inner magnetic pole and the unshown magnetic pole face shown by the inner magnet 632. It is wrapped by face. In addition, in order to guide the ion sputter particles to the wafer 558, the outer poles must produce a higher magnetic flux than the inner pole. The extending magnetic field lines trap electrons and extend the plasma closer to the wafer 558. The ratio of magnetic flux should be at least 150%, preferably greater than 200%. Two embodiments of the triangular magnetron of Fu have 25 external magnets and 6 or 10 internal magnets of the same size but different polarities.

When argon is received into the chamber, the DC voltage difference between the target 556 and the ground shield 566 ignites the argon with plasma, and positively charged argon ions are attracted to the negatively charged target 556. The ions collide with the target 556 with substantial energy and induce a target atom or atom cluster that is sputtered from the target 556. Certain target particles impinge upon the wafer 558 and are thus deposited thereon, thus forming a target material film. In reactive sputtering of metal nitride, additionally nitrogen is received into the chamber and reacts with the sputtered metal atoms to form metal nitride on the wafer 558.

The illustrated chamber can be magnetic ion sputtered of copper, including self-maintained sputtering. In this case, after the plasma is ignited, the supply of argon is stopped in the case of SSS, and the copper ions have a high enough density to resputter the copper target with a yield greater than one. Optionally, with a reduced flow rate, insufficient target power density at chamber pressure, a predetermined argon supply is continued to support pure self-maintaining sputtering, but nevertheless the rate of magnetic sputtering is clearly reduced. If the argon pressure is markedly increased above 5 millitorr, argon removes energy from the copper ions and reduces magnetic sputtering. Wafer bias draws copper particles deeply into the hole.

However, in order to achieve a deeper hole coating with partially neutral flux, it is desirable to increase the distance between the target 556 and the wafer 558, ie to operate in a long-throw mode. . In long-throw, the target-to-substrate space is generally greater than half the substrate diameter. When used, larger than 90% wafer diameter is preferred, but spaces larger than 80%, including 100% and 140% of the substrate diameter, are suitable. The throw mentioned in the examples is referred to as a 200 mm wafer. Long-throw in conventional sputtering reduces the sputtering deposition rate, but ion sputtered particles are not affected by such a large reduction.

The coordinated division between conventional (argon-based) sputtering and self-maintaining sputtering (SSS) allows for control of the distribution between neutral and ion sputter particles. The control is particularly advantageous for sputter deposition of copper seed layers in high aspect ratio via holes. Control of the number of ions of sputtered atoms is referred to as magnetic ion plasma (SIP) sputtering.

One embodiment made by the present invention is a via shown in cross section in FIG. Seed copper layer 650 is deposited on barrier layer 24 in via hole 22, for example, using the long-throw sputter reactor of FIG. 15 and under conditions that activate SIP. SIP copper layer 65 may be deposited, for example, to a blanket thickness of 50 to 300 nm or more preferably 80 to 200 nm. SIP copper seed layer 650 has a thickness on the sidewalls in the range of 2-20 nm, more preferably in the range of 7-15 nm. In terms of narrow holes, the sidewall thickness should not exceed 50 nm. The properties of the thin film are enhanced by lowering the pedestal temperature to below 0 ° C, preferably below -40 ° C, so that the cooling provided by rapid SIP deposition becomes important.

SIP copper seed layer 650 has good bottom coverage and improved sidewall coverage. Experimentally it has been observed to planarize much more than IMP or CVD copper deposited directly on barrier layer 24. After the copper seed layer 650 is deposited, the hole is preferably formed by a copper layer (as shown in FIG. 1) by electro-chemical plating using the seed layer 650 as one of the electroplanting electrodes. 118). However, the planar structure of the SIP copper seed layer 650 also activates high temperature deposition of copper by reflow or standard sputtering or physical vapor deposition (PVD).

Several experiments were performed in SIP to deposit the seed layer into 0.12 μm-wide via holes in 1.2 μm oxide. 0.2 μm blanket thickness copper on top of oxide for 290 mm target-to-substrate spacing, chamber pressure below 0.1 milliTorr (indicative of SSS mode) and DC power of 14 kW applied to the target with 601 triangle magnetron Vapor deposition forms 18 nm on the via bottom and about 12 nm on the via sidewalls. Deposition times of 30 s and below are typical. When the target power is increased to 18 kW, the bottom coverage is increased to 37 nm without significant change in sidewall thickness. Higher bottom coverage at higher power results in higher ionization fraction. For both cases, the deposited copper thin film is observed to be much flatter than seen for IMP or CVD copper.

SIP deposition is relatively fast between 0.5 and 1.0 μm / min compared to an IMP deposition rate of only 0.2 μm / min. Fast deposition rates lead to short deposition cycles and, in combination with the absence of argon ion heating, significantly reduce the thermal budget. It is believed that low temperature SIP deposition results in a very flat copper seed layer.

A 290 nm throw was used for Fu's standard triangle magnetron using 10 internal magnets and 25 external magnets. Under various conditions the ion current flux was measured as a function of the radius from the target center. The results are shown in the graph of FIG. 19. Curve 660 was measured for a target power of 16 mA and chamber pressure of 0 milliTorr. Curves 662, 664, 664 were measured for a target power of 18 kW and chamber pressures of 0, 0.2, and 1 milliTorr, respectively. These currents correspond to ion densities between 10 ¹¹ and 10 ¹² cm ^{-3 ,} compared to 10 ⁹ cm ^{-3 or less in} conventional magnetron and sputter reactors. Zero pressure conditions were used to measure the copper ionization rate. Spatial dependence is approximately equal to the direct dependence on the DC target power for ionization rates that vary between 10% and 20%. The relatively low ionization rate demonstrates that SIP without long throw will have much of the neutral copper flux, which has the disadvantageous deep filling properties of conventional PVD. The results indicate that operation at higher power is desirable for better step coverage because of increased ionization.

Thereafter, the tests are repeated while reducing the number of internal magnets in the Fu magnetron to six. That is, the second magnetron improves the constant in magnetic flux, which increases the constant of the sputtered ion flux toward the wafer. The results are shown in FIG. 20. Curve 668 shows the ion current flux for a target power of 12 mA and a pressure of 0 milliTorr; Curve 679 is about 18 Hz. The curves for 14 'and 16' are in the middle. Thus, the modified magnetron forms a more constant ion current towards the wafer, which in turn depends on the target power and higher power is desirable.

Relatively low ionization rates of 10% to 20% represent a substantial flux of neutral copper as compared to 90% to 100% fraction of IMP. While wafer bias can lead copper ions deep into holes, long throws achieve the very same for copper neutrals.

A series of tests were used to determine the combined effects of throw and chamber pressure on the distribution of sputter particles. At zero chamber pressure, a throw of 140 nm forms a distribution of about 45 degrees; Throw at 190 nm is about 35 degrees; And the throw of 290 nm is about 25 degrees. The pressure was changed for a throw of 190 nm. The median distribution remains about the same for 1, 0.5 and 1 milliTorr. The low-level tails, however, are pushed back about 101 for the highest pressure, indicating scattering of certain particles. These results indicate that satisfactory results are obtained below 5 milliTorr, but the preferred range is below 2 milliTorr, the more preferred range is below 1 milliTorr, and the most preferred range is 0.2 milliTorr and below. Also, as expected, the distribution is best for long throws.

SIP thin films deposited into high-aspect ratio holes have advantageous upper sidewall coverage and do not tend to form overhangs. In another aspect, the IMP thin film deposited into the hole has better bottom and bottom corner coverage, but the sidewall thin film has insufficient coverage and tends to be rough. The advantages of both types of sputtering can be combined by using two steps of copper seed sputter deposition. In a first step, deposition is carried out in an IMP reactor which forms a high density plasma, for example by use of RF induced source power. Exemplary deposition conditions are a pressure of 20-60 milliTorr, a DC target power of 1-30 kW, and a bias power of 150W. The first step provides good but rough bottom and bottom sidewall coverage. In a second and preferred subsequent step, copper is deposited in a SIP reactor of the kind described above to form a smaller degree of copper ionization. Exemplary deposition conditions are 1 Torr pressure, DC target power of 18-24 kV and bias power of 500W. The second step provides good flat top sidewall coverage and further flattens the already deposited IMP layer. The blanket deposition thickness for the two steps is preferably in the range of 50 to 100 nm for IMP deposition and in the range of 100 to 200 nm for the SIP layer. The blanket thicknesses may be in a ratio of 30:70 to 70:30. Alternatively, the SIP layer may be deposited before the IMP layer. After the copper seed layer is sputter deposited by a two step process, the remainder of the hole is filled by, for example, electroplating.

SIP sidewall coverage is very narrow and can be problematic for high-aspect ratio vias. Techniques for 0.13 μm vias and smaller vias are being developed. Below a blanket thickness of about 100 nm, sidewall coverage may be discontinuous. As shown in the cross-sectional view of FIG. 21, the disadvantageous structure allows the SIP copper thin film 680 to be formed of discontinuous thin films containing voids or other defects 682 on the via sidewall 30. . Defect 682 may be a lack of copper or a thin layer of copper that cannot act locally as an electroplating cathode. Nevertheless, the SIP copper thin film 680 is flat and well nucleated except for the defects 682. In these challenging structures, it is advantageous to deposit copper CVD seed layer 684 onto SIP copper nucleation film 680. As it is deposited by chemical vapor deposition, it is typically conformal and well condensed by the SIP copper film 680. The CVD seed layer 684 fills the defects 682 and provides a continuous, non-rough seed layer for subsequent copper electroplating to complete the filling of the holes 22. The CVD layer can be deposited in a CVD chamber designed for copper deposition, such as the CuxZ chamber commercially available from Applied Materials.

Experiments were performed in which 20 nm of CVD copper was alternatively deposited on the SIP copper nucleation layer and the IMP nucleation layer. Bonding with SIP forms a relatively flat CVD seed layer, while bonding with IMP produces a very rough surface in the CVD layer that may be discontinuous.

CVD layer 684 may be deposited, for example, to a thickness in the range of 5-20 nm. Thereafter, the remaining portions of the holes can be filled with copper by other methods. The very flat seed layer formed by CVD on top of the nucleation layer of SIP copper allows holes to be efficiently filled with copper by electroplating or conventional PVD techniques in the narrow vias shown. Particularly for electroplating, the flat copper nucleation and seed layers provide a continuous, nearly constant electrode for powering the electroplating process.

In filling vias or other holes with ultra-high aspect ratios, a sufficiently thick CVD copper layer 688 as shown in the cross-sectional view of FIG. It may be advantageous to deposit on nucleation layer 680. The advantage of CVD filling is that it eliminates the need for a separate electroplating step. In addition, electroplating requires fluid fluxes that can be difficult to control in holes having a width of 0.13 μm or less.

An advantage of the copper bilayer of this embodiment of the present invention is that the double layer allows the copper deposition to be performed with a relatively low thermal burden. Tantalum tends to dewet from oxides at higher thermal burdens. IMP has many of the same coverage advantages for deep hole filling, but IMP tends to operate at much higher temperatures because it creates a high flux of activated argon ions that dissipate energy in the layer in which it is deposited. Furthermore, IMP invariably injects certain argon into the deposited film. In contrast, relatively thin SIP layers are deposited at relatively high rates and the SIP process is not inherently hot due to the absence of argon. In addition, the SIP deposition rate is much faster than IMP and therefore any high temperature deposition is much shorter, with a factor of 1/2.

In addition, the thermal burden is reduced by low temperature ignition of the SIP plasma. The cold plasma ignition and processing sequence is shown in the flowchart of FIG. When the wafer is inserted into the sputter reactor through a load lock valve, the load lock valve is closed and the gas pressure is paralleled in step 690. The argon chamber pressure is raised to the pressure used for ignition, typically between 2 and about 5 to 10 milliTorr, provided to the backside of the wafer at an argon backside cooling gas at a backside pressure of about 5 to 10 Torr. do. In step 692, argon is ignited at a low level, typically at a target power in the range of 10-5 mA. After the plasma has been detected and ignited, in step 694 the chamber pressure is reduced rapidly, for example 3s, while the target power is maintained at a low level. If sustained self-sputtering is planned, the chamber argon supply is stopped, but the plasma continues in SSS mode. For self-ionizing plasma sputtering, the argon supply is reduced. The backside cooling gas is continuously supplied. Once the argon pressure has been reduced, in step 696 the target power rises rapidly up to the intended sputtering level, for example above 10 to 24 kW or 200 nm wafer, which level can be reduced to SIP or SSS sputtering. Is chosen. At the same time, steps 694 and 696 can be combined by reducing pressure and increasing power. In step 698, power is continuously supplied to the target for the time required to sputter deposit the material at the selected level to the selected thickness. This ignition sequence is colder than when using the intended sputtering power level for ignition. Higher argon pressure facilitates ignition but will adversely affect the sputtered nuclei if continued at the higher power level intended for sputter deposition. At lower ignition power, very little copper is deposited because of the low deposition rate at reduced power. In addition, pedestal cooling allows the wafer to be kept at a low temperature through an ignition process.

Many features of the apparatus and process of the present invention can be applied to sputtering that does not include long throws.

Although the present invention is currently particularly useful for copper-to-copper metallization and barrier and liner deposition, other aspects of the present invention may be applied to sputtering of other materials for other purposes.

As described in pending application number 10 / 202,778, filed on July 25, 2002, which is hereby incorporated by reference in its entirety, the inter-device interconnection layers or layers also generate SIP and ICP plasma. It may be deposited in a sputter chamber similar to chamber 152 (FIG. 4). For example, if deposited in a chamber such as chamber 152, target 156 would be formed of a deposition material, such as copper. In addition, the ICP coil 151 may also be formed of the same deposition material, especially when coil sputtering is intended for some or all of the intermetallic deposition of the device.

As mentioned above, the illustrated chamber 152 is capable of self-ionizing sputtering on copper while including self-maintaining sputtering. In this case, after the plasma is ignited, the supply of argon in the case of SSS can be stopped, and the copper ions have a density high enough to resputter the copper target in a yield greater than one. Alternatively, some amount of argon continues to be supplied at reduced flow rates and chamber pressures and perhaps for insufficient target power density to support pure self-maintained sputtering, but nevertheless significantly reduced self-sputtering portions. Can be. If the argon pressure is increased significantly above 5 milliTorr, argon will remove energy from copper theories and reduce self-sputtering. Wafer bias draws ionized portions of the copper particles deep into the holes.

However, in order to achieve deeper hole coating with partially neutral flux, it is desirable to increase the distance between target 156 and wafer 158, ie operate in long-throw mode as discussed above. . The controlled division between self-ionizing plasma (SIP) sputtering, inductively coupled plasma (ICP) sputtering and self-maintaining sputtering (SSS) allows control of the distribution between neutral and ionized particles. Such control is particularly advantageous for sputter deposition of copper seed layers in high aspect ratio via holes. Control of the sputtered ionization rate is achieved by mixing self-ionizing plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering.

One embodiment of the structure according to the invention is the via shown in the cross sectional view of FIG. 24. Copper seed layer 700 is deposited in via hole 702 over liner layer 704 (which may include two or more barriers and liner layers, such as the TaN barrier and Ta liner layers mentioned above), for example Using a long-throw sputter reactor of the type shown in FIG. 4, it is made under conditions that promote coupling of SIP and ICP and / or alternation of SIP and ICP. Here, the reactor will have a target comprising copper or other seed layer deposition material. SIP-ICP copper layer 700 may be deposited, for example, to a blanket thickness of 50-300 nm or more preferably 80-200 nm. Preferably, the SIP-ICP copper seed layer 700 has a thickness in the range of 2-20 nm on the via sidewalls. In terms of narrow holes, the sidewall thickness should not exceed 50 nm. The properties of the film are enhanced by lowering the pedestal temperature below 0 ° C, preferably below -40 ° C, so that the cooling provided by rapid SIP deposition becomes important.

It is believed that the SIP-ICP copper seed layer 700 will have good bottom coverage and improved sidewall coverage. As described in more detail below, copper seed layer 700 typically employs a copper deposition material to increase coverage at the inner bottom corners of the via, leaving thinner coverage at the center of the via bottom. It can be resputtered in a separate step or during initial deposition to redistribute. After the copper seed layer 700 is deposited (preferably, after being deposited and redistributed), the hole is preferably copper of FIG. 14B by electrochemical plating using the seed layer 700 as one of the electroplating electrodes. It may be filled with a copper layer similar to layer 347b '. However, the flat structure of the SIP-ICP copper seed layer 700 also promotes reflow or high temperature deposition of copper by standard sputtering or physical vapor deposition (PVD).

In one embodiment, the SIP-ICP layer may be formed in a process that combines selected features of both the SIP deposition technique and the ICP deposition technique in one step, which step is generally referred to herein as the SIP-ICP step. . In addition, the reactor 715 according to an alternative embodiment has a second coil 716 in addition to the coil 151 shown in FIG. 25. In the same way as coil 151, one end of coil 716 is darkspace shield 164 by feedthrough standoff 182 at the output of amplifier and matching network 717. ') Is insulatively coupled. An input of the matching network 717 is coupled to the RF generator 718. The other end of coil 716 connects shield 164 'to ground by feedthrough standoff 182 via blocking capacitor 719 to provide a DC bias on coil 716. Is coupled through insulating. DC bias can be controlled by a separate DC source 721.

In the ICP or combined SIP-ICP stage, RF energy is applied to one or both of the RF coils 151 and 716 at frequencies of 1-3 kW and 2Mhz, for example. When powered, the coils 151 and 716 inductively couple the RF energy into the reactor. The RF energy provided by the coils ionizes a precursor gas such as argon to maintain the plasma to ionize the sputtered deposition material. However, rather than maintaining the plasma at a relatively high pressure, such as 20-60 mTorr, which is typical for high density IMP processes, the pressure is preferably maintained at significantly lower pressures, for example 2 mTorr. As a result, the ionization rate in reactor 150 will be significantly lower than typical high density IMP processes.

In addition to the foregoing, the reactor 150 shown is also capable of self-ionized sputtering in long-throw mode. As a result, the deposition material will be ionized by the self-generated plasma not only by the result of the low pressure plasma held by the RF coil or coils, but also by the DC magnetron sputtering of the target. Combined SIP and ICP ionization processes can provide sufficiently ionized material for good floor and bottom corner coverage. However, the lower ionization rate of the low pressure plasma provided by the RF coils 151 and 716 allows sufficient neutral sputtering material to remain unionized for deposition on the upper sidewalls by the long-throw performance of the reactor. . Thus, the combined SIP and ICP sources of ionized deposition material can provide good bottom and bottom corner coverage and good top sidewall coverage. In yet another embodiment, the power to the coils 151 and 716 can be alternated such that power to the upper coil 726 is removed or reduced in proportion to the power applied to the lower coil 151 in one step. have. In this step, the center of the inductively coupled plasma is moved closer to the substrate from the target. Such a configuration can reduce the interaction between the self-ionized plasma generated near the target and the inductively coupled plasma maintained by the one or more coils. As a result, higher proportions of neutral sputtering material may be maintained.

In a second step, power to the lower coil 151 may be reversed to be removed or reduced in proportion to the power applied to the upper coil 716. In this step, the center of the inductively coupled plasma can be moved from the substrate toward the target. This configuration can increase the proportion of ionized sputter material.

In another embodiment, the layer may be formed in two or more steps, with little or no RF power applied to either coil in one step, generally referred to herein as the SIP step. In addition, the pressure will be maintained at a relatively low level, preferably at 5 mTorr or less, more preferably at 2 mTorr or less, for example at 1 mTorr. In addition, the power applied to the target will be relatively high, for example in the range of 18-24 kW DC. The bias can also be applied to the substrate support at, for example, a power level of 500 watts. Under these conditions, ionization of the deposition material occurs primarily as a result of self-ionizing plasma (SIP). Combined with the long-throw mode configuration of the reactor, good top sidewall coverage can be achieved with a low overhang. The portion of the layer deposited in this initial step may be in the range of 1000-2000 angstrom, for example.

In the second stage, generally referred to herein as the ICP stage, preferably within the same chamber, RF power may be applied to one or both of the coils 151 and 716. In addition, in one embodiment, the pressure can be raised considerably so that a high density plasma can be maintained. For example, the pressure may rise to 20-60 mTorr, the RF power to the coil may rise to a range of 1-3 kW, the DC power to the target is reduced to 1-2 kW, and the bias to the substrate support Is reduced to 150 watts. Under these conditions, ionization of the deposition material will occur primarily as a result of high density ICP. As a result, good floor and bottom corner coverage can be achieved in the second step. Power may be applied simultaneously or alternately, as described above.

After the copper seed layer is sputter deposited by the process of combining the SIP and the ICP, the rest of the holes can be filled by the same or different process. For example, the rest of the holes can be filled by electroplating or CVD.

The order of the SIP step and the ICP step may be reversed, some RF power may be applied to one or more coils in the SIP step, and certain self ionization may be induced in the ICP step. In addition, sustained self sputtering (SSS) may be induced in one or more stages. Therefore, process parameters, including pressure, power, and target-substrate distance, can be varied depending on the particular application to achieve the desired result.

As mentioned previously, the coils 151 and 516 may be operated independently or may be operated together. In one embodiment, the coils can be operated together, where the RF signal applied to one coil is phase shifted relative to another RF signal applied to the other coil to produce a helicon wave. For example, RF signals may be phase shifted by a portion of the wavelength described in US Pat. No. 6,264,812.

One embodiment of the present invention preferably includes an integrated process performed on an integrated multi-chamber tool, such as the Endura 5500 platform schematically shown in the plan view of FIG. The platform has been described functionally in US Pat. No. 5,186,718 to Tepman et al.

Substrates that have already been etched into the via holes or other structure of the insulating layer are two independent configured to transfer substrates into and out of the system from substrate cassettes loaded into respective load lock chambers. Are loaded into and out of the system through load lock chambers 732, 734 operated. After the substrate cassette has been loaded into the load lock chambers 732, 734, the chamber is pumped to an appropriately low pressure, for example in the range of 10 ⁻³ to 10 ⁻⁴ Torr, and the load lock chamber and the first substrate transfer chamber 736 The slit valve between) is opened. Thereafter, the pressure of the first substrate transfer chamber 736 is maintained at such low pressure.

A first robot 738 located in the first transfer chamber 736 transfers the substrate from the cassette to one of the two degassing / orienting chambers 740, 742 and then the first plasma. It is delivered to a pre-clean chamber 744, where hydrogen or argon plasma cleans the surface of the substrate. If a CVD barrier layer is deposited, first robot 738 then transfers the substrate to CVD barrier chamber 746. After the CVD barrier layer is deposited, the robot 738 transfers the substrate to a pass through chamber 748, from which the second robot 750 transfers the substrate to a second transfer chamber. 752). Slit valves separate the chambers 744, 746, 748 from the first transfer chamber 736 to isolate processing and pressure levels.

The second robot 750 selectively transfers the substrates to and from the reaction chambers disposed therein. The first IMP sputter chamber 754 may be dedicated to copper deposition. Similar to the chamber 410 described above, a SIP sputter chamber 756 is dedicated to the deposition of a SIP copper seed layer or nucleation layer. This chamber combines SIP for lower and sidewall coverage with resputtering for improved bottom corner coverage in one or more steps as described above. Also, for example, at least a portion of the barrier layer of Ta / TaN is deposited by SIP sputtering and coil sputtering and ICP resputtering, so SIP-ICP sputter chamber 760 is probably used to sputter refractory metal in reactive nitrogen plasmas. Only. The same SIP-ICP chamber 760 may be used to deposit refractory metals and nitrides thereof. CVD chamber 758 is applied to copper nucleation, deposition of seed or liner layers, or to complete filling of holes, or both. Each chamber 754, 756, 758, 760 is selectively opened to the second transfer chambers 752 by slit valves. It is possible to use different configurations. For example, especially if CVD is used to complete hole filling, IMP chamber 754 may be replaced by a second CVD copper chamber.

After the low pressure processing, the second robot 750 transfers the substrate to an intermediately placed thermal chamber 762, which may be a cooling chamber if the preceding processing was a high temperature, or It may be a rapid thermal processing (RTP) chamber where annealing of the metallization is desired. After the heat treatment, the first robot 738 draws out the substrate and re-delivers the substrate to one of the load lock chambers 732, 734. Of course, other configurations are possible in which the present invention may be performed depending on the steps of the integrated process.

The entire system is controlled by a computer based controller 770 operating on a control bus 772 that communicates with the sub-controllers associated with each chamber. Process recipes are read into the controller by a recordable medium 774, such as a magnetic floppy disk or CD-ROM, insertable into the controller 770, or on the communication link 776.

Many features of the apparatus and process of the present invention can be applied to sputtering that is not related to long throw. Although the present invention is particularly useful at this time for tantalum and tantalum nitride liner layer deposition and copper inter-level metallization, other aspects of the present invention may be applied to sputtering other materials and for other purposes. US Provisional Application No. 60 / 316,137, filed August 30, 2001, relates to sputtering and resputtering techniques, which are incorporated herein by reference.

Of course, variations of the invention in various aspects will be apparent to those skilled in the art, certain modifications will be apparent from reading this specification, and other variations are matters of conventional physical design and process design. Other embodiments are also possible, and the specific design of the other embodiments depends on the particular application. As such, the scope of the invention is defined not by the specific embodiments described herein, but by the appended claims and their equivalents.

150: reactor 152: vacuum chamber
156: target 158: wafer
204: matching network 206: RF generator
330: magnetron 332, 334: magnet
336: magnetic yoke 338: high density plasma region
349: Via 352: Outlet
360: gas inlet 416: target
418: electrical insulator 424: substrate
434: DC power 444: yoke
446: rotary arm 462: permanent magnet
476: clamp member 550: reactor
554: target isolator 558: wafer
564: floating shield 576: ring
577: rim 581: flange
600: channel 610: DC power supply
616: mass flow control system 630: magnetron
650: SIP copper seed layer 732, 734: load lock chamber
744: pre-clean chamber 770: controller

Claims (35)

A method of depositing metal into a hole having an aspect ratio of at least 4: 1 formed in a dielectric layer of a substrate, the method comprising:
A sputter deposition step of depositing a deposition material comprising a metal in the hole in an inductively coupled plasma in a chamber; And
A sputter deposition step of depositing a deposition material comprising a metal in said hole in a self-ionized plasma in a chamber,
Sputter deposition in the self-ionized plasma and sputter deposition in the inductively coupled plasma are performed in the same chamber. The method of claim 1,
And filling the hole with a metal. The method of claim 2,
The filling step is a metal deposition method comprising the electroplating step. The method of claim 1,
Sputter deposition in the self-ionized plasma precedes sputter deposition in the inductively coupled plasma. delete The method of claim 4, wherein
Sputter deposition in the inductively coupled plasma further comprises a resputtering step of resputtering the deposition material deposited in the self-ionized plasma in the inductively coupled plasma. The method according to claim 6,
And said resputtering comprises removing a deposited material deposited on the bottom of said hole. The method of claim 1,
Sputter deposition in the self-ionized plasma deposits a deposition material comprising at least one of tantalum and tantalum nitride. The method of claim 1,
Sputter deposition in the self-ionized plasma deposits a deposition material comprising copper. The method of claim 1,
Sputter deposition in the inductively coupled plasma deposits a deposition material comprising at least one of tantalum and tantalum nitride. The method of claim 1,
Sputter deposition in the inductively coupled plasma deposits a deposition material comprising copper. The method of claim 1,
Sputter deposition in the inductively coupled plasma uses at least partially RF inductive coupling with a coil in the chamber containing the inductively coupled plasma to form the inductively coupled plasma. . A method of forming interconnects in holes having an aspect ratio of at least 4: 1 formed in a dielectric layer of a substrate, the method comprising:
Sputter depositing a barrier layer in said hole in a self-ionized plasma in a chamber;
Resputtering the lower portion of the barrier layer in an inductively coupled plasma in the chamber to remove at least a portion of the lower portion of the barrier layer;
Sputter depositing a liner layer on the barrier layer in the hole in a self-ionized plasma in the chamber;
Resputtering the lower portion of the liner layer in an inductively coupled plasma in the chamber to remove at least a portion of the lower portion of the liner layer;
Sputter depositing a seed layer in said hole in a self-ionized plasma in a chamber; And
Resputtering the lower portion of the seed layer in a self-ionized plasma in the chamber to redistribute at least a portion of the lower portion of the seed layer.
Interconnect forming method comprising a. The method of claim 13,
And filling a conductive metal into said hole after resputtering said seed layer. 15. The method of claim 14,
Wherein said filling step comprises an electroplating step. The method of claim 13,
Sputter deposition of barrier layer and liner layer in the self-ionized plasma and resputtering of the lower portion of the liner layer and barrier layer in the inductively coupled plasma are performed in the same chamber. The method of claim 13,
Sputter deposition of a seed layer in the self-ionized plasma and resputtering of a seed layer lower portion in the self-ionized plasma are performed in the same chamber. The method of claim 13,
Sputter deposition of the barrier layer in the self-ionized plasma deposits a deposition material comprising tantalum nitride. The method of claim 13,
Sputter deposition of the seed layer in the self-ionized plasma deposits a deposition material comprising copper. The method of claim 13,
The resputtering step in the inductively coupled plasma uses at least partially RF inductive coupling with a coil inside the chamber containing the inductively coupled plasma to form the inductively coupled plasma. Way. The method of claim 13,
The resputtering step at least in part in the self-ionized plasma uses auxiliary magnets at least partially disposed in the vicinity of the processing space between the substrate support pedestal and the target in the chamber having a central axis, the magnets along the central axis. And having a first magnetic polarity. The method of claim 17,
The seed layer sputter deposition in the self-ionized plasma includes biasing the substrate to a first level and the resputtering of the lower portion of the seed layer in the self-ionized plasma is greater than the first level. Biasing the substrate to a high second level. The method of claim 17,
The seed layer sputter deposition in the self-ionized plasma may include applying a first level of power to the target and the resputtering of the lower portion of the seed layer in the self-ionized plasma may include: Applying a second level of power lower than the level. A method of depositing metal into a hole having an aspect ratio of at least 4: 1 formed in a dielectric layer of a substrate, the method comprising:
A sputter deposition step of depositing a deposition material comprising a metal in the hole in an inductively coupled plasma in a chamber; And
A sputter deposition step of depositing a deposition material comprising a metal in the hole in a self-ionized plasma in the chamber;
One or more of the sputter deposition steps includes a resputtering step of resputtering the deposition material of the hole to remove the deposition material deposited below the hole,
Sputter deposition in the self-ionized plasma precedes sputter deposition in the inductively coupled plasma,
The sputter deposition in the inductively coupled plasma further includes a resputtering step of resputtering the deposition material deposited in the self-ionized plasma in the inductively coupled plasma, the resputtering step in the inductively coupled plasma. And removing the deposited material deposited on the bottom of the hole while depositing the material on the sidewall of the hole. 25. The method of claim 24,
And filling the hole with a metal. The method of claim 25,
The filling step is a metal deposition method comprising the electroplating step. delete 25. The method of claim 24,
Sputter deposition in the self-ionized plasma and sputter deposition in the inductively coupled plasma are performed in the same chamber. delete delete 25. The method of claim 24,
Sputter deposition in the self-ionized plasma deposits a deposition material comprising at least one of tantalum and tantalum nitride. 25. The method of claim 24,
Sputter deposition in the self-ionized plasma deposits a deposition material comprising copper. 25. The method of claim 24,
Sputter deposition in the inductively coupled plasma deposits a deposition material comprising at least one of tantalum and tantalum nitride. 25. The method of claim 24,
Sputter deposition in the inductively coupled plasma deposits a deposition material comprising copper. 25. The method of claim 24,
Sputter deposition in the inductively coupled plasma uses at least partially RF inductive coupling with a coil in the chamber containing the inductively coupled plasma to form the inductively coupled plasma. .

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