JP2008010532A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable to improve wiring reliability by suppressing generation of a facet and bowing in an opening of a connection hole and a wiring trench upper part. <P>SOLUTION: A stopper film 15 and an insulating film 16 are formed on a substrate, and a wiring trench 17 is formed on the insulating film 16 and a connection hole 18 is formed on its bottom. A first barrier film 21 is formed in an internal surface between the wiring trench 17 other than the bottom of the connection hole 18 and the connection hole 18. The stopper film 15 of the bottom of the connection hole 18 is removed to elongate the connection hole 18. A second barrier film 22 is formed on at least the bottom of the connection hole 18. A wiring material 23 is embedded via the second barrier film 22 and the first barrier film 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a barrier film is formed in a wiring groove and a connection hole formed in the bottom thereof.

Since copper (Cu) wiring provides lower resistance, lower capacitance, and higher reliability than aluminum (Al) alloy wiring, it is more important for micro devices where circuit delay due to wiring parasitic resistance and parasitic capacitance is dominant. I came. Generally, copper is not easy to dry etch unlike aluminum-based alloy wiring, and so-called damascene process is widely accepted. In the damascene process, for example, a predetermined groove is formed in an interlayer insulating film such as a silicon oxide (SiO ₂ ) film in advance, a wiring material is embedded in the groove, and the surplus wiring material is then subjected to chemical mechanical polishing (CMP). ) Is a wiring formation process formed by removing by a method or the like. Furthermore, the dual damascene method, in which wiring material is filled in at a time after forming connection holes and wiring grooves and excess wiring material is removed, is also effective in reducing the number of steps and cost (see, for example, Patent Document 1). ).

  As shown in FIG. 8A, a silicon nitride film (SiN), a silicon carbide film (SiC), and a silicon nitride carbide film (SiCN) are usually provided on the copper (Cu) wiring 111 as a stopper film 121 for the insulating film 122. A film that does not contain oxygen is used. When forming a wiring with a dual damascene structure, generally, a process is employed in which the stopper film 121 at the bottom of the connection hole 123 is finally processed to establish conduction with the underlying copper wiring 111.

As shown in FIG. 8B, the processing of the stopper film here is usually silicon oxide used as a cap film on the insulating film 122 where the connection hole 123 is formed and the insulating film 112 where the copper wiring 111 is formed. Since it is difficult to process a high selectivity with respect to the (SiO ₂ ) film or the silicon carbide oxide (SiOC) film, when removing the stopper film 121 at the bottom of the connection hole 123, the opening of the connection hole 123 and the wiring groove 124 are used. The problem arises that the shoulders fall to the top and facets occur.

  As a result, there arises a problem that a margin for a leak between wirings, which becomes more serious as LSI design rules become finer, decreases. Furthermore, as shown in FIG. 9 (3), due to the facet shape above the connection hole 123, the barrier metal film 125 formed by sputtering becomes an overhang shape.

  Then, as shown in FIG. 9 (4), when the copper 126 is embedded, there arises a problem that a void 127 is formed inside the connection hole 123. As a result, the wiring reliability is rapidly deteriorated.

  Further, as shown in FIG. 10A, the insulating film 132 in which the wiring groove 124 is formed on the insulating film 131 in which the connection hole 123 is formed is, for example, a polyaryl ether film 133 and a silicon carbide oxide (SiOC) film 134. Even when a hard mask 135 made of a silicon nitride carbide (SiCN) film is formed on the upper portion, the stopper film 121 at the bottom of the connection hole 123 is removed as shown in FIG. In this process, shoulder dropping or faceting occurs in the opening of the wiring groove 124 and the opening of the connection hole 123.

Japanese Patent Laid-Open No. 11-045887

  The problem to be solved is that shoulder drop occurs at the opening of the connection hole and the upper part of the wiring groove, and facet occurs at the opening of the connection hole and the upper part of the wiring.

  The present invention makes it possible to improve the wiring reliability by suppressing the occurrence of facets and shoulder drop at the opening of the connection hole and the upper part of the wiring groove.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a stopper film and an insulating film on a substrate, forming a wiring groove in the insulating film and a connection hole at the bottom of the wiring groove, and forming the bottom of the connection hole. Forming a first barrier film on the inner surfaces of the wiring groove and the connection hole, excluding the stopper film at the bottom of the connection hole and extending the connection hole, and at least a bottom of the connection hole. And a step of burying a wiring material through the first barrier film and the second barrier film inside the wiring groove and the connection hole.

  In the method of manufacturing a semiconductor device according to the present invention, since the first barrier film is formed on the inner surfaces of the wiring groove and the connection hole except for the bottom of the connection hole, the connection hole is extended to the stopper film. The first barrier film acts as a mask. For this reason, since the stopper film can be removed with high selectivity, so-called shoulder drop does not occur in the connection hole opening and the wiring groove opening.

  According to the method for manufacturing a semiconductor device of the present invention, since the stopper film can be removed with high selectivity, so-called shoulder drop does not occur in the connection hole opening and the wiring groove opening. In addition, a short margin between the wirings or between the wirings and the connection holes is secured, and the shape can also be advantageous for pinch-off when embedding the wiring material. There is an advantage that a reliable wiring structure is obtained, and an order of magnitude breakdown voltage effect can be obtained as compared with the conventional wiring structure.

  An embodiment (first example) according to a method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS.

  As shown in FIG. 1A, a wiring layer insulating film 12 is formed on a base 11 formed on a base (not shown). The wiring layer insulating film 12 is formed of, for example, a silicon carbide oxide (SiOC) film. A first wiring 14 made of copper (Cu) is formed on the wiring layer insulating film 12 through a barrier film 13. Here, the first wiring 14 is formed to have a height of 150 nm, and a stopper film 15 for preventing copper diffusion and oxidation is formed on the first wiring 14. The stopper film 15 is formed, for example, by forming a silicon carbonitride (SiCN) film with a thickness of 35 nm, for example, and also functions as an etching stopper in a later process. Subsequently, an insulating film 16 for forming wiring grooves and connection holes is formed on the stopper layer 15. This insulating film 16 is formed of, for example, a silicon carbide oxide (SiOC) film. Then, by the lithography technique and reactive ion etching, the wiring groove 17 and the connection hole 18 are formed in the bottom of the wiring groove 17 in the insulating film 16 to obtain a so-called dual damascene structure.

  Next, an example of a method for forming the first barrier film on the inner surfaces of the wiring groove 17 and the connecting hole 18 excluding the bottom of the connecting hole 18 will be described below. First, as shown in FIG. 1B, the first barrier film 21 is formed on the inner surfaces of the wiring groove 17 and the connection hole 18. The first barrier film 21 has a function of preventing the shoulder of the opening of the connection hole 18 and the upper part of the wiring groove 17 when the stopper film 15 at the bottom of the connection hole 18 is removed. Therefore, the first barrier film 21 is formed of a material that can selectively etch the stopper film 15. For example, tantalum (Ta) is formed to a thickness of 4 nm, for example. This film formation is performed by a directional sputtering method using a tantalum target using, for example, a general magnetron sputtering apparatus. The film thickness of the first barrier film 21 here is sufficient to be 2 nm or more in order to use it for facet prevention. Further, in order to selectively remove only the first barrier film 21 at the bottom of the connection hole 18 in the next step, it is desirable that the thickness be 10 nm or less.

  Next, as shown in FIG. 2C, the stopper film 15 at the bottom of the connection hole 18 is selectively removed (opened) to extend the connection hole 18. As this method, using a directional magnetron sputtering apparatus in which a tantalum target is installed, the substrate bias is set to 600 W, the target DC power is set to 5 kW, the atmosphere is set to 100% argon, and the pressure of the atmosphere is set to 133 mPa. The tantalum (Ta) film is formed and etched so as to be plus or minus zero on the so-called solid film, and a discharge treatment is performed for a predetermined time. As a result, bias etching is performed at the bottom of the connection hole 18 having a high aspect ratio while maintaining the state in which the first barrier film 21 remains on the upper part, the side wall part, the bottom part of the wiring groove 17 and the upper part and side wall part of the connection hole 18. As the component increases, the first barrier film 21 is selectively removed.

Next, as shown in FIG. 2 (4), the stopper film 15 at the bottom of the connection hole 18 is removed by etching to open the connection hole 18. This etching is performed by, for example, a general magnetron type etching apparatus, for example, octafluorocyclopentene (C ₅ F ₈ ), carbon monoxide (CO), argon (Ar), and oxygen (O ₂ ) as an etching gas. The gas flow rate ratio is C ₅ F ₅ : CO: Ar: O ₂ = 1: 10: 5: 1, the bias power is set to 1600 W, and the substrate temperature is set to 20 ° C. Under this etching condition, a selection ratio of 50 or more with the first barrier film 21 made of tantalum can be obtained, so that the shoulder drop at the opening of the connection hole 18 and the upper part of the wiring groove 17 is suppressed, and only the stopper film 15 is opened. It becomes possible to form a simple dual damascene structure.

  Next, as shown in FIG. 3 (5), after performing an appropriate degassing process, the second barrier film 22 is formed on the inner surfaces of the wiring groove 17 and the connection hole 18 via the first barrier film 21. Form. The second barrier film 22 serves as a diffusion prevention film for the interlayer insulating film of the copper wiring, and is formed, for example, by depositing tantalum (Ta) to a thickness of 10 nm, for example. For example, the film is formed by a directional sputtering method using a tantalum target using a general magnetron sputtering apparatus.

  Next, as shown in FIG. 3 (6), a wiring made of copper or an alloy containing copper is inserted into the wiring groove 17 and the connection hole 18 through the first barrier film 21 and the second barrier film 22. Embed material 23. The wiring material is formed using, for example, an electrolytic plating method, a sputtering method, or a CVD method. When the electrolytic plating method is used, a layer (not shown) serving as a copper plating seed is formed in advance on the inner surfaces of the wiring groove 17 and the connection hole 18. The second barrier film 22 needs to be formed on the inner surfaces of the wiring groove 17 and the connection hole 18 with good coverage. Therefore, for example, a directional sputtering method is preferably used for the film formation, and examples of such a film formation method include a self-discharge ionization sputtering method and a long-distance sputtering method. Moreover, it is desirable from the viewpoint of improving reliability that the first barrier film 21 and the second barrier film 22 are made of the same material.

  Next, the excessive wiring material 23, the first barrier film 21, and the second barrier film 22 on the insulating film 16 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the second wiring 24 made of the wiring material 23 is formed in the wiring groove 17 via the first barrier film 21 and the second barrier film 22, and the first barrier film 21 and the second barrier film are formed inside the connection hole 18. A plug 25 made of the wiring material 23 is formed via 22.

  Next, as shown in FIG. 4 (7), a prevention layer 26 for preventing copper diffusion and oxidation is formed. The prevention layer 26 is formed of, for example, a silicon carbide nitride (SiCN) film.

  According to the manufacturing method (first embodiment), since the stopper film 15 can be removed with high selectivity, so-called shoulder drop does not occur at the opening of the connection hole 18 and the opening of the wiring groove 17. Shorter margins between wires or between wires and connection holes are secured for finer generations, and the shape can be made advantageous for pinch-off when embedding wiring materials. On the other hand, there is an advantage that a highly reliable wiring structure is obtained, and an order of magnitude breakdown voltage effect can be obtained as compared with the conventional wiring structure.

  Next, an embodiment (second embodiment) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS.

As shown in FIG. 5A, a wiring layer insulating film 12 is formed on a base 11 formed on a base (not shown). The wiring layer insulating film 12 is formed of, for example, a silicon carbide oxide film (SiOC) ₂ . A first wiring 14 made of copper (Cu) is formed on the wiring layer insulating film 12 through a barrier film 13. Here, the first wiring 14 is formed to have a height of 150 nm, and a stopper film 15 for preventing copper diffusion and oxidation is formed on the first wiring 14. The stopper film 15 is formed by, for example, forming a silicon carbide nitride film (SiCN) 4 with a thickness of 35 nm, for example, and also functions as an etching stopper in a later process. Subsequently, an insulating film 16 for forming wiring grooves and connection holes is formed on the stopper layer 15. The insulating film 16 is formed of, for example, a silicon carbide oxide film (SiOC) 5. Then, by the lithography technique and reactive ion etching, the wiring groove 17 and the connection hole 18 are formed in the bottom of the wiring groove 17 in the insulating film 16 to obtain a so-called dual damascene structure.

  Next, an example of a method of forming the first barrier film on the inner surfaces of the wiring groove 17 and the connecting hole 18 excluding the bottom of the connecting hole 18 and removing the stopper film 15 will be described below. First, as shown in FIG. 5B, the first barrier film 21 is formed on the inner surfaces of the wiring groove 17 and the connection hole 18. The first barrier film 21 has a function of preventing the shoulder of the opening of the connection hole 18 and the upper part of the wiring groove 17 when the stopper film 15 at the bottom of the connection hole 18 is removed. Therefore, the first barrier film 21 is formed of a material that can selectively etch the stopper film 15. For example, tantalum (Ta) is formed to a thickness of 4 nm, for example. This film formation is performed by a directional sputtering method using a tantalum target using, for example, a general magnetron sputtering apparatus. The film thickness of the first barrier film 21 here is sufficient to be 2 nm or more in order to use it for facet prevention. Also, in order to selectively remove only the first barrier film 21 at the bottom of the connection hole 18 in the next step, it is desirable that the thickness be 8 nm or less.

  Next, as shown in FIG. 6 (3), the first barrier film at the bottom of the connection hole 18 is selectively removed (opened), and the stopper film 15 at the bottom of the connection hole 18 is continuously removed. The connection hole 18 is extended. As this method, using a directional magnetron sputtering apparatus in which a tantalum target is installed, the substrate bias is set to 1000 W, the target DC power is set to 5 kW, the atmosphere is set to 100% argon, and the pressure of the atmosphere is set to 67 mPa. The tantalum (Ta) film is formed and etched so as to be plus or minus zero on the so-called solid film, and a discharge treatment is performed for a predetermined time. As a result, bias etching is performed at the bottom of the connection hole 18 having a high aspect ratio while maintaining the state in which the first barrier film 21 remains on the upper part, the side wall part, the bottom part of the wiring groove 17 and the upper part and side wall part of the connection hole 18. As the component becomes larger, the first barrier film 21 and the stopper film 15 are selectively removed. As a result, the connection hole 18 is extended.

  Next, as shown in FIG. 6 (4), after performing an appropriate degassing process, the second barrier film 22 is formed on the inner surfaces of the wiring groove 17 and the connection hole 18 via the first barrier film 21. Form. The second barrier film 22 serves as a diffusion prevention film for the interlayer insulating film of the copper wiring, and is formed, for example, by depositing tantalum (Ta) to a thickness of 10 nm, for example. For example, the film is formed by a directional sputtering method using a tantalum target using a general magnetron sputtering apparatus.

  Next, as shown in FIG. 7 (5), the wiring made of copper or an alloy containing copper is inserted into the wiring groove 17 and the connection hole 18 through the first barrier film 21 and the second barrier film 22. Embed material 23. The wiring material is formed using, for example, an electrolytic plating method, a sputtering method, or a CVD method. When the electrolytic plating method is used, a layer (not shown) serving as a copper plating seed is formed in advance on the inner surfaces of the wiring groove 17 and the connection hole 18. The second barrier film 22 needs to be formed on the inner surfaces of the wiring groove 17 and the connection hole 18 with good coverage. Therefore, for example, a directional sputtering method is preferably used for the film formation, and examples of such a film formation method include a self-discharge ionization sputtering method and a long-distance sputtering method. Moreover, it is desirable from the viewpoint of improving reliability that the first barrier film 21 and the second barrier film 22 are made of the same material.

  Next, the excessive wiring material 23, the first barrier film 21, and the second barrier film 22 on the insulating film 16 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the second wiring 24 made of the wiring material 23 is formed in the wiring groove 17 via the first barrier film 21 and the second barrier film 22, and the first barrier film 21 and the second barrier film are formed inside the connection hole 18. A plug 25 made of the wiring material 23 is formed via 22.

  Next, as shown in FIG. 7 (6), a prevention layer 26 for preventing copper diffusion and oxidation is formed. The prevention layer 26 is formed of, for example, a silicon carbide nitride (SiCN) film.

  According to the manufacturing method (second embodiment), since the stopper film 15 can be removed with high selectivity, so-called shoulder drop does not occur at the opening of the connection hole 18 and the opening of the wiring groove 17. Shorter margins between wires or between wires and connection holes are secured for finer generations, and the shape can be made advantageous for pinch-off when embedding wiring materials. On the other hand, there is an advantage that a highly reliable wiring structure is obtained, and an order of magnitude breakdown voltage effect can be obtained as compared with the conventional wiring structure. Further, since the removal process of the first barrier film 21 and the stopper film 15 at the bottom of the connection hole 18 is continuously performed, there is an advantage that the manufacturing process is shortened compared to the first embodiment.

  In the first and second embodiments, the insulating film 16 in which the wiring trench 17 is formed is a single insulating film. However, even in a dual damascene structure using a plurality of insulating films, a stopper film at the bottom of the connection hole is used. In the process of removing the film, the manufacturing process for forming the first barrier film 21 and the second barrier film 22 of the present invention can be applied.

In the first and second embodiments, the first barrier film 21 forming step and the first barrier film 21 removing step are preferably performed in the same chamber. The first barrier film 21 forming step, the first barrier film 21 removing step, and the stopper film 15 removing step are preferably performed in the same chamber. Furthermore, the first barrier film 21 forming step, the first barrier film 21 removing step, the stopper film 15 removing step, and the second barrier film 22 forming step are preferably performed in the same chamber. By performing the process in the same chamber as described above, it is possible to improve the wiring reliability because an unnecessary oxide film is not formed because it is not exposed to an oxidizing atmosphere. In addition, since the transfer time of the process hall can be eliminated, TAT (Turn
Around Time) can be shortened.

It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed an example which concerns on the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed an example which concerns on the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed an example which concerns on the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 15 ... Stopper film, 16 ... Insulating film, 17 ... Wiring groove, 18 ... Connection hole, 21 ... 1st barrier film, 22 ... 2nd barrier film, 23 ... Wiring material

Claims (7)

Forming a stopper film and an insulating film on the substrate, forming a wiring groove in the insulating film and a connection hole at the bottom of the wiring groove;
Forming a first barrier film on the inner surface of the wiring groove and the connection hole excluding the bottom of the connection hole;
Removing the stopper film at the bottom of the connection hole and extending the connection hole;
Forming a second barrier film at least at the bottom of the connection hole;
And a step of burying a wiring material in the wiring trench and the connection hole through the first barrier film and the second barrier film. The method of manufacturing a semiconductor device according to claim 1, wherein the first barrier film is formed of a material capable of selectively etching the stopper film. The method of manufacturing a semiconductor device according to claim 1, wherein the first barrier film forming step and the stopper film removing step are continuously performed. The method of manufacturing a semiconductor device according to claim 1, wherein the first barrier film and the second barrier film are formed of the same material. The method for manufacturing a semiconductor device according to claim 1, wherein the forming step of the first barrier film and the removing step of the first barrier film are performed in the same chamber. The method of manufacturing a semiconductor device according to claim 1, wherein the first barrier film forming step, the first barrier film removing step, and the stopper film removing step are performed in the same chamber. The first barrier film forming step, the first barrier film removing step, the stopper film removing step, and the second barrier film forming step are performed in the same chamber. A method for manufacturing a semiconductor device.

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