KR101174151B1 - Apparatus for driving of liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving device of a liquid crystal display device capable of reducing the number of pins of a connector and the number of transmission lines of a cable for transmitting a reference gamma voltage.

A driving device of a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel; A reference gamma voltage generator configured to generate a plurality of reference gamma voltages; A gamma buffer integrated circuit configured to buffer and output at least one reference gamma voltage among the plurality of reference gamma voltages supplied from the reference gamma voltage generator; A plurality of data integrated circuits for embedding the gamma buffer integrated circuit and converting a data signal input using the buffered plurality of reference gamma voltages into an analog image signal and supplying the analog image signal to the liquid crystal panel; A plurality of gate integrated circuits for supplying scan pulses to the liquid crystal panel; A first data board supplying the buffered reference gamma voltage to half of the plurality of data integrated circuits; A second data board configured to supply the buffered reference gamma voltage to the remaining data integrated circuits of the plurality of data integrated circuits; And a signal transmission member for transmitting the buffered reference gamma voltage between the first and second data boards.

Description

Driving device for liquid crystal display {APPARATUS FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view schematically showing a driving device of a liquid crystal display according to the prior art.

2 is a plan view schematically illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a plan view showing the data tape carrier package shown in FIG.

FIG. 4 is a block diagram schematically illustrating the data integrated circuit shown in FIG. 2. FIG.

5 is a plan view schematically illustrating a driving device of a liquid crystal display according to another exemplary embodiment of the present disclosure.

FIG. 6 is a plan view of the data tape carrier package shown in FIG. 5; FIG.

Description of the Related Art

1, 101: lower substrate 2, 102: upper substrate

3, 103: liquid crystal panel 6, 106: gate integrated circuit

10, 110: data integrated circuit 12, 112: control board

14, 114: timing controller 16, 116: reference gamma voltage generator

20, 30, 120, 130: data board 107: dummy signal line

140: dummy cable 150: signal control unit

152: shift register 154: latch portion

156: DAC unit 158: output buffer unit

160: gamma voltage generation unit 170: gamma buffer integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device capable of reducing the number of pins of a connector for transmitting a reference gamma voltage and the number of transmission lines of a cable.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

1 is a view showing a driving device of a liquid crystal display according to the prior art.

Referring to FIG. 1, a driving apparatus of a liquid crystal display according to the related art includes a liquid crystal panel 3; A plurality of gate integrated circuits 6 for supplying scan pulses to the liquid crystal panel 3; A plurality of data integrated circuits 10 for supplying an analog image signal to the liquid crystal panel 3; A timing controller 14 for supplying data signals to the plurality of data integrated circuits 10 and controlling the respective data and gate integrated circuits 10 and 12, and generating a plurality of reference gamma voltages to generate a plurality of data integrated circuits ( A control board 12 mounted with a reference gamma voltage generator 16 supplied to 10), a first data board 20 connected to half of the plurality of data integrated circuits 10, and a plurality of data integrated circuits. The second data board 30 connected to the rest of 10, the first cable 18A connected between the first data board 20 and the control board 12, and the second data board 30 and the control. A second cable 18B connected between the boards 12 is provided.

The liquid crystal panel 3 includes a lower substrate 1 and an upper substrate 2. A liquid crystal (not shown) is injected between the lower substrate 1 and the upper substrate 2 of the liquid crystal panel 3, and not shown to maintain a constant gap between the lower substrate 1 and the upper substrate 2. Not equipped with a spacer.

The upper substrate 2 is formed with a color filter, a black matrix, and the like, not shown.

In the lower substrate 1, signal wirings such as data lines and gate lines (not shown) are formed, and thin film transistors and pixel electrodes connected to the thin film transistors are formed at the intersections of the data lines and the gate lines. The TFT switches the analog image signal to be transmitted from the data line toward the liquid crystal cell in response to the scan pulse from the gate line to the pixel electrode.

In addition, data and gate pad regions connected to the data lines and the gate lines, respectively, are formed at one side of the lower substrate 1.

The timing controller 14 is mounted on the control board 12 and is connected to the dot clock Dclk, the horizontal synchronizing signal Hsync, and the vertical synchronizing signal Vsync from the outside through a user connector (not shown) disposed on the control board 12. , Data enable (DE) and source data (RGB) are supplied. The timing controller 14 controls the driving timing of each data integrated circuit 10 by using a dot clock Dclk, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data enable DE. In addition to generating a data control signal for generating a gate control signal for controlling the driving timing of each gate integrated circuit (6).

The timing controller 14 arranges the source data RGB supplied from the outside to be suitable for driving the liquid crystal panel 3 and supplies the source data RGB to the data integrated circuits 10.

The reference gamma voltage generator 16 includes a plurality of resistors connected in series between the first voltage and the second voltage on the control board 12. The reference gamma voltage generator 16 generates a plurality of reference gamma voltages having different voltage values at the divided nodes between the plurality of resistors connected in series.

A plurality of control signal transmission lines (not shown), a plurality of data signal transmission lines (not shown), and a plurality of first and second reference gamma voltage transmission lines 22 and 24 are formed in the first data board 20.

Gate and data control signals are supplied to the plurality of control signal transmission lines through the first cable 18A. In addition, the data signals are supplied to the plurality of data signal transmission lines through the first cable 18A. The reference gamma voltages of some of the plurality of reference gamma voltages are supplied to the plurality of first reference gamma voltage wires 22, and the plurality of second reference gamma voltage transmission lines are described below. The reference gamma voltage buffered from the data integrated circuit 10 is supplied.

A plurality of control signal transmission lines (not shown), a plurality of data signal transmission lines (not shown), and a plurality of third and fourth reference gamma voltage transmission lines 32 and 34 are formed on the second data board 30.

Gate and data control signals are supplied to the plurality of control signal transmission lines through the second cable 18B. In addition, the data signals are supplied to the plurality of data signal transmission lines through the second cable 18B. The plurality of third reference gamma voltage wires 32 are supplied with the remaining reference gamma voltages among the plurality of reference gamma voltages through the second cable 18B, and the fourth reference gamma voltage wires 34 are described later. The reference gamma voltage buffered from each data integrated circuit 10 is supplied.

Each data integrated circuit 10 is mounted in a data tape carrier package 8.

Each data tape carrier package 10 is attached to be connected between the data pad area of the lower substrate 1 and the first data board 20, and between the data pad area of the lower substrate 1 and the second data board 30. It is attached to be connected.

Each data integrated circuit 10 converts a data signal supplied from the timing controller 14 into an analog image signal and supplies it to each data line in accordance with a data control signal from the timing controller 14 mounted on the control board 12. do. That is, each data integrated circuit 10 generates a plurality of gamma voltages by subdividing the plurality of reference gamma voltages supplied from the reference gamma voltage generator 16, and generates one of the plurality of gamma voltages generated according to the data signal. Selected as an analog image signal and supplied to each data line.

On the other hand, each data integrated circuit 10 is a control board 12, cables 18A, 18B, data boards 20, 30 and data from the reference gamma voltage generator 16 mounted on the control board 12. A gamma buffer integrated circuit (not shown) for buffering and redistributing the plurality of reference gamma voltages supplied through the tape carrier package 8 to other data integrated circuits 10.

Accordingly, after each reference gamma voltage supplied to each data integrated circuit 10 is buffered through a gamma buffer integrated circuit embedded in each data integrated circuit 10, the data tape carrier package 8 and the data board 20 are buffered. , 30) and cables 18A, 18B.

A case where eight reference gamma voltages are generated in the reference gamma voltage generator 16 will be described as an example.

First, among the eight reference gamma voltages, each of the first to fourth reference gamma voltages is transmitted through a plurality of first reference gamma voltage transmission lines of the control board 12, the first cable 18A, and the first data board 20. The data integrated circuit 10 is connected to the first data board 20. Accordingly, the first to fourth reference gamma voltages are buffered through the gamma buffer integrated circuits embedded in the respective data integrated circuits 10 to form the plurality of second reference gamma voltage wires 24 formed on the first data board 20. And then distributed to other data integrated circuits 10. At this time, the buffered first to fourth reference gamma voltages supplied to the plurality of second reference gamma voltage wires 24 are seconded through the first cable 18A, the control board 12, and the second cable 18B. The fourth reference gamma voltage wiring 34 formed on the data board 30 is supplied to the plurality of fourth reference gamma voltage wirings 34.

Each of the fifth to eighth reference gamma voltages of the eight reference gamma voltages is controlled through a plurality of third reference gamma voltage transmission lines of the control board 12, the second cable 18B, and the second data board 30. The data integrated circuit 10 is connected to the second data board 30. Accordingly, the fifth to eighth reference gamma voltages are buffered through the gamma buffer integrated circuits embedded in the respective data integrated circuits 10 to form the plurality of fourth reference gamma voltage wires 34 formed on the second data board 30. And then distributed to other data integrated circuits 10. In this case, the buffered fifth to eighth reference gamma voltages supplied to the plurality of fourth reference gamma voltage transmission lines 34 may be formed through the second cable 18B, the control board 12, and the first cable 18A. It is supplied to the plurality of second reference gamma voltage wirings 24 formed on the first data board 20.

Accordingly, the plurality of reference gamma voltages are buffered through the gamma buffer integrated circuits embedded in the respective data integrated circuits 10 and then distributed and supplied to the data integrated circuits 10.

Each gate integrated circuit 6 is mounted in a gate tape carrier package 4. Each gate tape carrier package 4 is attached to the gate pad region of the lower substrate 1. Accordingly, each gate driver 12 is connected from the timing controller 14 mounted on the control board 12 through the first cable 18A, the first data board 20 and the first data tape carrier package 10. The scan pulses are sequentially supplied to the gate lines in response to the supplied gate control signal.

The driving device of the liquid crystal display according to the related art includes a gamma buffer integrated circuit in each data integrated circuit 10, and is supplied from the reference gamma voltage generator 16 through each of the embedded gamma buffer integrated circuits. The current of the reference gamma voltage is amplified and redistributed to another data integrated circuit 10.

Accordingly, the driving device of the liquid crystal display according to the related art controls the control board 12 to redistribute the reference gamma voltage to each data integrated circuit 10 connected to each of the first and second data boards 20 and 30. In addition, the number of pins of the connectors disposed on the data boards 20 and 30 increases and the number of transmission lines of the cables 18A and 18B increases.

Accordingly, an object of the present invention is to provide a driving device of a liquid crystal display device capable of reducing the number of pins of a connector and the number of transmission lines of a cable for transmitting a reference gamma voltage.

In order to achieve the above object, the driving device of the liquid crystal display according to the embodiment of the present invention comprises a liquid crystal panel; A reference gamma voltage generator configured to generate a plurality of reference gamma voltages; A gamma buffer integrated circuit configured to buffer and output at least one reference gamma voltage among the plurality of reference gamma voltages supplied from the reference gamma voltage generator; A plurality of data integrated circuits for embedding the gamma buffer integrated circuit and converting a data signal input using the buffered plurality of reference gamma voltages into an analog image signal and supplying the analog image signal to the liquid crystal panel; A plurality of gate integrated circuits for supplying scan pulses to the liquid crystal panel; A first data board supplying the buffered reference gamma voltage to half of the plurality of data integrated circuits; A second data board configured to supply the buffered reference gamma voltage to the remaining data integrated circuits of the plurality of data integrated circuits; And a signal transmission member for transmitting the buffered reference gamma voltage between the first and second data boards.

The signal transmission member may be a dummy cable connected between the first and second data boards.

The signal transmission member may be a dummy signal line directly formed on the liquid crystal panel.

The driving apparatus of the liquid crystal display may further include a plurality of data tape carrier packages on which the respective data integrated circuits are mounted, and a plurality of gate tape carrier packages on which the respective gate integrated circuits are mounted.

The driving device of the liquid crystal display includes a timing controller for aligning source data from the outside into the data signals and supplying the data signals to the data integrated circuits and controlling the data integrated circuits and the gate integrated circuits, and the reference gamma. And a control board on which a voltage generator is mounted, a first cable connected between the control board and the first data board, and a second cable connected between the control board and the second data board.

The first data board may include a first signal line to which half of the plurality of reference gamma voltages are supplied from the reference gamma voltage generator through the first cable, and the gamma buffer embedded in each of the data integrated circuits. And a second signal wiring to which the reference gamma voltage buffered from the integrated circuit is supplied.

The second data board may include a third signal line through which the remaining reference gamma voltages of a plurality of reference gamma voltages are supplied from the reference gamma voltage generator through the second cable, and the gamma buffer integrated in each of the data integrated circuits. And a fourth signal wiring to which the reference gamma voltage buffered from the circuit is supplied.

The cable is connected to the second signal wiring and the fourth signal wiring.

The data integrated circuit may include a gamma voltage generator configured to generate a plurality of gamma voltages by subdividing the buffered reference gamma voltages supplied from the gamma buffer integrated circuit, the embedded gamma buffer integrated circuit, and the second and fourth signal lines. And a shift register for sequentially outputting a sampling signal, a latch portion for sequentially latching the data signal in accordance with the sampling signal, and a data signal from the latch portion using the plurality of gamma voltages. And an output buffer section for supplying an analog image signal from the digital-analog converter to a liquid crystal panel.

The dummy signal line may be directly formed on the liquid crystal panel so as to be connected to the second signal line and the fourth signal line.

The data tape carrier package connected to the first data board so as to be adjacent to the second data board includes the second signal line and a dummy line connected to the signal transmission member, and the data tape carrier package is adjacent to the first data board. The data tape carrier package connected to the second data board may include dummy wires connected to the fourth signal wires and the signal transmission member.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 6.

2 is a diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

2, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 103; A reference gamma voltage generator 116 for generating a plurality of reference gamma voltages; Built-in gamma buffer integrated circuit for buffering and outputting at least one reference gamma voltage among the plurality of reference gamma voltages supplied from the reference gamma voltage generator 116, and inputting data by dividing the buffered plurality of reference gamma voltages. A plurality of data integrated circuits 110 for converting a signal into an analog image signal and supplying them to the liquid crystal panel 103, a plurality of gate integrated circuits 106 for supplying scan pulses to the liquid crystal panel 103, and buffering The first data board 120 supplying the predetermined reference gamma voltage to the data integrated circuit 110 of the half of the plurality of data integrated circuits 110 and the remaining buffered reference gamma voltage of the plurality of data integrated circuits 110. The first and second data boards 120 and 13 are connected between the second data board 130 and the first and second data boards 120 and 130 to supply the data integrated circuit 110 to the buffered reference gamma voltage. A reference gamma voltage transmission dummy cable 140 is transmitted between 0).

In addition, the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention supplies a data signal to each data integrated circuit 110, and controls a timing controller 114 to control each data and each gate integrated circuit 110 and 112. And a control board 112 on which the reference gamma voltage generator 116 is mounted; A first cable 118A connected between the first data board 120 and the control board 112; A second cable 118B is further provided connected between the second data board 130 and the control board 112.

The liquid crystal panel 103 includes a lower substrate 101 and an upper substrate 102. Liquid crystals (not shown) are injected between the lower substrate 101 and the upper substrate 102 of the liquid crystal panel 103, and not shown to maintain a constant gap between the lower substrate 101 and the upper substrate 102. Not equipped with a spacer.

The upper substrate 102 is formed with a color filter, a black matrix, and the like, not shown.

On the lower substrate 101, signal wirings such as data lines and gate lines (not shown) are formed, and thin film transistors and pixel electrodes connected to the thin film transistors are formed at the intersections of the data lines and the gate lines. The TFT switches the analog image signal to be transmitted from the data line toward the liquid crystal cell in response to the scan pulse from the gate line to the pixel electrode.

Further, data and gate pad regions connected to the data lines and the gate lines, respectively, are formed at one side of the lower substrate 101.

The timing controller 114 is mounted on the control board 112 and is connected to the dot clock Dclk, the horizontal synchronizing signal Hsync, and the vertical synchronizing signal Vsync from the outside through a user connector (not shown) disposed on the control board 112. , Data enable (DE) and source data (RGB) are supplied. The timing controller 114 controls the driving timing of each data integrated circuit 110 by using a dot clock Dclk, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data enable DE. A data control signal for generating a gate control signal for controlling the driving timing of each gate integrated circuit 106 is generated.

In addition, the timing controller 114 arranges the source data RGB supplied from the outside to be suitable for driving the liquid crystal panel 103 and supplies the source data RGB to each data integrated circuit 110.

The reference gamma voltage generator 116 includes a plurality of resistors connected in series between a first voltage and a second voltage (not shown) on the control board 112. The reference gamma voltage generator 116 generates a plurality of reference gamma voltages having different voltage values at the divided nodes between the plurality of resistors connected in series.

The first data board 120 includes a plurality of control signal transmission lines (not shown), a plurality of data signal transmission lines (not shown), and a plurality of first and second reference gamma voltage transmission lines 122 and 124.

Gate and data control signals are supplied to the plurality of control signal transmission lines through the first cable 118A. In addition, the data signals are supplied to the plurality of data signal transmission lines through the first cable 118A. In addition, a plurality of reference gamma voltages of a plurality of reference gamma voltages are supplied to the plurality of first reference gamma voltage wires 122, and the plurality of second reference gamma voltage transmission lines are respectively integrated with data. The buffered reference gamma voltage is supplied from a gamma buffer integrated circuit embedded in the circuit 110.

The second data board 130 includes a plurality of control signal transmission lines (not shown), a plurality of data signal transmission lines (not shown), and a plurality of third and fourth reference gamma voltage transmission lines 132 and 134.

Gate and data control signals are supplied to the plurality of control signal transmission lines through the second cable 118B. In addition, the data signals are supplied to the plurality of data signal transmission lines through the second cable 118B. The remaining reference gamma voltages of the plurality of reference gamma voltages are supplied to the plurality of third reference gamma voltage wirings 132 through the second cable 118B, and the respective data are supplied to the plurality of fourth reference gamma voltage wirings 34. The buffered reference gamma voltage is supplied from a gamma buffer integrated circuit embedded in the integrated circuit 110.

Each data integrated circuit 110 is mounted in a data tape carrier package 108.

As illustrated in FIG. 3, each data tape carrier package 110 supplies a data signal Data and a data control signal DCS supplied from the timing controller 114 to the mounted data integrated circuit 110. The data integrated circuit 110 mounted with an input pad 109A and a control signal input pad 109B and at least one reference gamma voltage Vgam_m among a plurality of reference gamma voltages supplied from the reference gamma voltage generator 116. A data output pad 111 for outputting an analog image signal from a data integrated circuit 110 mounted and connected to a reference gamma voltage input pad 109C to be supplied to the data pad of the liquid crystal panel 103; And a reference gamma voltage output pad 109D for outputting the reference gamma voltage Vgam_m buffered by the gamma buffer integrated circuit embedded in the mounted data integrated circuit 110 to the data boards 120 and 130.

Each of the data tape carrier packages 110 on which half of the plurality of data integrated circuits 110 are mounted is connected between the data pad area of the lower substrate 101 and the first data board 120. Attached. In addition, each data tape carrier package 110 in which each of the remaining data integrated circuits 110 is mounted among the plurality of data integrated circuits 110 is connected between the data pad area of the lower substrate 101 and the second data board 130. To be attached.

Each gate integrated circuit 106 is mounted in a gate tape carrier package 104. Each gate tape carrier package 104 is attached to the gate pad region of the lower substrate 101. Accordingly, each gate driver 112 is connected from the timing controller 114 mounted on the control board 112 through the first cable 118A, the first data board 120 and the first data tape carrier package 110. The scan pulses are sequentially supplied to the gate lines in response to the supplied gate control signal.

Each of the plurality of data integrated circuits 110 converts a data signal supplied from the timing controller 114 into an analog image signal according to the data control signal from the timing controller 114 mounted on the control board 112 to convert each data line. To feed. That is, each data integrated circuit 110 generates a plurality of gamma voltages by subdividing the plurality of reference gamma voltages supplied from the reference gamma voltage generator 116, and generates one of the plurality of gamma voltages generated according to the data signal. Selected as an analog image signal and supplied to each data line.

To this end, each data integrated circuit 110 includes a signal controller 150 for relaying the data control signal DCS and the data signal Data from the timing controller 114 and the data board as shown in FIG. 4. The gamma buffer integrated circuit 170 buffering some of the reference gamma voltages Vgam_m among the plurality of reference gamma voltages input from the 120 and 130, and the buffered plurality of reference gamma voltages supplied from the data boards 120 and 130. A gamma voltage generator 160 for subdividing (Vgam_n) to generate a plurality of gamma voltages, a shift register 152 for supplying a sequential sampling signal, and a data signal from the signal controller 150 in response to the sampling signal The latched data signal Data from the latch unit 154 is latched using the latch unit 154 sequentially latching and simultaneously outputting the data and the plurality of gamma voltages supplied from the gamma voltage generator 160. Analog image And a analog converter (hereinafter, DAC bridle hereinafter) 156, an output buffer 158 to output the buffered analog video signal from the DAC unit 156 - fenugreek converted to digital. Each data integrated circuit 110 having such a configuration supplies an analog image signal to data lines corresponding to the number of output channels of the output buffer unit 158.

The signal controller 150 relays the various control signals (SSP, SSC, SOE, POL, etc.) and the data signal Data from the timing controller 114 to the corresponding components.

The gamma buffer integrated circuit 170 amplifies a part of the reference gamma voltage Vgam_m supplied from the reference gamma voltage generator 116 through the data boards 120 and 130 and the reference gamma voltage input pad 109C. At the same time, output to the outside. In this case, a part of the reference gamma voltage Vgam_n buffered by the gamma buffer integrated circuit 170 is output to the data boards 120 and 130 through the reference gamma voltage output pad 109D of the data tape carrier package 108. .

The gamma voltage generator 160 is configured to convert the plurality of reference gamma voltages Vgam_n buffered by the gamma buffer integrated circuit 170 of the other data integrated circuit 110 to correspond to the grayscale values of the data signal Data. The voltage is divided into voltages and supplied to the DAC unit 156.

The shift register 152 sequentially shifts the source start pulse SSP from the signal controller 150 according to the source sampling clock signal SSC, outputs it as a sampling signal, generates a carry signal, and generates a next data integrated circuit. It is supplied to the shift register 152 of (110).

The latch unit 154 sequentially samples the data signal Data from the signal controller 150 according to the sampling signal from the shift register 152 to latch the data signal Data for one horizontal line, and one horizontal line. The data signal Data for the line is simultaneously output to the DAC unit 156.

The DAC unit 156 converts the latched data signal Data from the latch unit 154 into an analog image signal and outputs it to the output buffer unit 158. At this time, the DAC unit 156 converts the data signal Data into a positive or negative analog image signal according to the polarity control signal POL supplied from the signal controller 150.

The output buffer unit 158 carries out signal buffering of the analog image signal from the DAC unit 156 and supplies it to the data lines DL1 to DLm.

Meanwhile, the reference gamma voltage transmission dummy cable 140 illustrated in FIG. 2 is connected to a connector disposed on one side of the first data board 120 and a connector disposed on one side of the second data board 130.

The reference gamma voltage transmission dummy cable 140 is connected to the data tape carrier package 108 from the gamma buffer integrated circuit 170 embedded in each of the half data integrated circuits 110 connected to the first data board 120. The buffered reference gamma voltage Vgam_n supplied to the plurality of second reference gamma voltage wires 124 through the reference gamma voltage output pad 109D is applied to the fourth reference gamma voltage wire 134 of the second data board 130. To feed.

In addition, the reference gamma voltage transmission dummy cable 140 is a reference of the data tape carrier package 108 from the gamma buffer integrated circuit 170 embedded in each of the remaining data integrated circuits 110 connected to the second data board 130. The buffered reference gamma voltage Vgam_n supplied to the plurality of fourth reference gamma voltage wires 134 through the gamma voltage output pad 109D is transferred to the second reference gamma voltage wire 124 of the first data board 120. Supply.

As described above, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention distributes and supplies each of the plurality of reference gamma voltages to the gamma buffer integrated circuit 170 embedded in each data integrated circuit 110, and then supplies each gamma. The buffered reference gamma voltage output from the buffer integrated circuit 170 is supplied to the gamma voltage generator 160 of each data integrated circuit 110. At this time, the buffered data from the half of the data integrated circuit 110 connected to the first data board 120 through the reference gamma voltage transmission dummy cable 140 connected between the first and second data boards 120 and 130. Some reference gamma voltages and the remaining buffered reference gamma voltages from the remaining data integrated circuit 110 connected to the second data board 120 are distributed.

An example in which eight reference gamma voltages are generated in the reference gamma voltage generator 116 will be described below.

First, the first to fourth reference gamma voltages of the eight reference gamma voltages are each of the plurality of first reference gamma voltage wires 122 of the control board 112, the first cable 118A, and the first data board 120. The data integrated circuit 110 is connected to the first data board 120 through the data integrated circuit 110. Accordingly, the first to fourth reference gamma voltages are buffered through the gamma buffer integrated circuits 170 embedded in the respective data integrated circuits 110 to form a plurality of second reference gamma voltage wires formed on the first data board 120. A plurality of fourth references of the second data board 130 through the reference gamma voltage transmission dummy cable 140 while being distributed to other data integrated circuits 110 connected to the first data board 120 through 124. It is supplied to the gamma voltage wiring 134 and distributed to the remaining data integrated circuit 110.

Each of the fifth to eighth reference gamma voltages of the eight reference gamma voltages may include a plurality of third reference gamma voltage wires 132 of the control board 112, the second cable 118B, and the second data board 130. The second data board 130 is supplied to the remaining data integrated circuit 110 connected to the second data board 130. Accordingly, the fifth to eighth reference gamma voltages are buffered through the gamma buffer integrated circuit 170 embedded in the remaining data integrated circuit 110, and thus the plurality of fourth reference gamma voltages formed on the second data board 130. The plurality of first of the first data board 120 is distributed to the other data integrated circuit 110 connected to the second data board 130 through the wiring 134 and at the same time through the reference gamma voltage transmission dummy cable 140. It is supplied to the reference gamma voltage wiring 122 and distributed to half of the data integrated circuit 110.

5 is a diagram illustrating a driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a driving apparatus of a liquid crystal display according to another exemplary embodiment of the present invention may include a liquid crystal panel 103; A reference gamma voltage generator 116 for generating a plurality of reference gamma voltages; Built-in gamma buffer integrated circuit for buffering and outputting at least one reference gamma voltage among the plurality of reference gamma voltages supplied from the reference gamma voltage generator 116, and inputting data by dividing the buffered plurality of reference gamma voltages. A plurality of data integrated circuits 110 for converting a signal into an analog image signal and supplying them to the liquid crystal panel 103, a plurality of gate integrated circuits 106 for supplying scan pulses to the liquid crystal panel 103, and buffering The first data board 120 supplying the predetermined reference gamma voltage to the data integrated circuit 110 of the half of the plurality of data integrated circuits 110 and the remaining buffered reference gamma voltage of the plurality of data integrated circuits 110. A dummy for transferring the second data board 130 to the data integrated circuit 110 and the reference gamma voltage buffered on the liquid crystal panel 103 between the first and second data boards 120 and 130. And a signal line 107.

In addition, the driving apparatus of the liquid crystal display according to another exemplary embodiment of the present invention supplies a data signal to each data integrated circuit 110 and controls a timing controller 114 for controlling each data and each gate integrated circuit 110 and 112. And a control board 112 on which the reference gamma voltage generator 116 is mounted; A first cable 118A connected between the first data board 120 and the control board 112; A second cable 118B is further provided connected between the second data board 130 and the control board 112.

Such a driving apparatus of the liquid crystal display according to another exemplary embodiment of the present invention is illustrated in FIG. 2 except for the dummy signal line 107 and the data tape carrier package 108 connected to the dummy signal line 107. The same elements as those of the driving device of the liquid crystal display according to the exemplary embodiment of the present invention. Accordingly, in the driving apparatus of the liquid crystal display according to another exemplary embodiment of the present disclosure, descriptions of other components except for the dummy signal line 107 will be replaced with those described with reference to FIGS. 2 to 4. Shall be.

The dummy signal line 107 is directly formed on the lower substrate 101 corresponding to the region where the first and second data boards 120 and 130 face each other along with the manufacturing process of the thin film transistor formed on the lower substrate 101. do. The dummy signal line 107 is formed in an area excluding the data pad part formed on the lower substrate 101.

The data tape carrier package 108 connected between one side of the dummy signal line 107 and the first data board 120 includes a plurality of second reference gamma voltages formed on the first data board 120 as illustrated in FIG. 6. And a dummy line 113 connected to the wiring 124 and the dummy signal line 107. The dummy line 113 supplies the buffered reference gamma voltage supplied from the second reference gamma voltage wires 124 of the first data board 120 to the dummy signal line 107 formed on the lower substrate 101. do.

In addition, the data tape carrier package 108 connected between the other side of the dummy signal line 107 and the second data board 130 may include a plurality of fourth standards formed on the second data board 130 as shown in FIG. 6. And a dummy line 113 connected to the gamma voltage wiring 134 and the dummy signal line 107. The dummy line 113 supplies the buffered reference gamma voltage supplied from the fourth reference gamma voltage wires 134 of the second data board 130 to the dummy signal line 107 formed on the lower substrate 101. do.

The dummy signal line 107 supplies the buffered half of the reference gamma voltage supplied from the first data board 120 to the second data board 130 and the buffered half supplied from the second data board 130. The remaining reference gamma voltage is supplied to the first data board 120.

As described above, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention uses a reference gamma voltage transmission cable or a reference gamma voltage transmission line formed in the liquid crystal panel to control the gamma buffer integrated circuit built into each data integrated circuit. By transferring the buffered reference gamma voltage between two data boards and distributing the data to another data integrated circuit, the number of pins of a connector and the number of transmission lines of a cable for transmitting the reference gamma voltage may be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (11)

A liquid crystal panel; A reference gamma voltage generator configured to generate a plurality of reference gamma voltages; A gamma buffer integrated circuit configured to buffer and output at least one reference gamma voltage among the plurality of reference gamma voltages supplied from the reference gamma voltage generator; A plurality of data integrated circuits for embedding the gamma buffer integrated circuit and converting a data signal input using the buffered plurality of reference gamma voltages into an analog image signal and supplying the analog image signal to the liquid crystal panel; A plurality of gate integrated circuits for supplying scan pulses to the liquid crystal panel; A first data board supplying the buffered reference gamma voltage to half of the plurality of data integrated circuits; A second data board configured to supply the buffered reference gamma voltage to the remaining data integrated circuits of the plurality of data integrated circuits; A signal transmission member for transmitting the buffered reference gamma voltage between the first and second data boards; A timing controller for aligning source data from an external source with the data signal and supplying the data signals to the data integrated circuits, controlling the data integrated circuits and the gate integrated circuits, and a control board on which the reference gamma voltage generator is mounted; , A first cable connected between the control board and the first data board; And a second cable connected between the control board and the second data board. The method of claim 1, And the signal transmission member is a dummy cable connected between the first and second data boards. The method of claim 1, And the signal transmission member is a dummy signal line directly formed on the liquid crystal panel. The method according to claim 2 or 3, A plurality of data tape carrier packages on which each data integrated circuit is mounted; And a plurality of gate tape carrier packages on which the gate integrated circuits are mounted. delete The method of claim 1, The first data board, A first signal wiring through which the reference gamma voltage of half of the plurality of reference gamma voltages is supplied from the reference gamma voltage generator through the first cable; And a second signal wiring supplied with a reference gamma voltage buffered from the gamma buffer integrated circuit embedded in each of the data integrated circuits. The method of claim 6, The second data board, A third signal wiring to which the remaining reference gamma voltages of the plurality of reference gamma voltages are supplied from the reference gamma voltage generator through the second cable; And a fourth signal wiring supplied with a reference gamma voltage buffered from the gamma buffer integrated circuit embedded in each of the data integrated circuits. The method of claim 7, wherein And the signal transmission member is connected to the second signal line and the fourth signal line. The method of claim 7, wherein The data integrated circuit, The gamma buffer integrated circuit, A gamma voltage generator configured to generate a plurality of gamma voltages by subdividing the buffered reference gamma voltages supplied from the embedded gamma buffer integrated circuit and the second and fourth signal lines; A shift register for sequentially outputting a sampling signal, A latch unit for sequentially latching the data signal according to the sampling signal; A digital-analog converter for converting an analog image signal from a data signal from the latch unit using the plurality of gamma voltages; And an output buffer section for supplying an analog image signal from said digital-analog converter to a liquid crystal panel. The method of claim 7, wherein And the signal transmission member is directly formed on the liquid crystal panel so as to be connected to the second signal wiring and the fourth signal wiring. 11. The method of claim 10, The data tape carrier package connected to the first data board so as to be adjacent to the second data board includes a dummy wire connected to the second signal wire and the signal transmission member, And the data tape carrier package connected to the second data board so as to be adjacent to the first data board includes a dummy wire connected to the fourth signal wire and the signal transmission member. .

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