KR101142333B1 - Method for forming contact plug of semiconductor device - Google Patents

Method for forming contact plug of semiconductor device Download PDF

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KR101142333B1
KR101142333B1 KR1020050132219A KR20050132219A KR101142333B1 KR 101142333 B1 KR101142333 B1 KR 101142333B1 KR 1020050132219 A KR1020050132219 A KR 1020050132219A KR 20050132219 A KR20050132219 A KR 20050132219A KR 101142333 B1 KR101142333 B1 KR 101142333B1
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film
forming
tin
semiconductor device
interlayer insulating
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KR20070069761A (en
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김백만
이영진
곽노정
김수현
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택플러그 형성방법을 개시한다. 개시된 본 발명의 방법은, 하부전극과 유전체막 및 상부전극으로 이루어진 캐패시터가 구비된 실리콘기판 상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 기판 전면 상에 Ti막을 형성하는 단계와, 상기 Ti막의 표면을 질화시켜 제1TiN막을 형성하는 단계와, 상기 제1TiN막 상에 제2TiN막을 형성하는 단계와, 상기 제2TiN막 상에 플러그용 금속막을 형성하는 단계와, 상기 층간절연막이 노출될 때까지 플러그용 금속막을 에치백하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for forming a contact plug of a semiconductor device. The disclosed method includes forming an interlayer insulating film on a silicon substrate having a capacitor comprising a lower electrode, a dielectric film, and an upper electrode, etching the interlayer insulating film to form a contact hole, and forming the contact hole. Forming a Ti film on the entire surface of the substrate including the Ti film, forming a first TiN film by nitriding the surface of the Ti film, forming a second TiN film on the first TiN film, and plugging the second TiN film on the second TiN film. Forming a metal film and etching back the plug metal film until the interlayer insulating film is exposed.

Description

반도체 소자의 콘택플러그 형성방법{Method for forming contact plug of semiconductor device}Method for forming contact plug of semiconductor device

도 1a 및 도 1b는 종래 기술의 문제점을 설명하기 위한 도면.1A and 1B are diagrams for explaining the problems of the prior art;

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 콘택플러그 형성방법을 설명하기 위한 공정별 단면도. 2A to 2C are cross-sectional views illustrating processes for forming a contact plug of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체기판 20: 제1층간절연막10 semiconductor substrate 20 first interlayer insulating film

30: 홀 40a: 하부전극30: hole 40a: lower electrode

40b: 유전체막 40c: 상부전극40b: dielectric film 40c: upper electrode

40: 캐패시터 50: 제2층간절연막40: capacitor 50: second interlayer insulating film

60: 콘택홀 70: Ti막60: contact hole 70: Ti film

80: 제1TiN막 90: 제2TiN막80: first TiN film 90: second TiN film

100: 텅스텐막 110: 콘택플러그100: tungsten film 110: contact plug

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게 는, 베리어막(barrier layer)의 증착 불량을 방지하면서 공정 마진을 확보할 수 있는 반도체 소자의 콘택플러그(contact plug) 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to a method for forming a contact plug of a semiconductor device capable of securing a process margin while preventing deposition failure of a barrier layer. It is about.

상기 베리어막은 배선 재료, 예를들어, 플러그용 금속막의 접착력를 증대시키면서, 플러그용 금속막과 기판 실리콘간의 반응이 일어나는 것을 방지하기 위해 형성되는 것으로서, 통상, Ti(티타늄)/TiN(티타늄질화)막이 이용되고 있다. The barrier film is formed to prevent a reaction between the plug metal film and the substrate silicon from occurring while increasing the adhesion of the wiring material, for example, the plug metal film, and typically, a Ti (titanium) / TiN (titanium nitride) film is formed. It is used.

그러나, 상부 베리어막인 TiN막은 증착 공정의 원료 기체인 TiCl4는 환원 기체인 NH3와 반응하여 형성하는데, 이때, 하부 베리어막인 Ti막이 노출되는 경우에 오히려 Ti와 반응하여 Ti를 TiClx(x=2～3)으로 변화시킨다. 도 1a에 나타낸 바와 같이, 이렇게 Ti가 TiClx로 변화된 이후에 TiN막을 그 위에 형성하게 되면 스트레스(stress)에 의해 TiN막이 떨어져 나가는 현상, 즉, TiN막이 필링(peeling)되면서 디펙트 소오스(defect source)로 작용하게 된다.However, the TiN film, the upper barrier film, is formed by reacting TiCl4, which is a raw material gas of the deposition process, with NH3, which is a reducing gas. To 3). As shown in FIG. 1A, when the TiN film is formed thereon after the Ti is changed to TiClx, the TiN film is peeled off due to stress, that is, the TiN film is peeled off and thus a defect source. Will act as.

이로 인해, 상기 상부 베리어막인 TiN막 상에 플러그용 금속막을 증착 한 후, 콘택플러그를 형성하기 위한 플러그용 금속막 에치백(etch back) 공정시, 도 1b에서와 같이, 웨이퍼에 많은 디펙트(defect)가 발생하게 되어, 이 영향으로 수율(yield)이 감소하고 있다.Therefore, after depositing the plug metal film on the TiN film, which is the upper barrier film, during the plug metal film etch back process for forming the contact plug, as shown in FIG. Defect occurs, and yield is decreasing due to this effect.

한편, 이와 같은 문제점을 해결하고자 Ti막 증착 후 질화(nitridation)를 통해 Ti막 표면의 일부를 TiN으로 바꾸어 줌으로써, TiN막 증착시 TiCl4와 Ti의 접촉을 막는 방법을 사용하고 있으나, 상기와 같은 방법은 웨이퍼(wafer)에 가해지는 열(보통 400～600℃)에 의해 Ti막과 NH3를 반응시키는 것인데 질화 효과가 크지 않아 웨이퍼 일부에서는 여전히 디펙트가 발생하고 있다.On the other hand, in order to solve this problem, by changing a part of the surface of the Ti film to TiN through the nitride (nitridation) after the deposition of the Ti film, a method of preventing contact between TiCl4 and Ti during the deposition of the TiN film, but using the same method The Ti film reacts with NH3 by the heat applied to the silver wafer (usually 400 to 600 ° C). However, since the nitriding effect is not great, defects still occur in some of the wafers.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 베리어막의 증착 불량을 방지하면서, 공정 마진을 확보할 수 있는 반도체 소자의 콘택플러그 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a contact plug of a semiconductor device capable of securing a process margin while preventing poor deposition of a barrier film.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 하부전극과 유전체막 및 상부전극으로 이루어진 캐패시터가 구비된 실리콘기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 기판 전면 상에 Ti막을 형성하는 단계; 상기 Ti막의 표면을 질화시켜 제1TiN막을 형성하는 단계; 상기 제1TiN막 상에 제2TiN막을 형성하는 단계; 상기 제2TiN막 상에 플러그용 금속막을 형성하는 단계; 상기 층간절연막이 노출될 때까지 플러그용 금속막을 에치백하는 단계;를 포함하는 반도체 소자의 콘택플러그 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film on a silicon substrate having a capacitor consisting of a lower electrode, a dielectric film and an upper electrode; Etching the interlayer insulating layer to form a contact hole; Forming a Ti film on an entire surface of the substrate including the contact hole; Nitriding the surface of the Ti film to form a first TiN film; Forming a second TiN film on the first TiN film; Forming a plug metal film on the second TiN film; And etching back the plug metal film until the interlayer insulating film is exposed.

여기서, 상기 Ti막의 표면을 질화시키는 단계는 NH3 가스 분위기에서 급속열처리로 수행하는 것을 특징으로 한다.The nitriding of the surface of the Ti film may be performed by rapid heat treatment in an NH 3 gas atmosphere.

상기 NH3 가스는 1000～10000sccm의 유량으로 흘려주는 것을 특징으로 한다.The NH3 gas is characterized by flowing at a flow rate of 1000 ~ 10,000 sccm.

상기 급속열처리는 600～900℃ 온도에서 10～100초 동안 수행하는 것을 특징으로 한다.The rapid heat treatment is characterized in that carried out for 10 to 100 seconds at a temperature of 600 ~ 900 ℃.

상기 플러그용 금속막은 텅스텐막인 것을 특징으로 한다.The plug metal film is a tungsten film.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 콘택플러그 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다. 2A to 2C are cross-sectional views illustrating processes for forming a contact plug of a semiconductor device according to the present invention.

도 2a을 참조하면, 트랜지스터와 같은 하부 패턴(도시안됨)이 형성된 반도체 기판(10)의 전면 상에 제1층간절연막(20)을 증착한다. 그런다음, 상기 제1층간절연막(20)의 소정 부분을 선택적으로 식각하여 상기 기판(10)의 일부분, 예를들어, 접합 영역을 노출시키는 홀(30)을 형성한다. 그런다음, 상기 홀(30)을 포함한 기판(10) 상에 하부전극(40a)과 유전체막(40b) 및 상부전극(40c)으로 이루어진 캐패시터(40)를 형성한다. Referring to FIG. 2A, a first interlayer insulating film 20 is deposited on the entire surface of the semiconductor substrate 10 on which a lower pattern (not shown) such as a transistor is formed. Then, a predetermined portion of the first interlayer insulating film 20 is selectively etched to form a hole 30 exposing a portion of the substrate 10, for example, a junction region. Next, a capacitor 40 including the lower electrode 40a, the dielectric film 40b, and the upper electrode 40c is formed on the substrate 10 including the hole 30.

다음으로, 상기 캐패시터(40)를 포함한 기판 전면 상에 제2층간절연막(50)을 증착한 후, 상기 제2층간절연막(50)과 캐패시터의 상부전극(40c)을 식각하여 콘택홀(60)을 형성한다. 이어서, 상기 콘택홀(60)을 포함한 기판 전면 상에 Ti막(70)을 증착한다.Next, after the second interlayer insulating film 50 is deposited on the entire surface of the substrate including the capacitor 40, the second interlayer insulating film 50 and the upper electrode 40c of the capacitor are etched to contact the contact hole 60. To form. Subsequently, a Ti film 70 is deposited on the entire surface of the substrate including the contact hole 60.

도 2b를 참조하면, 상기 Ti막(70)의 표면을 질화(nitridation)시켜 제1TiN막(80)을 형성한다. 여기서, 상기 Ti막(70)의 표면을 질화시켜 제1TiN막(80)으로 형성하는 것은 NH3 가스 분위기에서 급속열처리(Rapid Thermal Annealing)로 수행한다. 이때, 상기 NH3 가스는 1000～10000sccm의 유량으로 흘려주면서, 상기 급속열처리는 600～900℃ 온도에서 10～100초 동안 수행하는 한다.Referring to FIG. 2B, the first TiN film 80 is formed by nitriding the surface of the Ti film 70. Here, nitriding the surface of the Ti film 70 to form the first TiN film 80 is performed by rapid thermal annealing in an NH 3 gas atmosphere. At this time, the NH 3 gas is flowed at a flow rate of 1000 ~ 10,000 sccm, the rapid heat treatment is performed for 10 to 100 seconds at a temperature of 600 ~ 900 ℃.

여기서, 본 발명은 Ti막(70)에 고온으로 급속열처리를 수행함으로써, 상기 Ti막(70)의 질화(nitridation) 효과를 극대화시킬 수 있다. 따라서, 후속 TiN막 증착시 TiN막의 원료기체인 TiCl4와 Ti막의 Ti와의 접촉을 막을 수 있어 TiN막이 필링(peeling)되는 현상을 방지할 수 있다.Here, the present invention can maximize the nitriding effect of the Ti film 70 by performing a rapid heat treatment at a high temperature to the Ti film 70. Therefore, in the subsequent deposition of the TiN film, contact between TiCl 4, which is a raw material of the TiN film, and Ti of the Ti film can be prevented, thereby preventing the TiN film from peeling.

또한, 본 발명은 상기와 같은 급속열처리로 인해 캐패시터(40)의 상부전극(40c)과 Ti막(70)이 접촉한 곳에서 비저항이 낮은 C54상의 TiSi2가 형성될 수 있기 때문에 접촉 저항이 기존보다 낮아지는 효과를 얻을 수 있다.In addition, in the present invention, since the rapid thermal treatment as described above, the contact resistance is higher than that of TiSi 2 having a low specific resistance, because the upper electrode 40c of the capacitor 40 and the Ti film 70 may be formed. A lowering effect can be obtained.

도 2c를 참조하면, 상기 Ti막이 질화처리되어 형성된 제1TiN막(80) 상에 제2TiN막(90)을 증착한다. 그런다음, 상기 제2TiN막(90) 상에 플러그용 금속막으로 텅스텐막(100)을 증착한 후, 상기 제2층간절연막(50)이 노출될 때까지 텅스텐막(100)을 에치백하여 본 발명에 따른 콘택플러그(contact plug; 110)를 형성한다.Referring to FIG. 2C, a second TiN film 90 is deposited on the first TiN film 80 formed by nitriding the Ti film. Then, after depositing a tungsten film 100 on the second TiN film 90 with a metal film for plugging, the tungsten film 100 is etched back until the second interlayer insulating film 50 is exposed. A contact plug 110 according to the invention is formed.

전술한 바와 같이, 본 발명은 600～900℃ 온도에서 급속열처리를 수행함으로써, Ti막(70)을 충분히 질화시켜 제1TiN막(80)으로 형성한다. 이로 인해, 상기 제1TiN(80)막 상에 제2TiN막(90)의 증착에서의 필링(peeling)을 방지할 수 있어 소자의 수율 향상을 기대할 수 있다. As described above, in the present invention, the Ti film 70 is sufficiently nitrided to form the first TiN film 80 by performing rapid heat treatment at a temperature of 600 to 900 ° C. As a result, peeling in the deposition of the second TiN film 90 on the first TiN 80 film can be prevented, and the yield of the device can be improved.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 베리어막인 Ti막에 대해 800℃ 이상의 고온과 NH3 분위기의 급속열처리를 수행함으로써, 질화(nitridation)를 극대화시킬 수 있다. 이로 인해, 베이어막인 TiN막 증착에서의 필링(peeling) 현상을 방지할 수 있어, 소자의 수율 향상을 기대할 수 있다.As described above, according to the present invention, nitriding can be maximized by performing a rapid heat treatment of a high temperature of 800 ° C. or higher and an NH 3 atmosphere for the Ti film, which is a barrier film. For this reason, the peeling phenomenon in vapor deposition of the TiN film which is a Bayer film can be prevented, and the yield of an element can be expected to be improved.

또한, 본 발명은 급속열처리로 인해 캐패시터의 상부전극과 Ti막이 접촉한 곳에서 비저항이 낮은 C54상의 TiSi2가 형성될 수 있기 때문에 접촉 저항이 기존보다 낮아지는 효과를 얻을 수 있다.In addition, the present invention can obtain the effect that the contact resistance is lower than the conventional one because the C54 phase TiSi2 with low specific resistance can be formed in the place where the upper electrode of the capacitor and the Ti film contact due to the rapid heat treatment.

Claims (5)

하부전극과 유전체막 및 상부전극으로 이루어진 캐패시터가 구비된 실리콘기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on a silicon substrate having a capacitor including a lower electrode, a dielectric film, and an upper electrode; 상기 층간절연막과 캐패시터의 상부전극을 식각하여 콘택홀을 형성하는 단계;Forming a contact hole by etching the upper electrode of the interlayer insulating layer and the capacitor; 상기 콘택홀을 포함한 기판 전면 상에 Ti막을 형성하는 단계;Forming a Ti film on an entire surface of the substrate including the contact hole; 상기 Ti막의 표면을 질화시켜 제1TiN막을 형성하는 단계;Nitriding the surface of the Ti film to form a first TiN film; 상기 제1TiN막 상에 제2TiN막을 형성하는 단계;Forming a second TiN film on the first TiN film; 상기 제2TiN막 상에 플러그용 금속막을 형성하는 단계;Forming a plug metal film on the second TiN film; 상기 층간절연막이 노출될 때까지 플러그용 금속막을 에치백하는 단계;Etching back the plug metal film until the interlayer insulating film is exposed; 를 포함하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.Contact plug forming method of a semiconductor device comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1 항에 있어서, The method of claim 1, 상기 Ti막의 표면을 질화시키는 단계는 NH3 가스 분위기에서 급속열처리로 수행하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The step of nitriding the surface of the Ti film is a method of forming a contact plug of a semiconductor device, characterized in that to perform a rapid heat treatment in an NH 3 gas atmosphere. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제 2 항에 있어서, The method of claim 2, 상기 NH3 가스는 1000～10000sccm의 유량으로 흘려주는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The method for forming a contact plug of a semiconductor device, characterized in that the NH3 gas flows at a flow rate of 1000 ~ 10,000 sccm. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제 2 항에 있어서, The method of claim 2, 상기 급속열처리는 600～900℃ 온도에서 10～100초 동안 수행하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The rapid heat treatment is a contact plug forming method of a semiconductor device, characterized in that performed for 10 to 100 seconds at 600 ~ 900 ℃ temperature. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제 1 항에 있어서, The method of claim 1, 상기 플러그용 금속막은 텅스텐막인 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.And said plug metal film is a tungsten film.
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