KR0172770B1 - Method of forming barrier metal layer including silicide - Google Patents

Method of forming barrier metal layer including silicide Download PDF

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KR0172770B1
KR0172770B1 KR1019950003735A KR19950003735A KR0172770B1 KR 0172770 B1 KR0172770 B1 KR 0172770B1 KR 1019950003735 A KR1019950003735 A KR 1019950003735A KR 19950003735 A KR19950003735 A KR 19950003735A KR 0172770 B1 KR0172770 B1 KR 0172770B1
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layer
metal layer
barrier metal
forming
silicide
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KR1019950003735A
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KR960032607A (en
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장현진
홍택기
문영화
전영호
홍흥기
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조공정 중 실리사이드층 형성방법에 있어서, 소정 패턴이 형성된 웨이퍼의 전체구조 표면에 금속층(12)과 실리콘층(13)을 차례로 형성하는 제1단계; 및 상기 전체 웨이퍼를 열처리하는 제2단계를 포함하는 것을 특징으로 하여, 실리사이드층(14) 형성시 하부층을 구성하는 실리콘 원자의 소모를 최소화할 수 있어, 즉 금속층(2)이 하부층에 미치는 영향을 최소화할 수 있으며, 안정한 접촉저항을 얻을 수 있고, 또한 누설전류 발생을 방지할 수 있어 제품의 신뢰성 및 제조 수율을 증대시킬 수 있는 특유의 효과가 있는 실리사이드층 형성방법에 관한 것이다.The present invention provides a method for forming a silicide layer in a semiconductor device manufacturing process, comprising: a first step of sequentially forming a metal layer (12) and a silicon layer (13) on a surface of an entire structure of a wafer on which a predetermined pattern is formed; And a second step of heat-treating the entire wafer, so that the consumption of silicon atoms constituting the lower layer when the silicide layer 14 is formed can be minimized, that is, the effect of the metal layer 2 on the lower layer can be minimized. The present invention relates to a method of forming a silicide layer having a unique effect of minimizing, obtaining stable contact resistance, and preventing leakage current to increase product reliability and manufacturing yield.

Description

실리사이드를 포함하는 장벽금속층 형성방법Method of forming barrier metal layer containing silicide

제1도는 종래기술에 따라 실리사이드를 포함하는 장벽금속층이 형성된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device in which a barrier metal layer including silicide is formed according to the prior art.

제2a도 및 제2b도는 본 발명의 일실시예에 따른 장벽금속층 형성 공정 단면도.2a and 2b is a cross-sectional view of the barrier metal layer forming process according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 실리콘기판 12 : 티타늄층11 silicon substrate 12 titanium layer

13 : 실리콘층 14 : 티타늄실리사이드층13: silicon layer 14: titanium silicide layer

15 : 티타늄나이트라이드층 16 : 게이트15 titanium nitride layer 16 gate

17 : 층간절연막17: interlayer insulating film

본 발명은 반도체 기술에 관한 것으로, 특히 실리사이드를 포함하는 장벽금속층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method of forming a barrier metal layer comprising silicide.

일반적으로, 실리사이드층은 증간접속(Interconnection)층 및 스텝 커버리지(Step coverage) 개선을 위한 웨팅층(Weting layer) 형성을 위하여 사용된다.In general, the silicide layer is used to form a wetting layer for improving an interconnection layer and step coverage.

첨부된 도면 제1도는 종래기술에 따라 형성된 타타늄실리사이드를 포함하는 반도체 소자의 단면을 도시한 것으로, 이하 이를 참조하여 종래기술을 살펴본다.1 is a cross-sectional view of a semiconductor device including a titanium silicide formed according to the prior art, the following description of the prior art.

종래에는 층간절연막(5)을 관통하여 접합영역(n+)을 노출시키는 콘택홀이 형성된 실리콘기판(1) 전체구조 상부에 티타늄층(2) 및 티타늄나이트라이드층(3)을 차례로 형성하며, 이때 열공정으로 인하여 실리콘(Si)과 티타늄(Ti)이 반응하여 타타늄실리사이드층(4)을 형성하게 된다. 이렇게 형성된 티타늄실리사이드층(4)이 오믹 접촉(Ohmic contact)을 제공하여 콘택저항을 개선하게 된다. 미설명 도면 부호 '4'는 게이트를 나타낸 것이다.Conventionally, a titanium layer 2 and a titanium nitride layer 3 are sequentially formed on the entire structure of the silicon substrate 1 having contact holes through the interlayer insulating film 5 to expose the junction region n + . At this time, due to the thermal process, silicon (Si) and titanium (Ti) react to form the titanium silicide layer 4. The titanium silicide layer 4 thus formed provides ohmic contact, thereby improving contact resistance. Unexplained reference numeral 4 denotes a gate.

그러나, 상기 제1도에 도시된 바와 같이 종래에는 실리사이드층 형성시 기판의 실리콘 원자(Si)와 장벽금속층(예를 들어, 티타늄층)의 금속 원소가 반응하기 때문에, 접합영역의 실리콘 원자(Si)의 소모로 인하여 접합 특성이 열화되는 문제점이 있었다. 또한, 실리사이드층 형성시 기판 내부로 침투하는 금속 원자는 누설 전류를 발생시켜 소자의 신뢰도를 저하시키는 문제점이 있었다.However, as shown in FIG. 1, conventionally, since silicon atoms (Si) of the substrate and metal elements of the barrier metal layer (for example, titanium layer) react during formation of the silicide layer, the silicon atoms (Si) of the junction region are reacted. ), There was a problem that the bonding properties deteriorated due to the consumption of In addition, the metal atoms penetrating into the substrate when the silicide layer is formed, there is a problem to reduce the reliability of the device by generating a leakage current.

이러한 문제점은 반도체 소자의 고집적화 의해 접합영역(n+)이 점점 앝아지고 있는 추세에 따라 더욱 큰 문제점으로 부각되고 있다.This problem is becoming a bigger problem as the junction area (n + ) is gradually decreasing due to high integration of semiconductor devices.

따라서, 본 발명은 안정한 콘택저항을 얻을 수 있고, 누설전류 발생을 억제할 수 있는 실리사이드를 포함하는 장벽금속층 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a barrier metal layer including silicide capable of obtaining stable contact resistance and suppressing leakage current generation.

상기 목적을 달성하기 위하여 본 발명은 실리사이드를 포함하는 장벽금속층 형성방법에 있어서, 콘택홀이 형성된 웨이퍼 전체구조 표면을 다라 제1 장벽금속층을 형성하는 제1단계; 상기 제1 장벽금속층 상에 실리콘층을 형성하는 제2단계; 및 열처리를 실시하여 상기 제1 장벽금속층 및 상기 실리콘층을 이루는 원소간의 반응에 의해 실리사이드막을 형성하는 제3단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for forming a barrier metal layer including silicide, comprising: a first step of forming a first barrier metal layer on the entire surface of a wafer on which contact holes are formed; Forming a silicon layer on the first barrier metal layer; And a third step of performing a heat treatment to form a silicide film by a reaction between the elements forming the first barrier metal layer and the silicon layer.

본 발명은 실리사이드화가 가능한 장벽금속층 상부에 실리콘층(단결정, 다결정 모두 가능)을 제공함으로써 실리사이드층 형성에 의해 접합영역에 미치는 영향을 최소화하는 기술이다.The present invention provides a silicon layer (both single crystal and polycrystalline) on top of the silicideable barrier metal layer, thereby minimizing the influence on the junction region by forming the silicide layer.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있도록 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art may easily implement the present invention.

첨부된 도면 제2a도 및 제2b도는 본 발명의 일실시예에 따른 장벽금속층 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.2A and 2B are views illustrating a barrier metal layer forming process according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the drawings.

먼저, 제2a도에 도시된 바와 같이 게이트(16) 접합영역(n+)을 비롯한 하부 구조가 형성된 실리콘기판(11) 상에 층간절연막(17)을 증착하고 이를 선택 식각하여 접합영역(n+)을 노출시키는 콘택홀을 형성한다. 이어서, 스퍼터링(Sputtering) 시스템에 티타늄 타겟, 실리콘 타겟, 티타늄나이트라이드 타겟을 각각 장착한 후, 실리콘기판(11) 전체구조 상부에 장벽금속층인 티타늄층(12)을 증착하고 그 상부에 실리콘층(13)을 증착한다. 이때, 실리콘층(13)은 300Å 이하의 두께로 증착하는 것이 바람직하다.First, as shown in FIG. 2A, the interlayer insulating layer 17 is deposited on the silicon substrate 11 having the lower structure including the gate 16 junction region n + , and selectively etched to form the junction region n +. To form a contact hole exposing Subsequently, after mounting the titanium target, the silicon target, and the titanium nitride target in the sputtering system, the titanium layer 12, which is a barrier metal layer, is deposited on the entire structure of the silicon substrate 11 and the silicon layer 13) is deposited. At this time, the silicon layer 13 is preferably deposited to a thickness of 300 kPa or less.

이어서, 제2b도에 도시된 바와 같이 실리콘층(13) 형성 후 곧바로 어닐(Anneal) 챔버에서 열처리를 실시하여 티타늄실리사이드층(14)을 형성하고, 전체구조 표면에 타타늄나이트라이드층(15)을 형성한다. 이때, 열처리(어닐링)는 550℃ 이상의 고온에서 실시하며, 주된 실리사이드 반응이 실리콘층(13)과 티타늄층(12)에서 일어나기 때문에 실리사이드 형성시 접합영역(n+)에 미치는 영향을 최소화할 수 있다.Subsequently, as shown in FIG. 2B, immediately after the silicon layer 13 is formed, a heat treatment is performed in an anneal chamber to form the titanium silicide layer 14, and the titanium nitride layer 15 is formed on the entire structure surface. To form. At this time, the heat treatment (annealing) is carried out at a high temperature of 550 ℃ or more, and since the main silicide reaction occurs in the silicon layer 13 and the titanium layer 12, it is possible to minimize the effect on the junction region (n + ) when forming the silicide. .

참고적으로, 모든 공정은 고진공 상태에서 인-시츄(In-situ)로 실시하는 것이 효과적이며, 이렇게 형성되는 실리사이드층은 타타늄나이트라이드층 없이 주 금속층인 알루미늄막의 웨팅층으로 사용할 수도 있다.For reference, it is effective to perform all processes in-situ in a high vacuum state, and the silicide layer thus formed may be used as a wetting layer of an aluminum film, which is a main metal layer, without a titanium nitride layer.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변환 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, conversions, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 접합영역에서의 실리사이드 반응을 최소화하여 접합영역 내의 실리콘 원자의 소모를 억제하고 장벽금속 원소의 접합영역에의 확산에 의한 접합 누설전류 발생을 억제하는 효과가 있으며, 이에 따라 안정한 콘택저항을 얻을 수 있어 소자의 신뢰성 및 수율을 증대시키는 효과가 있다.The present invention as described above has the effect of minimizing the silicide reaction in the junction region to suppress the consumption of silicon atoms in the junction region and suppress the generation of junction leakage current by diffusion of the barrier metal element into the junction region, thereby It is possible to obtain stable contact resistance, thereby increasing the reliability and yield of the device.

Claims (6)

실리사이드를 포함하는 장벽금속층 형성방법에 있어서, 콘택홀이 형성된 웨이퍼 전체구조 표면을 따라 제1 장벽금속층을 형성하는 제1단계; 상기 제1 장벽금속층 상에 실리콘층을 형성하는 제2단계; 및 열처리를 실시하여 상기 제1 장벽금속층 및 상기 실리콘층을 이루는 원소간의 반응에 의해 실리사이드막을 형성하는 제3단계를 포함하여 이루어진 실리사이드를 포함하는 장벽금속층 형성방법.1. A method of forming a barrier metal layer comprising silicide, the method comprising: a first step of forming a first barrier metal layer along a surface of a wafer entire structure in which contact holes are formed; Forming a silicon layer on the first barrier metal layer; And performing a heat treatment to form a silicide film by a reaction between the elements forming the first barrier metal layer and the silicon layer. 제1항에 있어서, 상기 제1 장벽금속층이 티타늄층인 것을 특징으로 하는 실리사이드를 포함하는 장벽금속층 형성방법.The method of claim 1, wherein the first barrier metal layer is a titanium layer. 제1항에 있어서, 상기 실리콘층이 300Å 이하의 두께로 형성되는 것을 특징으로 하는 실리사이드를 포함하는 장벽금속층 형성방법.The method of claim 1, wherein the silicon layer is formed to a thickness of about 300 GPa or less. 제1항에 있어서, 상기 열처리가 550℃ 이상의 온도에서 실시되는 것을 특징으로 하는 실리사이드를 포함하는 장벽금속층 형성방법.The method of claim 1, wherein the heat treatment is performed at a temperature of 550 ° C. or higher. 제1항에 있어서, 상기 제1 장벽금속층 및 상기 실리콘층이 동일한 스퍼터링 시스템에서 형성되는 것을 특징으로 하는 실리사이드를 포함하는 장벽금속층 형성방법.The method of claim 1, wherein the first barrier metal layer and the silicon layer are formed in the same sputtering system. 제2항에 있어서, 상기 제3단계 수행 후, 상기 실리사이드막 상에 티타늄나이트라이드층을 형성하는 제4단계를 더 포함하여 이루어진 것을 특징으로 하는 실리사이드를 포함하는 장벽금속층 형성방법.3. The method of claim 2, further comprising a fourth step of forming a titanium nitride layer on the silicide layer after performing the third step. 4.
KR1019950003735A 1995-02-24 1995-02-24 Method of forming barrier metal layer including silicide KR0172770B1 (en)

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