KR101104643B1 - Asynchronous e-fuse OTP memory cell and asynchronous e-fuse OTP memory device - Google Patents

Abstract

The present invention relates to an OTP memory cell and an OTP memory device. In particular, the present invention relates to a large channel width in an e-fuse cell to realize a low-power device by reducing operating current by reducing parasitic capacitances in bit lines and word lines. An asynchronous eFuse OTP memory cell and an asynchronous eFuse OTP memory device having a transistor for a program mode having a transistor and a transistor for a read mode having a small channel width.

According to the asynchronous E-Fuse OTP memory device according to the present invention, the parasitic capacitance of the word line and the bit line can be reduced in the read mode, thereby reducing the operating current of the read mode.

In addition, the use of a separate I / O method and the asynchronous interface method has the advantage that the memory device can be implemented.

OTP memory device, asynchronous, OTP cell, e-fuse

Description

Asynchronous e-fuse OTP memory cell and asynchronous e-fuse OTP memory device

The present invention relates to an OTP memory cell and an OTP memory device. In particular, the present invention relates to a large channel width in an e-fuse cell to realize a low-power device by reducing operating current by reducing parasitic capacitances in bit lines and word lines. An asynchronous e-fuse OTP memory cell and an asynchronous e-fuse OTP memory device having a program mode transistor having a transistor and a read mode transistor having a small channel width.

In general, nonvolatile memories such as EPROM, EEPROM, and flash memory are used for a main control unit (MCU), a power integrated circuit (Power IC), a display driving chip, and a CMOS image sensor.

However, these nonvolatile memories require additional processing that results in long turn-around time (TAT), increased complexity, lower reliability, and higher manufacturing costs. As a result, many OTP (One-Time Programmable) memory devices that can be designed based on e-fuse or anti-fuse logic processes without additional processes are used.

Anti-fuse OTP memory cells are electrically shorted by applying a voltage higher than the breakdown voltage to a thin gate oxide. The antifuse OTP memory device requires a logic transistor and a 5V medium voltage (MV) transistor because the program voltage is 5.5V to 8.5V.

However, in the process of providing only logic transistor and 3.3V intermediate voltage transistor, antifuse OTP is not suitable because the 3.3V transistor cannot be tolerated at the program voltage. On the other hand, the electric fuse (e-fuse) OTP cell blows the e-fuse by blowing an overcurrent of about 10 mA to 20 mA through the polysilicon gate to selectively blow the fuse. In the case of e-fuse, a 3.3V transistor can be programmed.

1 is a circuit diagram showing a conventional e-fuse cell.

As shown in FIG. 1, the conventional e-fuse cell 100 includes an e-fuse device 110 and an NMOS transistor 120. Before the program, the e-fuse device has a resistance of about 50 to 100 Ω. In the case of blowing the fuse, if the I / O interface voltage VIO (= 3.3 V) is applied to the bit line (BL) and the word line (WL), the fuse element 110 And the program current flows through the NMOS transistor 120, the resistance of the e-fuse device 110 becomes a few 100 kΩ or more. As such, the e-fuse element 110 is programmed in one of a conductive state and a highly resistive state.

However, in the conventional e-fuse cell, since the program operation and the read operation are performed by MN0, which is the NMOS transistor shown in FIG. 1, the channel width of the NMOS transistor must be large to satisfy the program current. In addition, the metal width of the bit line BL must be large in order to reduce the parasitic resistance of the bit line BL to reduce the program voltage.

However, in this case, since the parasitic capacitance of the word line WL and the bit line BL increases, there is a problem in that an operating current due to switching in the read mode increases.

It is an object of the present invention to provide an asynchronous e-fuse OTP memory cell capable of reducing the area occupied by an OTP memory cell array and reducing parasitic capacitance of word lines and bit lines.

Another object of the present invention is to provide an asynchronous e-fuse OTP memory device including an OTP memory cell array composed of the asynchronous e-fuse OTP memory cells.

In order to achieve the above object, the asynchronous E-Fuse OTP memory cell according to the present invention includes a first NMOS transistor and a first terminal having a first terminal connected to a ground voltage and a program word line signal WWL applied to the gate thereof. Is connected to the bit line BL, the second terminal is connected to the second terminal of the first NMOS transistor, and the second NMOS transistor and the first terminal to which the read word line signal RWL is applied to the gate thereof. And an e-fuse device 330 connected to the source line SL and having a second terminal connected to the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor in common. It is done.

In order to achieve the above another object, an asynchronous e-Fuse OTP memory device according to the present invention, at least two source lines, at least two bit lines, at least two program word lines, at least two read word lines, each connected at least An e-fuse OTP memory cell array in which two or more asynchronous e-fuse OTP memory cells are disposed, a control unit for generating mode control signals instructing an operation such as a program mode or a read mode of the e-fuse OTP memory device; A power switch circuit for supplying a logic voltage VDD or an interface voltage VIO to the eFuse OTP memory cell array in response to a mode control signal, a row decoder for decoding a row address signal, the mode control signal and a decoded row address The at least two program word lines in response to a signal and A word decoder for decoding at least two read word lines; a column decoder for decoding a column address signal; a source line driver circuit for driving a corresponding source line in response to the mode control signal and a data input signal; and a response to the mode control signal; And a bit line sense amplifier circuit for sensing and amplifying the bit line.

According to the asynchronous E-Fuse OTP memory device according to the present invention, the parasitic capacitance of the word line and the bit line can be reduced in the read mode, thereby reducing the operating current of the read mode.

In addition, the use of a separate I / O method and the asynchronous interface method has the advantage that the memory device can be implemented.

In order to fully understand the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings, which are provided for explaining exemplary embodiments of the present invention, and the contents of the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an asynchronous e-fus OTP memory device according to an embodiment of the present invention.

Referring to FIG. 2, the asynchronous eFuse OTP memory device 200 according to an exemplary embodiment of the present invention may include an eFuse OTP memory cell array 210, a controller 220, and a power switch of 128 rows × 9 columns × 1Kb. A circuit 230, a row decoder 240, a word line driver circuit 250, a column decoder 260, a source line driver circuit 270, and a bit line sense amplification circuit 280.

Each of the eFuse OTP memory cell arrays 210 includes at least two source lines, at least two bit lines, at least two program word lines, at least two read word lines, and at least two source line switch enable signal lines, respectively. At least two asynchronous eFuse OTP memory cells that are connected are disposed.

The controller 220 controls mode control signals GPM_ENb, WWL, and RWL instructing operation of a program mode, a read mode, and a standby mode of the asynchronous EFuse OTP memory device 200 according to control signals PGM and READ. , RD_EN ...)

The power switch circuit 230 switches the logic voltage VDD or the interface voltage VIO in response to the mode control signal to supply to the eFuse OTP memory cell array 210 according to an operation mode.

The row decoder 440 decodes the row address signal RA [6: 0] to generate decoded row address signals.

The word line driver circuit 250 may include the at least two program word line signals in response to a word line enable program signal WLEN_PGM, a word line enable read signal WLEN_RD, and a decoded row address signal among the mode control signals. (WWL) and at least two read wordline signals RWL.

The column decoder 260 decodes the column address signal CA [2: 0] to generate decoded column address signals WY.

The source line driving circuit 270 drives the corresponding source line in response to an internal program signal IPGM and a data input signal WD among the mode control signals.

The bit line sense amplification circuit 280 senses the bit line BL voltage according to whether or not the e-fuse of the OTP cell is programmed in the read mode and outputs digital data to the output port.

The main features of the asynchronous E-Fuse OTP memory device according to the present invention are shown in Table 1.

3A is a circuit diagram illustrating an asynchronous EFuse OTP memory cell in accordance with an embodiment of the present invention.

As shown in FIG. 3A, an asynchronous e-fuse OTP memory cell according to an exemplary embodiment includes a first NMOS transistor 310, a second NMOS transistor 320, and an e-fuse device 330.

A first terminal of the first NMOS transistor 310 is connected to a ground voltage VSS, and a program word line signal WWL is applied to its gate. The first NMOS transistor 310 has a large channel width and is used for a program mode.

A first terminal of the second NMOS transistor 320 is connected to a bit line BL, a second terminal of the second NMOS transistor 320 is connected to a second terminal of the first NMOS transistor 310, and a read word line signal RWL is connected to a gate thereof. Is applied to. The second NMOS transistor 320 has a small channel width and is used for a read mode.

In the eFuse device 330, a first terminal is connected to the source line SL, and a second terminal is common to the second terminal of the first NMOS transistor 310 and the second terminal of the second NMOS transistor 320. Connected. The e-fuse device 330 has a resistance of about 50 Ω to about 100 Ω before programming.

FIG. 3B is a photograph showing a layout of an asynchronous eFuse OTP memory cell according to an embodiment of the present invention, and FIG. 3C is a circuit diagram of an asynchronous eFuse OTP memory cell array according to an embodiment of the present invention.

3C shows an eFuse OTP memory cell array of 128 rows by 8 columns in one embodiment.

Table 2 shows the bias voltage conditions for each node according to the operation mode of the asynchronous EFuse OTP memory cell according to the present invention.

Referring to Table 2, the program word line WWL selected in the program mode is activated as VIO. At this time, since the unselected program word line WWL maintains 0V, the e-fuse element 310 of the OTP cell is isolated from the bit line BL.

In programming mode, to program the E-Fuse OTP cell, VDD is applied to the input port DIN and pulse is applied to the program signal PGM. The voltage of VIO is applied to the source line SL and the program word line WWL. Program current flows through the e-fuse 330 and the first NMOS transistor 310. In this way, the e-fuse element 330 is programmed and the resistance of the e-fuse element 330 is several hundred kΩ or more.

If the cell is not programmed, 0V is applied to the input port DIN and the source line SL maintains 0V, so the resistance of the e-fuse device 330 is not changed. When a logic '1' is applied to an input port DIN in an eFuse OTP memory device according to the present invention, an eFuse OTP memory cell is programmed and a logic '0' is applied to an input port DIN. Fuse OTP memory cells are not programmed.

Meanwhile, in the read mode, the bit line BL is precharged to the logic voltage VDD and one of the 128 read word lines RWL is decoded by the decoded signal of the row address signal RA [6: 0]. Only the read word line RWL is activated to the logic voltage VDD.

In the case of a cell in which an e-fuse device is not programmed, a current path is provided through the second NMOS transistor 320 and the e-fuse device 330 of FIG. 3A, so that the bit line BL is discharged to 0V and the output port DOUT. ), Logic '0' is output.

In the programmed cell, since the e-fuse device 330 is in a highly resistive state and the bit line BL is precharged with the logic voltage VDD, a logic is provided at the output port DOUT. '1' is output.

In the present invention, to implement a low-power, low-area eFuse OTP memory device, an asynchronous interface and a separate I / O method using separate input and output ports are used.

4A is a timing diagram in a program mode of an asynchronous eFuse OTP memory device according to the present invention, and FIG. 4B is a timing diagram in a read mode of an asynchronous eFuse OTP memory device according to the present invention.

As shown in FIG. 4A, in the program mode, a bit of data input signal is input to an OTP memory cell selected when the program signal PGM is activated high while the data of the address and the input port DIN are first applied. Program through the input port (DIN).

In the read mode, as shown in FIG. 4B, when an address to be read is first applied and then a read signal READ is activated high, the byte data of the selected cell has an output port after the access time has passed. DOUT). At this time, the program signal PGM maintains a low state.

FIG. 5 is a diagram illustrating a word line driver circuit of the asynchronous EFuse OTP memory device of FIG. 2.

Referring to FIG. 5, the word line driving circuit 250 of the e-fuse OTP memory device according to an exemplary embodiment of the present invention may include a first NAND gate 21 and a word line to input row address signals RA210 and RA543. In response to the enable program signal WLEN_PGM and the inverted word line enable program signal WLENb_PGM, a first transfer gate 22 and a logic voltage VDD that transfer an output of the first NAND gate 41 are included. A first PMOS transistor 23 and a first transfer gate connected to a source, the word line enable program signal WLEN_PGM connected to a gate thereof, and an output of the first transfer gate 22 connected to a drain thereof; A second inverter 24 that inputs the output of 22, a third NMOS transistor 25 whose ground voltage VSS is connected to its source and the output of the first transfer gate 22 is connected to its gate. Ground voltage VSS is connected to a source thereof and The fourth NMOS transistor 26 having its output connected to its gate, an interface voltage VIO connected to its source, and the drain of the fourth NMOS transistor 26 connected to its gate and A second PMOS transistor 27 having a drain of the third NMOS transistor 25 connected to the drain thereof, the interface voltage VIO is connected to a source thereof, and a drain of the third NMOS transistor 25 is connected thereto. A third PMOS transistor 28 connected to a gate and the drain of the fourth NMOS transistor 26 is connected to the drain thereof, driven by the interface voltage VIO and of the third NMOS transistor 25. The word line enable read signal inverted with the output of the third inverter 29 and the first NAND gate 21 having a drain connected to its input terminal and an inverted program word line signal WWLb connected to its output terminal. (WLENb_RD) The first word is line (RWL), a read receiving input is connected to the output terminal and a NOR gate (30).

As shown in FIG. 5, when the word line driving circuit 250 enters the program mode, the word inverted from the word line enable program signal WLEN_PGM selected by the signal A6 decoded by the row decoder 240. The line enable program signal WLENb_PGM becomes logic '1' and logic '0', respectively. In this state, only the program word line WWL selected by decoding the row address A [6: 0] is driven by VIO and the unselected program word line WWL is maintained at 0V.

FIG. 6 is a diagram illustrating a source line driving circuit of the asynchronous EFuse OTP memory device of FIG. 2. FIG.

Referring to FIG. 6, the source line driving circuit 270 of the asynchronous EFuse OTP memory device may include a second NAND gate that receives a column address signal WY and a data input signal WD decoded by the column decoder. 50), a fourth inverter 51 receiving the internal program signal IPGM generated by the controller, a fifth inverter 52 receiving the output of the fourth inverter 51, and the internal program signal IPGM. ) And a second transfer gate 53 which transfers the output of the second NAND gate 50 in response to the inverted internal program signal IPGMb, and a logic voltage VDD connected to a first terminal and connected to a second terminal. A fourth PMOS transistor 54 to which the output of the second transfer gate 53 is connected and the internal program signal IPGM is applied to the gate, and a sixth to input the output of the second transfer gate 53. Inverter 59, ground voltage VSS is connected to its source and the second transfer gate 53 A fifth NMOS transistor 55 having an output of which is connected to its gate, a ground voltage VSS connected to its source, and a sixth NMOS transistor having an output of the sixth inverter 59 connected to its gate 56) a second voltage connected to the source of the interface voltage VIO, a drain of the sixth NMOS transistor 56 to a gate thereof, and a drain of the fifth NMOS transistor 55 to a drain thereof; 5 PMOS transistor 57, the interface voltage (VIO) is connected to its source, the drain of the fifth NMOS transistor 55 is connected to its gate and the drain of the sixth NMOS transistor 56 is A seventh inverter 60 driven by the sixth PMOS transistor 58 connected to the drain and the interface voltage VIO, and a drain of the fifth NMOS transistor 55 connected to an input terminal thereof; 7 Half the output of the inverter Which includes an eighth inverter (61).

The source line driver circuit 270 supplies the interface voltage VIO to the anode of the e-fuse device in the program mode. When the data input signal WD of the input port DIN is logic '1', the interface voltage VIO is supplied to the source line SL, and the data input signal WD of the input port DIN is logic '. In the case of 0 ', the source line SL is driven at 0V. In the read mode, since the internal program signal IPGM is logic '0', the source line SL drives 0V.

FIG. 7 is a diagram illustrating a bit line sense amplifier circuit of the asynchronous EFuse OTP memory device of FIG. 2.

Referring to FIG. 7, the bit line detection amplification circuit 280 of the e-fuse OTP memory device according to the present invention includes a ninth inverter 71 for inputting a precharge signal PRECHARGE, and the logic voltage VDD. A seventh PMOS transistor 72 connected to a source, an output of the ninth inverter 71 connected to a gate thereof, and the bit line BL connected to a drain thereof, and the logic voltage VDD An eighth PMOS transistor 73 connected with a bit BL connected to a drain thereof and an inverted bit line load signal BL_LOADb connected to a gate thereof, and a tenth inputting an inverted sensing enable signal SAENb An inverter 74, a ninth PMOS transistor 75 having a logic voltage VDD connected to a source thereof, and a bit line BL connected to a gate thereof, and a drain of the ninth PMOS transistor connected to a source thereof The connected and inverted sensing enable signal SAENb is connected to its gate. A seventh NMOS transistor 77 and a seventh PMOS transistor 76 and a drain of the tenth PMOS transistor 76 connected to the drain thereof, and an output of the tenth inverter connected to the gate thereof; The source of the NMOS transistor is connected to the drain thereof, the ground voltage VSS is connected to the source thereof, and the bit line BL is connected to the gate thereof. A latch 79 for latching the drain and outputting digital data to the output port DOUT is provided.

The E-Fuse OTP memory device according to the present invention is programmed in units of bits and performs read operations in units of bytes. In the read mode, the seventh PMOS transistor 72 is turned on by a short pulse precharge signal PRECHARGE before the read word line RWL is activated. Precharged to (VDD).

The bit line BL connected to the cell programmed with logic '1' while the read word line RWL is activated maintains the logic voltage VDD, while the cell programmed with logic '0' has a resistance of the eFuse device. Since it is about 50 ~ 100Ω, discharge the bit line BL to 0V.

When the data of the EFuse OTP memory cell is sufficiently transferred to the bit line BL and the bit line sense amplifier enable signal SAENb is activated to 0 V, the digital line sensing bit line sense amplifier circuit 280 is activated. Senses the voltage of the bit line BL and outputs the read data to the output port DOUT.

The eighth PMOS transistor 73, which is a PMOS load transistor having a high impedance, is turned on while the read word line RWL is selected to pull up the bit line BL to the logic voltage VDD. It acts as a load. Therefore, when reading the data of '1', the voltage of the bit line BL precharged to the logic voltage VDD is not discharged by the e-fuse device having a high resistance of 100 kΩ or more in the selected cell.

8A is a diagram illustrating a simulation result of a cell programmed as '0' in a read mode of an asynchronous EFuse OTP memory device according to an embodiment of the present invention, and FIG. 8B is an asynchronous eFuse according to an embodiment of the present invention. A diagram showing a simulation result of a cell programmed as '1' in the read mode of the OTP memory device.

As shown in FIGS. 8A and 8B, when the read signal READ is input, the bit line BL is precharged to the logic voltage VDD by the precharge signal PRECHARGE. After the bit line BL is precharged, the read word line RWL is activated and data of the cell is transferred to the bit line BL. When the data of the cell is sufficiently transmitted to the bit line BL, the digital data of the bit line BL is sensed by the bit line detection amplifier circuit 280 by the bit line detection amplifier circuit enable signal SAENb to output an output port ( DOUT).

On the other hand, SPICE simulation results show that the operating currents in the read mode of the E-Fuse OTP memory device according to the present invention are 349.5 ㎂ and 3.3 에서 at 1.98 V VDD and 3.6 V VIO, respectively.

9 is a layout diagram of an asynchronous e-fus OTP memory device according to an embodiment of the present invention.

Referring to FIG. 9, it can be seen that the layout area of the asynchronous E-Fuse OTP memory device according to an embodiment of the present invention is 300 μm × 557 μm.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a circuit diagram showing a conventional e-fuse OTP cell.

2 is a block diagram illustrating an asynchronous e-fus OTP memory device according to the present invention.

3A is a circuit diagram illustrating an asynchronous eFuse OTP memory cell in accordance with the present invention.

Figure 3b is a photograph showing the layout of the asynchronous e-fuse OTP memory cell according to the present invention.

3C is a circuit diagram illustrating an asynchronous EFuse OTP memory cell array in accordance with the present invention.

4A is a timing diagram in the program mode of an asynchronous eFuse OTP memory device in accordance with the present invention.

4B is a timing diagram in a read mode of an asynchronous eFuse OTP memory device in accordance with the present invention.

FIG. 5 is a diagram illustrating a word line driver circuit of the asynchronous EFuse OTP memory device of FIG. 2.

FIG. 6 is a diagram illustrating a source line driving circuit of the asynchronous EFuse OTP memory device of FIG. 2.

FIG. 7 is a diagram illustrating a bit line sense amplifying circuit of the asynchronous EFuse OTP memory device of FIG. 2.

8A and 8B illustrate simulation results in a read mode of an asynchronous E-Fuse OTP memory device according to an embodiment of the present invention.

9 is a photograph showing a layout of an asynchronous e-fus OTP memory device according to an embodiment of the present invention.

Claims (7)

delete delete delete In the e-fuse OTP memory device, An eFuse OTP memory cell array 210 in which at least two asynchronous eFuse OTP memory cells are respectively coupled to at least two source lines, at least two bitlines, at least two program wordlines, and at least two read wordlines ; A controller 220 for generating mode control signals instructing an operation of a program mode or a read mode of the eFuse OTP memory device; A power switch circuit 230 for supplying a logic voltage VDD or an interface voltage VIO to the eFuse OTP memory cell array in response to the mode control signal; A row decoder 240 for decoding a row address signal; A word line driver circuit 250 for driving the at least two program word lines and at least two read word lines in response to the mode control signal and the decoded row address signal; A column decoder 260 for decoding a column address signal; A source line driver circuit 270 for driving the corresponding source line in response to the mode control signal and the data input signal; And And a bit line sense amplification circuit 280 for sensing and amplifying the bit line in response to the mode control signal. The eFuse OTP memory cell, A first NMOS transistor having a first terminal connected to a ground voltage and a program word line WWL connected to a gate thereof; A second NMOS transistor having a first terminal connected to a bit line, a second terminal connected to a second terminal of the first NMOS transistor, and a read word line RWL connected to a gate thereof; And And an e-fuse device having a first terminal connected to a source line and a second terminal connected to a second terminal of the first NMOS transistor and a second terminal of the second NMOS transistor in common. Asynchronous eFuse OTP memory device. The word line driver circuit 250 of claim 4, wherein A first NAND gate 21 for inputting a row address signal; A first transfer gate 22 transferring an output of the first NAND gate in response to a word line enable program signal WLEN_PGM and an inverted word line enable program signal WLENb_PGM; A first PMOS transistor (23) having a logic voltage (VDD) coupled to its source, the word line enable program signal (WLEN_PGM) coupled to its gate, and an output of the first transfer gate coupled to its drain; A second inverter 24 for inputting an output of the first transfer gate; A third NMOS transistor 25 having a ground voltage VSS connected to a source thereof and an output of the first transfer gate connected to the gate thereof; A fourth NMOS transistor 26 having a ground voltage VSS connected to a source thereof and an output of the second inverter connected to a gate thereof; A second PMOS transistor having an interface voltage VIO connected to its source, a drain of the fourth NMOS transistor 26 connected to its gate, and a drain of the third NMOS transistor 25 connected to the drain thereof (27); A third having the interface voltage VIO connected to its source, a drain of the third NMOS transistor 25 connected to its gate, and a drain of the fourth NMOS transistor 26 connected to its drain PMOS transistor 28; A third inverter 29 driven by the interface voltage VIO and having a drain of the third NMOS transistor 25 connected to its input terminal and the inverted program word line WWLb connected to its output terminal; ; And And a first NOR gate 30 configured to receive the word line enable read signal WLENb_RD inverted from the output of the first NAND gate 21 and receive a read word line RWL connected to an output terminal thereof. Asynchronous eFuse OTP memory device. The method of claim 4, wherein the source line driving circuit 270, A second NAND gate 50 for receiving the column address signal WY and the data input signal WD decoded by the column decoder; A fourth inverter 51 receiving an internal program signal IPGM generated by the controller; A fifth inverter 52 receiving an output of the fourth inverter; A second transmission gate 53 which transfers the output of the second NAND gate in response to the internal program signal IPGM and the inverted internal program signal IPGMb; A fourth PMOS transistor 54 having a logic voltage VDD connected to a first terminal, an output of the second transfer gate connected to a second terminal, and an internal program signal IPGM applied to the gate; A sixth inverter (59) for inputting an output of the second transfer gate; A fifth NMOS transistor 55 having a ground voltage VSS connected to the source thereof and an output of the second transfer gate connected to the gate thereof; A sixth NMOS transistor 56 having a ground voltage VSS connected to a source thereof and an output of the sixth inverter connected to a gate thereof; A fifth PMOS transistor (57) having the interface voltage (VIO) connected to its source, a drain of the sixth NMOS transistor connected to its gate, and a drain of the fifth NMOS transistor connected to the drain thereof; A sixth PMOS transistor 58 having the interface voltage VIO connected to its source, a drain of the fifth NMOS transistor connected to its gate, and a drain of the sixth NMOS transistor connected to the drain thereof; And A seventh inverter (60) driven by the interface voltage (VIO) and having a drain of the fifth NMOS transistor connected to its input terminal; And And an eighth inverter (61) for inverting the output of the seventh inverter. The circuit of claim 4, wherein the bit line detection amplifier circuit comprises: A ninth inverter 71 for inputting a precharge signal PRECHARGE; A seventh PMOS transistor (72) having the logic voltage (VDD) connected to a source thereof, an output of the ninth inverter connected to a gate thereof, and the bit line (BL) connected to a drain thereof; An eighth PMOS transistor 73 having the logic voltage VDD connected to its source, a bit BL connected to its drain, and an inverted bit line load signal BL_LOADb connected to its gate; A tenth inverter 74 for inputting the inverted sensing enable signal SAENb; A ninth PMOS transistor (75) having the logic voltage (VDD) connected to its source and the bit line (BL) connected to its gate; A tenth PMOS transistor 76 having a drain of the ninth PMOS transistor connected to a source thereof and an inverted sensing enable signal SAENb connected to a gate thereof; A seventh NMOS transistor (77) having a drain of the tenth PMOS transistor 76 connected to the drain thereof, and an output of the tenth inverter connected to the gate thereof; An eighth NMOS transistor 78 having a source of the seventh NMOS transistor connected to a drain thereof, a ground voltage VSS connected to the source thereof, and the bit line BL connected to a gate thereof; And And a latch (79) for latching the drain of the seventh NMOS transistor and outputting the drain port to an output port of a bit line sense amplifying circuit.

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