KR20130056544A - One-time programable memory of electrical fuse type - Google Patents

Abstract

PURPOSE: An electrical fuse type OTP(One-Time Programmable) memory is provided to prevent a substrate biased with an electrical fuse link with VSS from being shorted in a programming operation by arranging an N-well floated under the electrical fuse link. CONSTITUTION: An electrical fuse type OTP memory includes an N-well and a word line driving circuit. The N-well is floated under an electrical fuse link. The word line driving circuit selectively activates a write word line(WWL) signal and a read word line(RWL) signal when a row decoded WERP signal is directly inputted to the electrical fuse type OTP memory. The electrical fuse type OTP memory precharges a bit line with a ground voltage in a standby mode.

Description

One-Time Programmable Memory of Electrical Fuse Type

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to OTP (One-Time Programmable) memory using an eFuse (eFuse, electrical Fuse) method, and more particularly to implement an eFuse OTP memory that operates at a high speed such as 32 bits. The present invention relates to an e-fuse type OTP memory having a new structure that can realize various functions without shorting the substrate biased by the e-fuse link and the VSS during programming, and realize a low area.

OTIF memory refers to a memory that allows only one program operation and no more writes, and which allows only read operations. The number of readings can be any number of times.

There are many kinds of orthopy memory. EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash (Flash) memory that stores binary information in a floating gate memory cell can be used as orthopy memory if only the program function is deleted, and EPROM (Electrically Programmable ROM) Can be used as an orthopedic memory.

However, the most common type of OT memory is the fuse type. The fuse method refers to a method of determining binary information according to whether a fuse is blown or not. In addition, PMIC (Power Management IC) incorporates non-volatile memory. In this case, there is an inconvenience that a separate manufacturing process is added when an EEPROM or a flash memory is incorporated. Therefore, a non-volatile memory built in a PMIC or the like is often used as an e-fife type e-fuse memory that does not require an additional process.

The e-fuse method is a method of arranging a fuse and then applying a high voltage to the fuse to program it by blowing the fuse. ", IEICE Trans. Electron., Vol. E93-C, no. 8, pp. 1365-1370, Aug. The technology is open to the public in 2010.

Polysilicon fuses are used for analog trimming (Donald G. Fink and Donald Christiansen, Electronics Engineers' Handbook, McGraw-Hill, Nov. 1996). EFuse OTP memory using polysilicon fuses programs overcurrent to eFuse (N. Robson et al., "Electrically Programmable Fuse eFuse: From Memory Redundancy to Autonomic Chips", Proceedings of Custom Integrated Circuits Conference, pp. 799-804, Sep. 2007). Efuse's pre-programmable resistance is around 50-200 mA, and with the program current flowing through the e-fuse, the e-fuse's resistance typically exceeds a few kΩ. As such, the e-fuse is programmed in one of a conductive state and a highly resistive state (Du-Kwi Kim, Ji-Hye Jang, Liyan Jin, Jae-Hyung Lee, Pan-Bong Ha, and Young-Hee Kim, Design and Measurement of a 1-KBit eFuse One-Time Programmable Memory IP Based on a BCD Process, The Institute of Electronics, Information, and Communication Engineers, vol.E93-C, no. 8, pp. 1365-1370, Aug. 2010). eFuse OTP is widely used in small capacity OTP memory applications and can be implemented in standard CMOS processes without any additional process.

Conventional dual-port eFuse OTP cells are memory cells that store one bit of binary information, typically as shown in Figure 1, eFuse, a read-out NMOS transistor (MN2) capable of passing read mode current, and large It consists of a programming NMOS transistor MN1 through which a program current can flow. The circuit driving the word line (WL) of the dual port eFuse OTP cell decodes the row address according to the operation mode, thereby reading the read word line (RWL) and the write word line. Selectively activates the (WWL) (Write Word-Line) signal.

Programming the eFuse applies a voltage of about 5 V through the select line SL and turning on the programming transistor MN1 causes a sudden current flow across the fuse which results in destruction of the current path . For example, a polysilicon layer having a width of about 0.18 micrometers is suitable for fuses of this purpose.

Note that the program operation is also used for various names such as fusing, blowing, writing, etc., but it is just another expression that means the same operation in OTP memory.

If the fuse is blown, a precharge voltage of 5 V is applied to the bit line BL, the ground (VSS) voltage of the selection line SL, and the gate of the read transistor MN2 (read word line RWL). When the voltage of 5 V is applied (hereinafter, referred to as 'read mode voltage condition'), the voltage of the bit line BL remains at 5 V, which is a precharged voltage.

If the fuse remains intact, the precharged voltage of the bit line is discharged through the fuse FS under the read mode voltage condition. Eventually, the sense amplifier connected to the bitline can read either the 'high' or 'low' voltage depending on the blown fuse.

Considerations for the 32-bit high-speed eFuse OTP memory design include the same structure as the existing 16-bit low-speed design, which allows the fuse to be thermally disrupted and p-substrate biased by e-fuse link and ground voltage (VSS). There is a possibility of this shorting.

If shorted, the eFuse cell programmed as 1 would read as 0, resulting in memory failure. In the conventional low-speed eFuse OTP memory, when a row decoded WERP (Word Line (WL) Enable for Read or Program) signal is input directly instead of a row address, the write word line WWL of FIG. There is a problem that there is no word line WL driving circuit for selectively activating the read word line RWL signal.

Furthermore, in the eFuse OTP memory of the conventional low speed design, the delay chain circuit occupies a large area because a delay is applied to the MOS capacitor, so that the total memory area is large and thus, cost reduction is difficult. there was.

The present invention is to solve the problems of the conventional method to implement an eFuse OTP memory operating at a high speed, such as 32-bit. Specifically, the present invention has a problem that the eFuse link and the VSS are short-circuited by placing a floating N-Well under the eFuse link to solve the problem that the eFuse link and the VSS biased substrate (p-substrate) may be shorted during programming. Its purpose is to solve it.

When the row decoded WERP signal is directly input to the eFuse OTP memory, the present invention selectively activates the write word line (WWL) and the read word line (RWL) signals, which are the word line (WL) signals of the dual port eFuse OTP cell. By devising a word line (WL) driving circuit, an eFuse OTP memory that can operate even when a row decoded WERP (word line WL Enable for Read or Program) signal is input directly to the eFuse OTP memory is input. Has a purpose.

In addition, when precharging the BL of the conventional eFuse OTP memory to VSS, the conventional method is to precharge the short pulse period while entering the read mode, but the present invention precharges the BL to the VSS in the standby mode. The purpose of the present invention is to reduce the layout area of the control circuit, and to eliminate the delay chain circuit used in the BL precharging signal.

This object is achieved by an e-fuse OTP memory provided according to the present invention.

In an e-fuse OTP memory provided according to an aspect of the present invention, an E-Fuse OTP (electric Fuse One-Time Programmable) memory includes an N-Well floating under an eFuse link.

In one embodiment, the eFuse OTP memory is a read word line (RWL) signal and a write word line (WLL) signal of a dual port eFuse OTP cell when a row decoded WERP signal is directly input to an eFuse OTP memory. The word line driver circuit may further include a word line driver circuit for selectively activating the word line signal.

In another embodiment, the eFuse OTP memory may precharge the BL to VSS in the standby mode.

According to the present invention having the above-described configuration, in an eFuse OTP memory, an eFuse link is provided by placing a floating N-Well under the eFuse link in order to prevent a short-circuit of the p-substrate biased by the eFuse link and the VSS during programming. And VSS provide the advantage of solving the short-circuit problem. When the row decoded WERP signal is directly input to the eFuse OTP memory, the present invention selectively activates a write word line (WWL) signal and a read word line (RWL) signal, which are word line (WL) signals of a dual port eFuse OTP cell. By designing a word line (WL) driving circuit, an eFuse OTP memory that is operable even when a row decoded WERP (word line (WL) enable for read or program) signal is input directly to the eFuse OTP memory, rather than a row address, can be implemented. It offers the advantage that it can. Furthermore, the present invention can be implemented by precharging the BL to VSS in the standby mode, thereby eliminating the delay chain circuit used in the BL precharging signal, thereby reducing the layout area of the control circuit. According to the present invention provides a significant effect, such as to implement an eFuse OTP memory operating at a high speed, such as 32bit.

1 is a circuit diagram of a typical dual port eFuse OTP cell.
2 is a timing diagram according to an operation mode, which shows (a) program mode, (b) normal read mode, and (c) test read mode.
3 is a block diagram of a typical 32-bit eFuse OTP memory.
4 is a layout of a dual port eFuse OTP memory cell in accordance with the present invention.
5 is a circuit diagram illustrating (a) a word line (WL) driving circuit and (b) an SL driving circuit according to the present invention.
6 is a circuit diagram illustrating a VSS BL precharging BL S / A circuit.
7 is a BL control timing diagram showing (a) the conventional scheme and (b) the scheme in accordance with the present invention.
8 is a layout of an eFuse OTP memory designed in accordance with the present invention.
9 is a graph showing the results of simulation of the program current according to the eFuse resistance in the program mode according to the present invention.
10 is a schematic diagram showing a simulation waveform in the normal read mode according to the present invention.
FIG. 11 is a diagram illustrating a waveform of measuring a function-specific output of a test chip of an eFuse OTP memory according to the present invention.
12 is a view showing a test result of an eFuse OTP memory on a wafer according to the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and is defined by the claims of the present invention.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

Hereinafter, with reference to the accompanying drawings illustrating the present invention with a specific example as follows.

The present invention provides a 32-bit eFuse OTP memory for PMIC that is reliable and prevents malfunction using the Magnachip 0.18 process, as described in detail below. Specifically, the present invention solves the problem of shorting the VSS of the eFuse link and the p-substrate during programming by placing the N-Well under the eFuse link. In the present invention, when a decoded WERP (WL) enable for read or program (WL) signal is directly input to an eFuse OTP memory, the present invention reads and writes a read word line (RWL) of a dual port eFuse OTP memory cell. A word line (WL) driving circuit for selectively activating a word line (WWL) is proposed. It also provides the benefits of eliminating the delay circuits in the BL precharging circuit, thereby reducing the layout area of the control circuit.

Key features of the 32-bit eFuse OTP memory designed using the Magnahip 0.18 GF-ACL process according to a specific embodiment of the present invention are shown in Table 1 below. The cell array consists of 32 rows and 1 column, and n + polysilicon eFuse was used. Operation mode includes program mode, normal read mode and test read mode. EFuse OTP memory performs program and read operation in bit unit. And the program time is 20s. The power supply voltage used is a single power supply of VDD. In VDD mode, 5.5V to 6V are used to supply enough program power to the eFuse when in program mode, and a low voltage of 1.8V is used to lower the read current through unprogrammed cells in read mode. . The devices used in the design were only 5V MOS transistors.

2 is a timing diagram according to an operation mode. In the program mode, as shown in (a) of FIG. 2, the timing diagram shows a high signal and a low signal of the access signal and the PE signal, respectively, with WERP [31: 0] decoded as the row selection signal. Activating 'will program the selected OTP memory cell. The access signal is 'active high' as a signal for reading or program access, and the PE is 'active low' as a program enable signal.

If the eFuse link is programmed slightly larger than the minimum senseable resistance, the resistance of the eFuse may fluctuate below the minimum senseable resistance during use, resulting in poor data sensing.

Therefore, the present invention applies a sensing margin test technique having a variable pull-up load. The test read mode allows the pull-up load of the BL-S / A (Bit-Line Sense Amplifier) circuit to have a higher impedance than the normal read mode, so that only the programmed resistance of the eFuse is passed during the wafer test. 2 (b) and 2 (c) show timing diagrams for the normal read and test read modes, respectively, and the bit data of the selected cell is output to the OUTPUT port after the access time has passed. In normal read mode, T1 is active, while in test read mode, T2 is active.

A 32-bit eFuse OTP memory, provided in accordance with one embodiment of the present invention, has an eFuse OTP memory cell array of 32 rows and 1 columns, a word line (WL) driving circuit, a source line (SL) as shown in FIG. 3 as a block diagram. It may be composed of a driving circuit, BL S / A, and control logic. The control logic supplies the internal control signal suitable for program and read mode according to the control signals (Access, PE, T1, T2). The BL S / A circuit senses the digital data coming out of the BL and outputs it to the OUTPUT port depending on whether or not the eTP is programmed in the OTP cell in read mode.

The 32-bit eFuse OTP memory uses the dual port eFuse OTP cell circuit of FIG. 1, and the cell layout image is shown in FIG. 4. In order to solve the problem of short-circuit of the p-substrate biased by the eFuse link and the VSS during programming, a floating N-Well is placed below the eFuse link as shown in FIG. 4. The layout sizes of the designed eFuse OTP memory cells are 38.03 μm and 4.56 μm.

Table 2 below shows bias voltages at the eFuse OTP memory cell nodes for each operation mode. In the program mode, the write word line WWL of the selected cell is activated with VDD. Since the write word line WWL of the unselected cell maintains 0 V, the eFuse link of the OTP cell is isolated from the BL.

In order to program the eFuse OTP cell in the program mode, a VDD voltage is applied to the SL and the write word line WWL of FIG. 1, and a program current flows through the eFuse and MN1. This will program the eFuse, and the resistance of the eFuse will be more than a few tens of k. In the read mode, only the read word line RWL of the selected cell is activated to the VDD voltage while the BL is precharged to the VSS voltage. If the cell has not been programmed with eFuse, BL is maintained at low voltage of 0V through MN2 and eFuse link of FIG. 1, and logic '0' is outputted to DOUT. In the programmed cell, the eFuse is in a high resistance state, and the BL voltage is pulled up to a high voltage VDD by a pull-up load, so the logic is outputted to the OUTPUT.

FIG. 5A illustrates a write word line (WWL) signal and a read word line (RWL) signal, which are word line (WL) signals of a dual port eFuse OTP cell, when a row decoded WERP signal is directly input to an eFuse OTP memory. The word line (WL) driving circuit is selectively shown. When the program mode is entered, the word lines WL EN_RD and PGM_EN become logic '1' and logic '0', respectively. The word line WL driving circuit selected by the WERP signal has a write word line WWL of VDD, The read word line (RWL) is designed to drive 0V. The SL driving circuit of FIG. 5B supplies the VDD voltage to the anode of the eFuse in the program mode, and the SL drives 0V because the PGM_EN signal is in a logic '0' state in the read mode.

The BL S / A circuit used in the 32-bit eFuse OTP memory design of the present invention is shown in FIG. 6, and the precharging transistor (MN0) for precharging the BL to VSS by the BL_PCG signal, and the pull-up of the BL to VDD It consists of pull-up load transistors (MP0 and MP1) and negative level sensitive D-latch. The BL S / A circuit precharges the BL to VSS before the read word line (RWL) is activated. Thus, only when the programmed eFuse cell is accessed, the BL is pulled up to VDD, and when not programmed, the BL maintains the precharging level VSS. On the other hand, if the data from the eFuse OTP memory cell is sufficiently transmitted to the BL and the SAENb (Sense Amplifier Enable bar) signal is activated to 0 V, the negative-level sensitive D-latch senses the BL voltage VDD or 0V and outputs it to the OUTPUT port. .

7 (a) and 7 (b) show BL control timing diagrams of the conventional scheme and the proposed scheme according to the present invention, respectively. In the conventional BL control timing diagram, the BL_PCG signal generates a short pulse of high as the RD (Internal Read) signal is activated high, so that the BL is precharged to VSS, whereas the timing diagram of FIG. Precharges BL to VSS as the RD signal enters standby mode. By using the control timing diagram of FIG. 7B, the delay chain circuit of BL_PCG is eliminated, thereby reducing the area occupied by the control logic.

Sensing margin test technique having a variable pull-up load according to the present invention (see Jeong-Ho Kim, Du-Hwi Kim, Liyan Jin, Pan-Bong Ha, and Young-Hee Kim, Design) of 1-Kb eFuse OTP Memory IP with Reliability Considered, Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 88-94. June 2011) using the test read mode of FIG. Designed. The test read mode tests the pull-up load of the BL-S / A (Bit-Line Sense Amplifier) circuit to turn on the high impedance MP1 to test for normal programming than the normal read mode. In normal read mode, on the other hand, the small pull-up resistor turns on MP0 to sense BL as normal 1 data even if the programmed eFuse resistance fluctuates low. Changing the programmed eFuse resistance high does not matter as the sensing margin increases. Therefore, only the case where the programmed resistance is lowered is considered in the design.

8 shows a layout image of a 32-bit eFuse OTP memory designed using a 0.18 GF-ACL process. The layout area is 38.12 μm × 52.745 μm.

According to the present invention, the power line routing resistance of the 32-bit eFuse OTP memory IP designed using the Magnachip 0.18 GF-ACL process and the routing resistance 10 when the IP is used at the chip level are modeled to provide the program current in the program mode. The program current was simulated. As shown in FIG. 9, the program current according to the eFuse resistance is 32.1mA at a VDD voltage of 5.5V and room temperature.

10 shows a simulation waveform in the normal read mode. When the read command comes in, as shown in FIG. 6, the BL_PCG signal for precharging the BL to VSS becomes low and turns off the BL precharging transistor MN0. After the BL precharging transistor is turned off, the read word line RWL is activated and data of the cell is transferred to the BL. When data of cell is sufficiently transmitted to BL, data of BL is sensed by SAENb signal and output to OUTPUT port. Upon entering standby mode, BL_PCG is activated to precharge BL to VSS. Thus, when designing a BL_PCG circuit, the delay chain circuit for generating a short pulse can be eliminated.

 Since the BL S / A circuit using the variable pull-up load of FIG. 6 is used, the senseable resistors are simulated at 31kΩ and 20kΩ, respectively, in test read mode and normal read mode. In this case, sensing is possible as long as the eFuse resistance does not drop below 11kΩ in the field.

Figure 11 shows the function-specific OUTPUT measurement waveform for the test chip of the eFuse OTP IP. You can see that the OUTPUT of the programmed cell is normally read. As a result of measuring 94 dies using the Advantest apparatus, as shown in the wafer map of FIG. 12, it was confirmed that the function operates normally 100%.

Above, the layout area of the designed eFuse OTP memory is 38.81 μm × 252.745 μm. By measuring 94 dies fabricated using a memory tester, the OTP memory yield was 100% at a program voltage of 5.5V.

As described above, according to the present invention, a 32-bit eFuse OTP memory may be implemented using a Magna chip semiconductor 0.18 CMOS process. This memory solves the problem of shorting the eFuse link and VSS by placing a floating N-Well under the eFuse link to solve the problem of shorting the p-substrate biased by the eFuse link and VSS during programming. When the row decoded WERP signal is directly input to the eFuse OTP memory, a word line for selectively activating the write word line (WWL) and the read word line (RWL) signals of the word line (WL) signal of the dual port eFuse OTP cell ( WL) drive circuit. In addition, the conventional method of precharging the BL of the eFuse OTP memory to VSS was a method of precharging for a short pulse period while entering the read mode, but the present invention has been changed to a method of precharging the BL to VSS in the standby mode. . This eliminates the delay concatenation circuit used in the BL precharging signal, thereby reducing the layout area of the control circuit.

SL: Selection Line
BL: bit line
MN1: Programmable transistor
MN2: Read transistor
eFuse: This fuse

Claims (3)

In the One-Time Programmable (OTP) memory of the eFuse (eFuse),
E-fuse type OTP memory, characterized in that it has an N-Well (floating) beneath the e-fuse link. The method of claim 1, wherein the e-fuse OTP memory,
When a row decoded WERP signal is directly input to the e-fuse OTP memory, a write word line (WWL) signal and a read word line (RWL) signal, which is a word line (WL) signal of a dual port eFuse OTP cell, is selectively selected. E-fuse type OTP memory further comprises a word line driving circuit for activating. The method of claim 1, wherein the e-fuse OTP memory,
An e-fuse type OTP memory, wherein the bit line BL is precharged to the ground voltage VSS in the standby mode.

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