KR101762920B1 - One-time programmable memory apparatus - Google Patents
One-time programmable memory apparatus Download PDFInfo
- Publication number
- KR101762920B1 KR101762920B1 KR1020150191201A KR20150191201A KR101762920B1 KR 101762920 B1 KR101762920 B1 KR 101762920B1 KR 1020150191201 A KR1020150191201 A KR 1020150191201A KR 20150191201 A KR20150191201 A KR 20150191201A KR 101762920 B1 KR101762920 B1 KR 101762920B1
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- terminal
- bit line
- reference voltage
- terminal connected
- signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- Power Engineering (AREA)
- Read Only Memory (AREA)
Abstract
The present invention relates to a technology for reducing the layout area by using one reference voltage generation circuit for the fuse-type memory device instead of using a reference voltage generation circuit for each bit line sense amplifier.
To this end, according to the present invention, in an orthopedic memory device, a voltage of a bit line on an api-cell array is compared with a reference voltage to sense bit line data, and whether data is normally programmed in the api cell array The reference voltage generating circuit for comparing the program data stored in the data driving and latch unit with the data read from the at least one OFT cell array in order to confirm the reference voltage, And a sense amplifier and a comparator which use only one of them for the column.
Description
The present invention relates to a technology for implementing a low-area orthotropic memory device, and more particularly to a technique of using a single reference voltage generating circuit in a fuse-type memory device instead of using a reference voltage generating circuit for each bit- And more particularly to an orthopedic memory device capable of reducing the area.
One-Time Programmable (OTP) memory refers to a memory that can not be written any more by a single program operation and allows only read operations. The number of leads can be any number of times. There are various kinds of OTP memory. EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash (Flash) memory that stores binary information in a floating gate memory cell can be used as orthopy memory if only the program function is deleted, and EPROM (Electrically Programmable ROM) Can be used as an orthopedic memory. However, the most commonly used orthopy memory is the fuse type. The fuse method refers to a method of determining binary information according to whether a fuse is blown or not.
PMIC (Power Management IC) is a chip applied to information devices such as mobile phones, notebook computers, TVs and monitors. It converts power supplied from outside into stable and efficient power required by the system. The PMIC uses a small amount of efuse (electrical fuse) -optimized memory capable of logic-based design that does not require an additional process to perform analog trimming, to be.
A dual port eFuse OTP cell is used as an OTFT cell array of this fuse type memory intellectual property (hereinafter referred to as "e-fuse OTFT memory").
However, since one reference voltage generating circuit is used for each column in the sensing circuit of the conventional orthophilic memory device, the layout size of the fuse orthopedic memory is increased and the read current is increased .
SUMMARY OF THE INVENTION A problem to be solved by the present invention is to provide a dual-port fuse-type cell in which a relatively small-sized dual-port fuse-type cell is used in an OTFT cell array and only one reference voltage generation circuit is used in the fuse- Thereby reducing the layout area.
According to an aspect of the present invention, there is provided an OTFT device including: an OTFT cell array including a plurality of OFT cells arranged in a bipolar fashion; A control logic unit for outputting an internal control signal corresponding to the operation mode according to a read signal, a program signal, and a test mode enable signal; A row driver for receiving a row address and driving a selected row on the atopy cell array under the control of the control logic unit; A data driving and latch unit which decodes a column address to selectively drive a desired one of all columns on the atopy cell array and latches program data; And a control circuit for sensing data of a bit line by sensing a voltage of a bit line on the atopy cell array in a manner of comparing the voltage of the bit line on the atopy cell array with a reference voltage, A reference voltage generating circuit for comparing the program data stored in the driving and latching unit with the data read from the at least one atopy cell array at the present time, the reference voltage generating circuit being used for a plurality of columns on the atopy array, And a comparator.
The present invention uses a relatively small-sized dual-port fuse-optic cell in an opportunistic cell array of an orthopy-memory device and uses only one reference voltage generation circuit in the fuse-orophytic memory device, So that the layout area of the orthophilic memory device can be reduced.
Also, by implementing analog sensing, there is an effect that the sensing resistance can be reduced to a low value in the PV mode and the read mode.
1 is a block diagram of an orthopy memory device according to an embodiment of the present invention.
FIG. 2A is a circuit diagram of a dual-ported fuse-type cell array arranged in an octipole cell array.
2B is a circuit diagram of a differential pair of fuse-optic cells arranged in an orthogonal cell array.
3A is a layout image of a dual port fuse-type cell.
3B shows a layout image of a fuse-optic cell in a differential pair.
Fig. 4 is a diagram showing that the dual port fuse-optic cells are arranged in 4 rows x 8 columns.
5 is a circuit diagram showing an embodiment of a sense amplifier and a comparator.
6 is a detailed view of the reference voltage generating circuit.
7 is a layout image of the orthophilic memory device.
8A and 8B are waveform diagrams showing simulation results for an orthophilic memory device.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a block diagram of an orthophilic memory device according to an embodiment of the present invention. As shown in FIG. 1, the
In the
The
The
The data driving and
The sense amplifier and the
FIG. 2A is a circuit diagram of a dual port fuse-tap cell arranged in the
The circuit for driving the word line (Word-Line) of the atypical cell decodes the row address according to the operation mode and selectively outputs the read word line signal (RWL) and the write word line signal (WWL) Activate.
In the program mode for the eFuse, a voltage of 5 V or 0 V is supplied through the source line SL according to the data to be programmed, and the programming transistor MN1 is turned on. Accordingly, when a voltage of 5V is supplied through the source line SL, a sudden current flows to both ends of the fuse eFuse so that the eFuse is cut off. However, when a voltage of 0V is supplied, (eFuse) does not flow at both ends of the eFuse, so the eFuse maintains its original connected state.
When the eFuse is blown in the program mode, a precharge voltage of 5 V is supplied to the bit line BL in the read mode, and a precharge voltage of 5 V is applied to the gate of the read transistor MN2 ), The voltage of the bit line BL stays at 5V, which is the precharged voltage.
However, if the eFuse is kept connected in the program mode, the voltage precharged to the bit line BL in the read mode is applied to the lead transistor MN2, the eFuse and the source line SL ≪ / RTI >
Therefore, the sense amplifier connected to the bit line BL can read the high or low voltage according to the break or continuity of the eFuse. That is, in the read mode, the write word line WWL is driven by the ground voltage VSS and the read word line RWL is driven by the power supply voltage VDD. Thus, when the output data DOUT of the sense amplifier is "1" and "0" is programmed to the notch cell when "1" is programmed to the notch cell, Quot; 0 ".
FIG. 2B is a circuit diagram of a differential paired fuse-off cell, in which the dual port of FIG. 2A has a structure in which a dual-port fuse-type cell is connected in a pair as compared with a circuit of a fuse- to be. The fuse apity cell of the differential pair can receive a reference voltage through a simple peripheral circuit without requiring a reference voltage generating circuit.
FIG. 3A shows a layout image of the dual port fuse-optic cell. The cell size is 20.555 占 퐉 占 5.09 占 퐉 (= 104.625 占 퐉 2 ). 3B shows a layout image of the fuse-optic cell in which the differential pair has a cell size of 17.02 mu m x 11.26 mu m (= 191.6452 mu m 2 ), and the dual port is twice the size of the fuse-optic cell.
In view of this, it is preferable that the dual port type fuse type cell as shown in FIG. 2A uses the fuse type cell.
The main features of the
FIG. 4 exemplarily illustrates that the dual-port fuse-type cells as shown in FIG. 2A are arranged in 4 rows by 8 columns (32 bits) in the
The
When the data driving and
It is necessary to test whether the data is normally programmed in the
5 is a circuit diagram showing an embodiment of the sense amplifier and the
The bit
The
The
6 is a detailed circuit diagram showing an embodiment of the reference
The operation of the sense amplifier and the
In the stand-by state, the bit line precharge signal BL_PCG is held at 0V, and the bit line load bar signal BL_LOADb is maintained at the level of the power supply voltage VDD. In this state, the line to which the reference voltage VREF is supplied and the bit line BL are in a floating state, and the first node N1 and the second node N2 are connected to the sense amplifier enable signal SAEN And is precharged to the power supply voltage VDD supplied through the PMOS transistors MP54 and MP55, which are turned on each other.
The NMOS transistor MN51 of the bit
Then, the NMOS transistor MN2, which is a read transistor, is turned on by the read word line signal RWL.
Thereafter, when the bit line load bar signal BL_LOADb is activated to a low level at the power supply voltage VDD, the reference voltage VREF in the normal read mode is reduced to the level of the resistor R53, Is set according to the ratio of the resistance value of the resistor R52 connected in series with one resistor selected by any one of the NMOS transistors MN57 and MN58 in the resistor R54. The values of the resistors R52 to R54 are not particularly limited, but the values of the resistors R52 and R53 are 1.5 k ?, and the value of the resistor R54 is 3 k? .
Since the resistance value of the eFuse link varies depending on the presence or absence of the programming of the selected OTFT cell on the
When the data of the atopy cell is sufficiently transferred to the bit line BL, the sense amplifier enable signal SAEN is activated to "high ". Accordingly, the
At this time, the
On the other hand, in consideration of the case where the resistance value of the eFuse link programmed during the data retention time is reduced, the PMOS transistor MN58 is turned to the Tm control signal PVDD_TM in the PVR (Program-Verify-Read) Is turned on so that the reference voltage VREF is set by the resistors R52 and R54 connected in series. In the read mode, considering that the resistance value of the eFuse link programmed during the retention time is reduced, the NMOS transistor MN57 is turned on with the normal control signal PVDD_NORMAL, and the resistance R52, (VREF) is set. By doing so, even if the resistance value of the programmed e-fuse fluctuates to some extent, normal data can be sensed.
FIG. 7 shows a layout image of an orthopedic memory device (32-bit eFuse OTP memory) 100 according to an embodiment of the present invention, which is designed using a Magnachip 0.18 mu m GF-ACL process. As a result of the simulation, the layout area of the
8A and 8B are waveform diagrams showing simulation results of the
Table 2 below shows simulation results for the read current when a bit line sense amplifier according to the prior art is used and Table 3 shows the results of the
Table 4 below shows simulation results of a program-verify-read (PVR) mode for an
Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.
100: OTFT memory device 110: OTFT cell array
120: control logic section 130: low driver
140: Data driving and latching unit 150: Sense amplifier and comparator
151: bit line control unit 152: sense amplifier
153: RS latch 154: output buffer
Claims (6)
A control logic unit for outputting an internal control signal corresponding to the operation mode according to a read signal, a program signal, and a test mode enable signal;
A row driver for receiving a row address and driving a selected row on the atopy cell array under the control of the control logic unit;
A data driving and latch unit which decodes a column address to selectively drive a desired one of all columns on the atopy cell array and latches program data; And
The data of the bit line is read by sensing the voltage of the bit line on the atopy cell array in comparison with the reference voltage, And comparing whether the program data stored in the latch unit and the data currently read in the atopy cell array coincide with each other,
And a sense amplifier and a comparator that use only one reference voltage generating circuit for generating the reference voltage for a plurality of columns on the atopy array.
A transistor having one terminal connected to the bit line and a read word line signal supplied to a gate;
A program transistor in which one terminal is connected to the other terminal of the read transistor, the other terminal is connected to the ground terminal, and a write word line signal is supplied to the gate; And
A dual port having an e-fuse having one terminal connected to a common connection point of the other terminal of the read transistor and one terminal of the programming transistor and the other terminal connected to a source line on the atopy cell array, And a memory for storing the data.
A sense amplifier unit for sensing the voltage of the bit line by comparing the reference voltage with the reference voltage and outputting the voltage to the first node and the second node;
A fourth PMOS transistor which is turned on by a sense amplifier enable signal in a standby mode and precharges the first node to a power supply voltage; And
And a fifth PMOS transistor that is turned on by the sense amplifier enable signal in the standby mode and precharges the second node to the power supply voltage.
And an RS latch having a first input terminal connected to the first node and a second input terminal connected to the second node.
A first PMOS transistor having one terminal connected to a power supply voltage and a gate supplied with a bit line load bar signal;
A first resistor having one terminal connected to the other terminal of the first PMOS transistor and the other terminal connected to the bit line; And
And a bit line control unit having an NMOS first NMOS transistor having one terminal connected to the bit line and the other terminal connected to a ground terminal and a gate supplied with a bit line precharge signal. Device.
A sixth PMOS transistor having one terminal connected to the power supply voltage and a gate supplied with a bit line load bar signal;
A second resistor having one terminal connected to the other terminal of the sixth PMOS transistor and the other terminal connected to the output terminal of the reference voltage;
A seventh NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a normal control signal;
An eighth NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a Tm control signal;
A third resistor and a fourth resistor each having one terminal connected to the other terminal of the seventh NMOS transistor and the eighth NMOS transistor and the other terminal connected to each other;
An inverter for inverting and outputting the bit line load bar signal;
A ninth NMOS transistor having one terminal commonly connected to the other terminal of the third resistor and the fourth resistor, the other terminal connected to the ground terminal, and a gate connected to the output terminal of the inverter; And
And a tenth NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a bit line precharge signal.
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