KR20140110579A

KR20140110579A - eFuse OTP Memory device

Info

Publication number: KR20140110579A
Application number: KR1020130025173A
Authority: KR
Inventors: 김영희
Original assignee: 창원대학교 산학협력단
Priority date: 2013-03-08
Filing date: 2013-03-08
Publication date: 2014-09-17

Abstract

The present invention relates to an eFuse OTP memory device. To this end, the present invention comprises a control logic unit for supplying a control signal for a read mode, a program mode and a program-verify-read mode, A data latch unit for storing program data in a column selected by the program column selecting unit, and a plurality of differential pair eFuse cells (eFuse cells) for performing an operation of programming an eFuse or reading data, a data output buffer unit for reading and storing data from the OTP cell array; and a control unit for, when the program verify read mode is performed, storing program data stored in the data latch unit and read data of the data output buffer unit A comparator for comparing the comparison result of the comparator, - it includes a bar (PFb) Pin-fail. In addition, a variable pull-up load circuit for sensing margin test is configured to vary the impedance of the program verify lead mode and the pull-up load of the bit line pre-charge circuit used in the lead mode. According to the present invention, it is possible to know the program state of the eFuse OTP in the package state and to prevent the occurrence of sensing failure even if the programmed eFuse link resistance is reduced.

Description

This fuse OTP memory device {eFuse OTP Memory device}

[0001] The present invention relates to an OTP memory, and more particularly, it relates to an OTP memory that tests whether an eFuse OTP memory is normally programmed in a package state, - an eFuse OTP memory device having an eFuse OTP memory cell designed to perform a sensing margin test using an up-load.

Power ICs, such as Power Management ICs (PMICs), typically require a small amount of nonvolatile memory to perform analog trimming functions. However, as nonvolatile memory, memories such as EEPROM and Flash memory require additional processes that result in long process, low reliability, and high manufacturing cost.

Therefore, eFuse electrical fuse one-time programmable (OTP) memory, which does not require additional processing, is often used.

The eFuse OTP memory is programmed by flowing an overcurrent to the eFuse. The program transfer resistance is about 50 to 100 Ω. As the program current flows through the eFuse, the eFuse resistance after the program becomes more than several tens of kΩ. This eFuse OTP memory programs 1-bit data into either a conductive state or a high resistive state.

On the other hand, the eFuse OTP memory device should be primarily considered to satisfy the following two design conditions.

One of the first conditions is that the eFuse OTP memory should be able to be tested in the finished eFuse OTP memory device that the package has been successfully programmed to.

That is, it is possible to test whether or not the eFuse OTP memory is programmed in the assembling step of the state before the package. In this case, since the influence of peripheral devices and the like is not reflected, characteristics before and after the package may be different. It is therefore necessary to check the eFuse OTP memory status in the package state.

However, in this case, when the eFuse OTP memory device is packaged, the number of pins of the PMIC chip used therein becomes a problem. That is, since the PMIC chip has a few number of pins to be used, there arises a problem that data of 8-bit or more can not be read in the package state.

The next second condition is that the eFuse OTP memory should not cause a faulty sensing even if the resistance of the programmed eFuse link is reduced during the data retention time. For example, when the eFuse link is programmed in the vicinity of the minimum resistance that can be sensed, the resistance of the eFuse programmed during actual use may fluctuate below the minimum resistance that can be sensed, which may result in the inability to sense data.

As is well known, the eFuse OTP memory is widely applied to a small capacity OTP memory application, and has various advantages that can be realized by a standard CMOS process. However, as described above, some required design conditions are required. If it is designed without considering the required design conditions, the process and equipment should be added to test whether the eFuse OTP memory is programmed normally. In addition, the possibility of bad data sensing can not be overestimated.

This causes degradation of performance of the eFuse OTP memory and various devices using the same.

Korean Patent Publication No. 10-2010-0099845 US Published Patent US 2009-0251943

SUMMARY OF THE INVENTION An object of the present invention is to provide an eFuse OTP memory device capable of testing whether an eFuse OTP memory is normally programmed in a package state.

It is another object of the present invention to provide a eFuse memory device that enables data sensing by enabling a margin test for resistance variation of a programmed eFuse link during a data retention time.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a control logic unit for supplying a control signal for a read mode, a program mode, and a program-verify-read mode; A program column selecting unit for selecting a column to be programmed in the program mode; A data latch unit for storing program data in a column selected by the program column selecting unit; an OTP cell array composed of a plurality of differential pair eFuse cells for performing an operation of programming an eFuse or reading data; A data output buffer unit for reading and storing data from the OTP cell array; A comparing unit comparing the program data stored in the data latch unit and the read data of the data output buffer unit when the program verify read mode is performed; And a pass-fail-bar (PFb) pin outputting a comparison result of the comparison unit.

The differential pair eFuse cell includes: a first data storage unit for storing program data; And a second data storage unit having a structure symmetrical with the first data storage unit to store complementary program data.

The first data storage unit includes a first NMOS transistor MN1 and a second NMOS transistor MN2 connected in series and a second NMOS transistor MN2 connected to the first NMOS transistor MN1 and the second NMOS transistor MN2. Wherein the second data storage unit includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4 connected in series and a third NMOS transistor MN4 and a fourth NMOS transistor MN4 connected in series, And a second eFuse (eFuse 2) configured on a line to which the NMOS transistor MN4 is connected, wherein the first eFuse and the second eFuse are connected to each other, and the connection node of the first eFuse and the second eFuse has the program Mode and a source line which is a switching power source for driving the OV in the read mode and the program verify read mode is connected.

The first NMOS transistor MN1 and the third NMOS transistor MN3 are program transistors and the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are connected to a lead for decreasing the current in the read mode. It is a special transistor.

When the program data of the differential pair eFuse cell is '1', the first eFuse is in a 'bolling' state, and when the program data of the differential pair eFuse cell is '0' (bolwing) state.

In the OTP cell array, the differential pair eFuse cell is composed of 1 row x 24 columns.

The variable pull-up load circuit further includes a bit line pre-charge circuit used in the program verify lead mode and the read mode, The load impedance of the pull-up load of the load circuit is varied.

And the variable pull-up load circuit utilizes the difference between the program verify lead mode and the eFuse resistor which can be sensed in the lead mode.

The variable pull-up load circuit comprises: a first pull-up load transistor (MP1) and a second pull-up load transistor (MP2) which are constituted by PMOS elements and whose gate ends are connected to each other and are supplied with a BL_LOADb signal; A third full-up load transistor (MP3) and a fourth full-up load transistor (MP4) composed of PMOS elements and receiving a TM_BL_LOADb signal for program verify lead; And a first transistor MN5 and a second transistor MN6 for an NMOS which are constituted by NMOS devices and are supplied with a BL_PCG signal for bit line precharging, and the first through fourth pull- MP1) (MP2) (MP3) (MP4) maintain high-impedance.

The program data and the read data are all 24 bits. If all of the bits match, a '1' is output through the PFb pin. If at least one bit of the bits does not match, 0 '.

The fuse OTP memory device of the present invention has the following effects.

First, the present invention proposes a program verify read mode for the fuse OTP memory device.

In the program verify mode, the program data is compared with the readers and the comparison result is output to the PFb pin. Therefore, it is possible to know whether the eFuse OTP is normally programmed through the PFb output from one pin in the package state.

In the program verify mode, a margin test for the resistance variation of the programmed eFuse link can be performed using a variable full-up load resistance circuit. Therefore, even if the resistance of the programmed eFuse link is reduced, it is possible to prevent a sensing failure from occurring.

1 is a block diagram of an eFuse OTP memory device according to an embodiment of the present invention;
2 is a circuit diagram of the program column selection unit PGM_COL_SEL shown in FIG.
3 is a circuit diagram of the program data latch unit (PD latch) shown in FIG.
FIG. 4 is a circuit diagram showing a differential paired eFuse cell constituting the cell array of FIG.
FIG. 5 is a diagram showing a variable pull-up load circuit configuration for performing a sensing margin test in consideration of fluctuations of eFuse resistances programmed in the cell array shown in FIG.
6 is a block diagram of a BL sense amplifier (BL) sensing a differential voltage between the bit lines BL and BLb when the voltage of the bit line BL (BLb) is pulled up by the variable pull-up load circuit of FIG. BL S / A, BL Sense Amplifier)
Fig. 7 is a circuit diagram of the comparator shown in Fig.
8 is a timing diagram when the eFuse OTP memory device according to the embodiment of the present invention operates in the program verification read mode
9 is a timing diagram showing experimental results in a program verification read mode according to an embodiment of the present invention.
10 (a) is a layout photograph of a differential paired eFuse OTP applied to the present invention, (b) is a layout photograph of a dual port eFuse OTP

Hereinafter, embodiments of the eFuse memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a test mode support for testing whether the eFuse OTP memory of the eFuse OTP memory device is normally programmed in a package state and to provide a test mode support programmed during data retention time using a variable pull- eFuse provides a technical feature to enable margin testing for resistance variation of the link.

For convenience of description, the description of the eFuse OTP memory device having the above-described technical features will be described with respect to the configuration of each circuit, and the operation thereof will be described as well.

1 is a block diagram of an eFuse OTP memory device according to an embodiment of the present invention.

In the description of FIG. 1, each configuration of the eFuse OTP memory device will be described with reference to the corresponding FIG. 2 to FIG. 7.

First, as shown in FIG. 1, the eFuse OTP memory device 100 is provided with a control logic unit 110 for supplying an appropriate internal control signal according to an operation mode according to a series of control signals. The control signal applied to the control logic unit 110 includes a read (RD) signal, a program (PGM: Program) signal, and a program verify-read enable signal (PVR_EN). Here, the PVR_EN signal serves to distinguish between a program-verify-read mode and a read mode. The read mode is a normal read mode in which only the program is read, unlike the read mode for program verification.

The eFuse OTP memory device 100 supports a read mode, a program mode, and a program verify read mode in accordance with the control signal. The present embodiment supports the program verification read mode among the above modes, and this mode will be mainly described. In other words, in the program verify lead mode, the sensing margin test using the variable full-up load is performed in consideration of the fluctuation of the programmed eFuse resistance, the test to check whether the eFuse OTP memory is normally programmed .

The eFuse OTP memory device 100 further includes a program column selection unit (PGM_COL_SEL) 120 for decoding the address signal ADD [4: 0] to select a programmed column, a program And a data latch unit (PD latch) 130. Here, the program data latch unit 130 latches the program input data DIN used to program the eFuse OTP memory in the program mode.

Also, the eFuse OTP memory device 100 includes an OTP cell array (hereinafter, also referred to as a 'cell array') 140 that performs an operation of programming an eFuse or reading data according to each mode. The cell array 140 according to the embodiment includes 1 row × 24 columns. The differential pair having a smaller sensing resistance of the eFuse link than the dual port eFuse OTP cell is a differential paired eFuse OTP cell ') Was used. And the link used for eFuse uses 'p-poly silicon' or 'Ti-silicon'. The memory cells constituting the OTP cell array 140 will be described in detail below with reference to FIG.

The eFuse OTP memory device 100 includes a data output buffer unit 160 for outputting data received from the cell array 140 according to a control operation of the control logic unit 110. The data output buffer unit 160 outputs the output data through the output port ([23: 0]) (DOUT / DOUTb) or transmits it to the comparison unit 170 described below.

A comparison unit 170 for comparing the program data PD [23: 0] latched in the program data latch unit 130 with the read data DOUT [23: 0] stored in the data output buffer unit 160 . The comparator 170 selects and outputs a '1' or '0' signal through a PFb (pass fail bar) pin. The signal '1' is a signal that is output when all of the 24 bits are matched and is normally programmed. The signal '0' is a signal that is output when the at least one bit of the 24 bits does not match and the program is not normally programmed.

The characteristics of the eFuse OTP memory device thus constructed will be described.

The eFuse OTP memory device 100 uses a 1-bit program bit and a 24-bit read bit. The program time for programming the data in the memory cell is 200 μs. Also, the power supply voltage used is a single power supply of VDD. The VDD voltage is used in program mode to supply sufficient program power to the eFuse link, and 4.5 to 5.5V in the read mode. In addition, only 5V MOS transistor was used.

Table 1 shows the main features of the eFuse OTP memory device described above.

Item Key Features Manufacture process Magna chip 0.18 μm process OTP cell array size 1 row * 24 columns Fuse Type p-poly silicon (Ti-silicide) Supply voltage 4.5V to 5.5V Temperature -40 ° C to 85 ° C
Operation mode Program mode Program Verification Lead Mode
(Program-Verify-Read mode) Read mode Program bit / Read bit 1bit / 24bit Program voltage 5.5V Program time 200 μs Access time 200 ㎱

Hereinafter, each of the components shown in FIG. 1 will be described in more detail.

FIG. 2 shows a circuit diagram of the program column selector PGM_COL_SEL shown in FIG.

The program column selecting section 120 operates as a circuit for selecting a column to be programmed in the program mode.

For this, as shown in FIG. 2, a first program column selector (PGM_COL_SEL) 122 and a second program column selector (PGM_COL_SELb) 124 are provided. In the embodiment, three NAND elements and four inverter elements . The first program column selection unit 122 receives the output signal of the NAD logic element and the DLb signal in a state where a NAND logic element for NAND processing the 'IPGM', 'YPRE 210' and 'YPRE43' signals is provided And a second inverter for outputting the output of the first NAND logic element as a PGM_BL_SEL signal, and a second inverter for inverting the output of the first NAND logic element, have. The second program column selector 124 includes a second inverter receiving the input data, a second NAND logic element for NADN processing the output of the second inverter and the DL signal, and a second NAND logic element for outputting the output of the second NAND logic element to the PGM_BLb_SEL And a second inverter for outputting the signal as a signal.

The program column selecting unit 120 drives the PGM_COL_SEL and PGM_COL_SELb signals at different levels according to the program mode and the read mode. That is, in the program mode, only the programmed PGM_COL_SEL and PGM_COL_SELb are driven to VDD and 0V while the row address A [4: 0] is decoded and the unprogrammed PGM_COL_SEL and PGM_COL_SELb are kept at 0V and VDD, respectively. On the other hand, in the read mode, PGM_COL_SEL [23: 0] and PGM_COL_SELb [23: 0] are all kept at 0V.

3 is a circuit configuration diagram of the program data latch unit (PD latch) shown in FIG.

Referring to FIG. 3, the program data latch unit 130 is a 'positive level sensitive D latch' structure, which stores program data in a program mode. Since the program data latch unit 130 having such a structure is a known technique, a detailed description thereof will be omitted.

Next, the configuration of the memory cell 141 used for designing the eFuse OTP memory will be described with reference to FIG. 4 is a circuit diagram showing a differential paired eFuse cell which is a memory cell 141 constituting the cell array 140 of FIG.

As shown in FIG. 4, the memory cell 141 is composed of a total of four MOS transistors and two eFuse elements and is symmetrical to each other.

Specifically, the memory cell 141 is divided into a first data storage unit 142 for storing program data and a second data storage unit 144 for storing complementary program data.

The first data storage unit 142 includes a first NMOS transistor MN1 and a second NMOS transistor MN2 connected in series and a first eFuse 1 connected to the connection line. The first NMOS transistor MN1 receives a 'PGM_BL_SEL' signal for selection of the program bit line BL through a gate terminal thereof, and a ground voltage (Vss) line is connected to a source terminal thereof. A read word line (RWL) is connected to a gate terminal of the second NMOS transistor MN2, and a bit line (BL) is connected to a drain terminal of the second NMOS transistor MN2.

The second data storage unit 144 includes the same elements as the first data storage unit 142 and is configured to be symmetrical with respect to each other. That is, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series. And a second eFuse (eFuse 2) is connected on the connection line. The third NMOS transistor MN3 is supplied with a 'PGM_BLb_SEL' signal for selecting a program bit line BLb through a gate terminal thereof and a ground voltage Vss line is connected to a source terminal thereof. The fourth NMOS transistor MN4 has a gate terminal connected to a read word line (RWL) and a drain terminal connected to a bit line.

The first NMOS transistor MN1 and the third NMOS transistor MN3 are program transistors capable of flowing a large program current and the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are program transistors capable of flowing a large program current, Can be used as a read-only transistor.

Further, a source line SL is connected to a connection line to which the first eFuse (eFuse 1) and the second eFuse (eFuse 2) are connected. In the program mode, the source line operates with a switching power supply that supplies a program voltage of 5.5 V to allow the overcurrent to flow, and to drive 0 V in the read mode and program verify read mode signals.

Meanwhile, the first to fourth NMOS transistors MN1, MN2, MN3 and MN4 of the memory cell 141 have different states according to the program data of '0' or '1'.

That is, the case where the program data is '1' will be described first. At this time, the PGM_BL_SEL signal and the PGM_BLb_SEL signal are applied at 5.5V and 0V, respectively. Accordingly, the first eFuse (eFuse 1) is in a blowing state as the overcurrent flows through the first eFuse (eFuse 1) and the first NMOS transistor (MN1). The blowing refers to a state in which the eFuse link is opened, and in this case, the resistance becomes several tens of k [Omega], and the program can not be performed. Since the third NMOS MN3 is off, the second eFuse eFuse 2 is not blown.

On the other hand, the program data is '0'. In this case, the first NMOS MN1 has an off state and the third NMOS MN2 has an on state. Therefore, only the second eFuse (eFuse 2) is in a blowing state, and the first eFuse (eFuse 1) is not blown.

The memory cell 141 provides different cell bias conditions in the program mode and the read mode. The cell bias conditions according to the program mode and the read mode are shown in [Table 2].

Program mode Lead mode Unselected Cell Selected Cell DIN 0 One 0 One 0 One RWL 0V 0V 0V 0V 0.67VDD 0.67VDD PD 0V 0V 0V 4.2V 0V 0V PDb 0V 0V 4.2V 0V 0V 0V SL 4.2V 4.2V 4.2V 4.2V 0V 0V BL Floating Floating Floating Floating 0V VDD BLb Floating Floating Floating Floating VDD 0V

The states of the input data DIN, the read word lines RWL, the program data PD and PDb, the source lines SL and the bit lines BL and BLb are shown in Table 2 in the program mode and the read mode, Let's take a look.

In the program mode, the read word line RWL is maintained at OV to turn off the second NMOS transistor MN2 and the fourth NMOS transistor MN4. The program data PD and PDb of the memory cell unselected in the row address A [4: 0] are held at 0 V while the program data PD and PDb of the selected memory cell 141 are held at 0 0V and 4.2V, and when the input data is 1, 4.2V and 0V are driven. When the input data is 0, the second eFuse 2 connected to the bit line BLb of the selected memory cell 141 is in a blowing state. When the input data DIN is 1, And the connected first eFuse (eFuse 1) becomes a blowing state. In addition, the source line is driven at 4.2V.

In the read mode, the read word line RWL is driven to 0.67 VDD and the program data PD and PDb are all kept at 0 V to turn off the first NMOS transistor MN1 and the third NMOS transistor MN3. And the source line SL is biased to OV. The voltages of the bit lines BL and BLb are 0 V and VDD when the input data is 0, and VDD and 0 V when the input data is 1, respectively.

FIG. 5 is a diagram illustrating a configuration of a variable pull-up load circuit for performing a sensing margin test in consideration of fluctuations of an eFuse resistance programmed in the cell array shown in FIG.

5, the variable pull-up load circuit 150 uses a method of precharging BL and BLb to the ground voltage VSS to reduce the read current flowing in the un-programmed cell . That is, since the resistance of the eFuse link programmed as described above may cause a sensing failure phenomenon if the eFuse resistance decreases during the data retention time, the resistance variation of the programmed eFuse should be considered. Thus, the variable pull-up load circuit 150 varies the impedance of the pull-up load of the BL pre-charge circuit used in the program verify lead mode and the read mode.

The configuration of the variable pull-up load circuit 150 for providing such a function is as follows.

5, first and second pull-up load transistors MP1 and MP2 constituted by a PMOS device and receiving a BL_LOADb signal and a third pull-up load transistor MP2 constituted by a PMOS device and receiving a TM_BL_LOADb signal, And a fourth pull-up load transistor MP3 (MP4). The first and third pull-up load transistors MP1 and MP3 are connected to the bit line BL and the second and fourth pull-up load transistors MP2 and MP4 are connected to the bit line BLb and the second pull- . The first through fourth pull-up transistors MP1, MP2, MP3, and MP4 are all designed to maintain a high-impedance state.

In addition, the variable pull-up load circuit 150 includes first and second transistors MN5 and MN6 for receiving the BL_PCG signal for BL pre-charge.

The first transistor MN5 is connected to the first and third pull-up load transistors MP1 and MP3 while the second transistor MP6 is connected to the second and fourth pull-up load transistors MP2 and MP4 ). &Lt; / RTI >

The variable full-up load circuit 150 is configured such that when the read word line (RWL) signal of the memory cell 141 is activated to 0.67 VDD, the BL_LOADb signal is applied to the first and second pull-up load transistors MP1 , The bit lines BL and BLb are pulled up to VDD, and the third and fourth pull-up load transistors MP3 and MP4 are turned off.

Since the impedances of the first to fourth pull-up transistors MP1, MP2, MP3 and MP4 are large, the bit line BL connected to the un-programmed eFuse maintains the ground voltage VSS, The bit line BL connected to the programmed eFuse is pulled up to the power supply voltage VDD. If the un-programmed memory cell 141 is read, the power supply voltage VDD, which is the precharge voltage of the bit line BL, is applied to the second NMOS transistor MN2 and the fourth NMOS transistor MN4 shown in FIG. And is discharged to the ground (GND) through the first eFuse (eFuse 1) and the second eFuse (eFuse 2).

On the other hand, the third and fourth pull-up load transistors MP3 (MP4) are used only during the test of the OTP IP, in which the first and second pull-up load transistors MP1 and MP2 are off.

Next, a circuit for detecting and outputting a differential voltage between the bit lines BL and BLb will be described with reference to FIG.

6, when the voltage of the bit line BL (BLb) is pulled up by the variable pull-up load circuit shown in FIG. 5, the BL sense amplifier detects differential voltage between the bit lines BL and BLb A circuit diagram of an amplifier (BL S / A, BL Sense Amplifier) is shown.

BL S / A 161 is a S / A-based D flip-flop circuit that senses the differential voltage between BL and BLb and uses a negative edge triggered D F / F. An SR latch circuit is also provided to latch the sensed differential voltage.

The BS S / A 161 maintains the ground voltage (VSS) at nodes N1 and N2 during SAENb high period. The SR latch circuit latches the data in the previous state. Then, when the transistor is in a low state, it senses a differential voltage between the bit lines BL and BLb and outputs the differential voltage through the data output ports DOUT and DOUTb.

The BL sense amplifier 161 performs the function of the data output buffer unit 160. That is, the data output buffer unit 160 functions as a part or all of the BL sense amplifier 161.

Fig. 7 is a circuit diagram of the comparator shown in Fig. 1. Fig.

The comparator 170 shown in FIG. 7 uses a dynamic pseudo NMOS (Logic pseudo NMOS) logic circuit. The comparison unit 170 compares the program data PD [23: 0] latched in the program data latch unit 130 and the read data stored in the data output buffer unit 160 when the program verify read mode is performed after the program mode (DOUT [23: 0]) match and output the result through the PFb pin.

When the enable signal COMP_EN for comparing the program data PD [23: 0] with the read data DOUT [23: 0] is 0 V, the comparator 170 compares the MATCH signal with the power supply voltage VDD), and PFb outputs VDD. When the enable signal is activated to a high state in a state where the read data DOUT [23: 0] is set, the program verify lead mode is performed.

If the program data PD [23: 0] and the read data DOUT [23: 0] match in accordance with the execution of the program verification read mode, the match signal maintains the power supply voltage VDD, And outputs the power supply voltage VDD. On the other hand, if at least one bit of the program data PD [23: 0] and the read data DOUT [23: 0] is different, the match signal is discharged to 0V and PFb outputs 0V.

8 is a timing diagram when the eFuse OTP memory device according to the embodiment of the present invention operates in the program verification read mode.

Referring to the timing diagram, when the read signal and the PVR_EN signal are all activated at a high level (a), output data is output after a predetermined access time (t _AC ) has passed.

Then, the comparator 170 compares the program data PD [23: 0] with the read data DOUT [23: 0] and outputs the result through the PFb pin.

The eFuse OTP memory device having the memory cell 141 configured in this way is tested to see if the eFuse OTP memory is normally programmed in the package state and at the same time is programmed using a variable pull-up load You can perform a margin test on the resistance variation of the eFuse link.

The second NMOS transistor MN2 and the fourth NMOS transistor MN4 which are the read-only transistors shown in Fig. 4 are selected by the read word line RWL in the read mode, and the variable pull- The voltage of the bit lines BL and BLb is pulled up to sense the differential voltage of the voltages output through the data output ports DOUT and DOUTb. At this time, the variable pull-up load circuit 150 varies the full-up load of the bit line pre-charge circuit used in the program verify lead mode and the read mode.

And, since the eFuse resistance that can be sensed in the program verify lead mode is larger than the lead mode, the difference between the eFuse resistance that can be sensed in the program verify lead mode and the lead mode becomes the margin resistance during the data retention time.

Therefore, in the program verify read mode, the sensing margin test is performed using the variable pull-up load circuit 150 in consideration of the fluctuation of the programmed eFuse resistor.

At this time, the comparison unit 170 compares the program data PD [23: 0] with the read data DOUT [23: 0]. At this time, the comparison unit 170 outputs the comparison value through the PFb output to one pin, so that it can be determined whether the memory cell is normally programmed even in the package state.

Next, an experimental result of the sensing resistance of the eFuse link programmed in the eFuse OTP memory device of the present embodiment will be described.

This is compared to the dual-port eFuse OTP. The comparison results are shown in Table 3.

Program Verification Lead Mode Lead mode In this embodiment
(Differential paired eFuse OTP) 9㏀ 4㏀ Dual port eFuse OTP 110㏀ 50㏀

As shown in Table 3, it can be seen that the sensing resistance of the programmed eFusse of Differential paired eFuse OTP applied to the present embodiment is smaller than that of the dual port eFuse OTP.

FIG. 9 shows experimental results in the program verification lead mode according to the embodiment of the present invention, in which (a) is programmed with '1' and (b) with '0'.

When the read signal is activated, the output data is output after a predetermined access time has elapsed.

Then, when the enable signal for comparison is activated, the PFb of the comparator 170 compares the program data PD [23: 0] with the read data DOUT [23: 0] and outputs the result . As a result of comparison, if the program data PD [23: 0] coincides with the read data DOUT [23: 0], 'PASS' is output. Otherwise, 'FAIL' is output.

10 is a layout of a differential paired eFuse OTP and an existing dual port eFuse OTP according to the present invention.

10 (a) is a layout photograph of a differential paired eFuse OTP applied to the present invention, and FIG. 10 (b) is a layout photograph of a dual port eFuse OTP. This is the result of using Magnap chip 0.18 mu m BCD process.

The size of the differential paired eFuse OTP is 367.965 μm × 107.34 μm (= 0.0395 mm 2) and the dual port eFuse OTP is 239.6 μm × 111.6 μm (= 0.0284 mm 2) .

And 289.9 mu m x 163.65 mu m (= 0.0475 mm < 2 >) when using the Magna chip 0.35 mu m BCD process.

As described above, according to the present invention, the program verify read mode is proposed for the eFuse memory device and the comparison result is output to the PFb pin by comparing the program data with the read data. Thus, the PFb , It can be seen that the eFuse OTP is normally programmed and a margin test for the resistance variation of the programmed eFuse link using the variable pull-up load resistance circuit is possible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent that modifications, variations and equivalents of other embodiments are possible. Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: E-fuse OTP memory device 110: Control logic part
120: program column selection unit 130: program data latch unit
140: OTP cell array 141: memory cell
150: variable pull-up load circuit 160: data output buffer unit
161: BL sense amplifier 170:

Claims

A control logic unit for supplying a control signal for a read mode, a program mode and a program-verify-read mode;
A program column selecting unit for selecting a column to be programmed in the program mode;
A data latch unit for storing program data in a column selected by the program column selecting unit;
an OTP cell array composed of a plurality of differential pair eFuse cells for performing an operation of programming an eFuse or reading data;
A data output buffer unit for reading and storing data from the OTP cell array;
A comparing unit comparing the program data stored in the data latch unit and the read data of the data output buffer unit when the program verify read mode is performed; And
And one pass-fail-bar (PFb) pin outputting a comparison result of the comparison unit.

The method according to claim 1,
The differential pair eFuse cell includes:
A first data storage unit for storing program data; And
And a second data storage unit having a structure symmetrical with the first data storage unit to store complementary program data.

3. The method of claim 2,
The first data storage unit includes a first NMOS transistor MN1 and a second NMOS transistor MN2 connected in series and a second NMOS transistor MN2 connected to the first NMOS transistor MN1 and the second NMOS transistor MN2. A first eFuse (eFuse 1)
The second data storage unit includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4 connected in series and a third NMOS transistor MN3 and a fourth NMOS transistor MN4 connected to each other. And a second eFuse (eFuse 2)
The first eFuse and the second eFuse are connected to each other,
And a source line, which is a switching power source for driving the OV in the read mode and the program verify read mode, is connected to the connection node of the first eFuse and the second eFuse by applying a program voltage of 5.5 V in the program mode An e-fuse OTP memory device.

The method of claim 3,
The first NMOS transistor MN1 and the third NMOS transistor MN3 are program transistors,
And the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are read-only transistors for reducing the current in the read mode.

The method of claim 3,
Wherein the first eFuse is in a bolling state when the program data of the differential pair eFuse cell is '1' and the second eFuse is in a state of 'bling' when the program data of the differential pair eFuse cell is '0' bolwing " state. < / RTI >

The method according to claim 1,
Wherein the OTP cell array is configured such that the differential pair eFuse cell comprises 1 row x 24 columns.

The method according to claim 1,
A variable full-up load circuit for sensing margin test is further configured,
Wherein the variable pull-up load circuit varies the impedance of a pull-up load of a bit line pre-charge circuit used in the program verify lead mode and the read mode.

8. The method of claim 7,
The variable pull-up load circuit includes:
Wherein the difference between the program verify read mode and the eFuse resistance that can be sensed in the read mode is used.

9. The method of claim 8,
The variable pull-up load circuit includes:
A first pull-up load transistor (MP1) and a second pull-up load transistor (MP2), which are composed of PMOS devices and whose gate ends are connected to each other and are supplied with a BL_LOADb signal;
A third full-up load transistor (MP3) and a fourth full-up load transistor (MP4) composed of PMOS elements and receiving a TM_BL_LOADb signal for program verify lead;
And a first transistor MN5 and a second transistor MN6 for NMOS which are constituted by NMOS devices and are supplied with a BL_PCG signal for bit line precharge,
Wherein the first through fourth pull-up transistors MP1, MP2, MP3, and MP4 maintain a high-impedance state.

The method according to claim 1,
Wherein the program data and the read data are all 24 bits,
And outputs '1' through the PFb pin when all the bits match,
And outputs '0' through the PFb pin if at least one bit or more of the bits do not coincide with each other.