KR101403500B1 - One-Time Programable Memory of Electrical Fuse Type With High Reliability For PMICs - Google Patents

Abstract

 The present invention relates to a highly reliable fuse-type memory device for a PIC. This is a 24-bit eFuse (OTP) one-time programmable memory device for a power management IC (PMIC), which includes an OTP cell array of 1 row x 24 columns, control signals RD, PGM, TM_EN A selection circuit PGM_COL_SEL for decoding a programmed column by decoding the address A [4: 0], a data latch for storing program data (data 23: 0] stored in the data latch and the read data program output signal DOUT [23: 0] of the output buffer, and an output buffer for reading data of the bit line BL. ], And in a program verify read mode for testing whether the eFuse OTP memory is normally programmed in the package state, the comparison circuit is configured to determine whether the eFuse OTP memory By comparing the read data read from the read mode and the program data is configured to output the comparison result to the comparison signal output terminal. Accordingly, in the PMIC chip package having the fuse-off-chip memory, after the fuse-off-chip memory is programmed, the error of the program in the package state can be tested by data output through one pin, Reliability is ensured, and the like.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-reliability fuse-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an OTP (One Time Programmable) memory device using an eFuse (electrical fuse) method. More particularly, the present invention relates to a PMIC IC chip with a single pin in the PMIC chip package, it is possible to check whether the e-fuse memory is normally programmed, thereby ensuring high reliability of the PMIC. Type memory device.

BACKGROUND ART [0002] Recently, with the development of mobile information devices operating based on batteries, power semiconductor integrated power management ICs (PMICs), which perform efficient control and management of limited battery resources, are becoming very important. PMIC is a key component in battery-based mobile information devices because it saves space and costs down by making various control and management functions one chip.

PMIC is a power control module composed of discrete power device module for power, high voltage power circuit, low voltage digital circuit, high voltage and low voltage analog circuit. It consists of two chips or one chip and converts the power to the electronic equipment Charge, and control of a semiconductor device, it is required to have a higher voltage and a higher reliability compared to a general semiconductor device.

In particular, the PMIC requires a small amount of nonvolatile memory to perform the analog trimming function. An embedded non-volatile memory is widely used for an eFuse OTP (electrical fuse one-time programmable) memory that can be used for a logic process-based design that does not require an additional process, and the memory capacity is required to be several hundred Kb or less Document 1:... SH Kulkarni et al, a 4kb metal-fuse OTP-ROM macro featuring a 2V programmable 1.37 2 1T1R bit cell in 32 high-k metal-gate CMOS, IEEE Solid-State Circuits, vol 45, no 4 , pp. 863-868, April 2010). The eFuse OTP memory is programmed by blowing an overcurrent to the eFuse (see Reference 2: J. Safran, A. Leslie, et al., A compact eFuse programmable array memory for SOI CMOS, Symposium on VLSI Circuits, pp. Pp. 72-73, June 2007) (Reference 3: N. Robson et al., Electrically programmable fuse (eFuse): From memory redundancy to autonomic chip, Proceedings of Custom Integrated Circuits Conference, pp. 799-804, Sep. 2007). The program transfer resistance of eFuse is about 50 ~ 100 ohms, and after program overcurrent flows through eFuse, the post-programmed resistance of eFuse is usually more than a few tens of ohms. In this way, eFuse programs one bit of digital data into either a conduction state or a high-resistance state.

The eFuse OTP memory is required to be designed to prevent the sensing failure from occurring when the resistance of the programmed eFuse link is reduced during the data retention time (see reference 4: M. Alavi et al., A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process, IEEE International Electron Devices Meeting, pp. 855-858, Dec. 1997). A variable pull-up load resistor that takes into account the programmed resistance variation of the eFuse link is used in the bit line (BL) precharging circuit in test read mode and read mode. Up load resistor. The eFuse resistors that can be sensed in the test read mode are larger than the read mode. Therefore, the difference between the eFuse resistances that can be sensed in the test read mode and the read mode is the sensing margin resistance during the data retention time (see Reference 5: JH Kim et al., Design of 1-Kb eFuse OTP memory (Refer to Reference 6: JH Jang et al., Design of an 8-bit differential paired eFuse OTP memory IP (IEEE 802.16e), Vol. 11, No. 2, pp. 88-94, reducing sensing resistance, J. Cent. South Univ., vol. 19, no. 1, pp. 168-173, January 2012). It should be designed so that the eFuse OTP memory can be normally programmed or tested in package state. However, the PMIC chip has a problem in that it can not read OTP read data of 8b or more from the package pin because the number of used pins is few.

It is a general object of the present invention to solve the problem that it is not possible to test whether a program is erroneous in a package state after programming the fuse-atopy memory in a PMIC chip package having the conventional fuse-offset memory.

Specifically, an object of the present invention is to provide a program-verify-read mode for testing whether the eFuse OTP memory is normally programmed in the package state of the PMIC. In program mode, the program data is latched into the program data latch circuit as well as used to program the eFuse OTP memory. The program data comparison circuit using the dynamic pseudo NMOS logic circuit compares the program data latched in the program data latch circuit with the read data read in the read mode, (pfb, pass fail bar) pin. This allows you to see if the eFuse OTP memory is normally programmed in the package state.

It is also an object of the present invention to provide a method of configuring a program verify read mode to enable a margin test for resistance variation of an eFuse link programmed during a data retention time using a variable pull-up load resistor circuit.

The above object is achieved by a highly reliable fuse-type memory device for a PCMCIA provided according to the present invention.

A highly reliable fuse-type memory device for a PC IC provided according to an aspect of the present invention includes a 24-bit electrical fuse (OTP) one-time programmable memory (PMT) for a power management IC A control logic for supplying an internal control signal suitable for an operation mode in accordance with control signals RD, PGM, TM_EN, an address A [4: 0] a data latch circuit for storing program data, an output buffer for reading data of the bit line BL, and a program data PD [ 23: 0] of the output buffer and the read data program output signal (DOUT) [23: 0] of the output buffer are matched, and whether or not the eFuse OTP memory is normally programmed in the package state In the program verify read mode, the comparison circuit may be configured to compare the program data latched in the latch circuit with the read data read in the read mode, and output the comparison result to the comparison signal output terminal.

In one embodiment, the comparison circuit compares the program data (PD) [23: 0] with the program output signal DOUT [23: 0] (= 1) as the comparison signal pfb and output a logic low signal (= 0) as the comparison signal pfb when one or more of the twenty-four bits do not coincide with each other.

In another embodiment, the comparison circuit is a program data comparison circuit using a dynamic pseudo NMOS logic circuit. The program data comparing circuit compares the program data latched in the program data latch circuit with the read data read in the read mode, .

In yet another embodiment, the eFuse cell of the eFuse memory may be a 24bit dual port eFuse OTP cell.

According to the present invention having the above-described configuration, in the PMIC, a program verification read mode is provided for testing whether the eFuse OTP memory is normally programmed in the package state. In program mode, the program data is latched into the program data latch circuit as well as used to program the eFuse OTP memory. After performing the program mode, the program data comparison circuit using the dynamic pseudo-NMOS logic circuit compares the program data latched in the program data latch circuit with the read data read in the read mode and outputs the comparison signals (pfb, pass fail bar) pins. This allows you to see if the eFuse OTP memory is normally programmed in the package state. In the program verify read mode, a margin test for the resistance variation of the eFuse link programmed during the data retention time is possible using a variable full-up load resistance circuit. Accordingly, in the PMIC chip package having the fuse-off-chip memory, after the fuse-off-chip memory is programmed, the error of the program in the package state can be tested by data output through one pin, Reliability is ensured, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a dual port eFuse cell circuit diagram according to the present invention. Fig.
2 is a block diagram of a 24 bit eFuse OTP memory according to the present invention;
FIG. 3A is a timing diagram for each operation mode according to the present invention, showing a program mode. FIG.
FIG. 3B is a timing diagram for each operation mode according to the present invention, showing a read mode. FIG.
FIG. 3C is a timing diagram for each operation mode according to the present invention, showing a program verification read mode. FIG.
4 is a circuit diagram illustrating a configuration of a selection circuit (PGM_COL_SEL) according to the present invention.
5 is a circuit diagram illustrating a configuration of a program data latch circuit according to the present invention;
6 is a circuit diagram illustrating a configuration of an output buffer circuit according to the present invention;
7 is a circuit diagram illustrating a configuration of a 24-bit program data comparison circuit using dynamic pseudo NMOS logic according to the present invention.
FIG. 8A is a timing diagram showing simulation results in a program verify read mode according to the present invention, and is a diagram illustrating a case where the program is programmed as '1'; FIG.
FIG. 8B is a timing diagram showing simulation results in a program verification read mode according to the present invention, and is a diagram illustrating a case where the program is programmed with '0'. FIG.
Figure 9 is a layout of a 24 bit eFuse OTP memory designed in accordance with the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and is defined by the claims of the present invention.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention designed a high reliability 24 bit dual port eFuse OTP memory for PMIC based on BCD process as described in detail below. The program data comparison circuit using the proposed dynamic pseudo NMOS logic circuit compares the program data with the read data in the program verification read mode and outputs the comparison result to the output terminal of the comparison signal (pfb, pass fail bar). Therefore, only one comparison signal output terminal can be tested to check whether the eFuse OTP memory is normally programmed. The program verify read mode can be used to design a sensing margin test circuit with a variable pull-up load that takes into account variations in the programmed eFuse resistors. According to one embodiment of the present invention, the layout area of the 24bit eFuse OTP memory designed using the Magnachip 0.35 BCD process is 289.9 mu m 163.65 mu m (= 0.0475 mm2).

Table 1 shows the main features of the 24bit eFuse OTP memory designed using Magnachip 0.35 BCD process according to one embodiment of the present invention.

As can be seen from Table 1, the cell array is composed of 1 row x 24 columns. The eFuse OTP cell uses a dual port eFuse OTP cell with a smaller cell area than the differential paired eFuse OTP cell to reduce the layout area of the OTP memory. The eFuse link uses p-polysilicon (p -polysilicon) was used. The operation modes are a program mode, a read mode, and a program verify read mode. The program bit and the read bit of the eFuse OTP memory are 1 bit and 24 bits, respectively, and the program time is 200s. The power supply voltage used is a single power supply of VDD. When the VDD voltage is programmed, 5.5V is used to supply sufficient program power to the eFuse link, and 4.5V to 5.5V is used in the read mode. The devices used in the design were only 5V MOS transistors.

For example, a circuit diagram of a dual-port eFuse OTP cell used in a 24-bit eFuse OTP memory design is shown in FIG. 1, and includes a programmable NMOS transistor MN1 capable of flowing a large program current and a read And the NMOS transistor MN2 for the NMOS transistor MN2 are respectively used.

The bias voltage of the eFuse cell for each operation mode is shown in Table 2.

As can be seen in Table 2, both the source line (SL) and the PGM_COL_SEL signal of the eFuse cell programmed to 1 in program mode are driven to VDD. Thus, when an overcurrent flows through the eFuse, the eFuse is blown. In read mode, the read word line (RWL) drives 0.67VDD and SL drives 0V. The cell programmed with 0 outputs 0V to the bit line BL since the eFuse is in the conduction state, whereas the cell programmed with 1 outputs the VDD to the bit line BL since it is in the high resistance state.

As shown in FIG. 2, the block diagram of the 24b eFuse OTP memory designed using the BCD process supplies an internal control signal suitable for the operation mode according to the OTP cell array of 1 row x 24 columns, the control signals (RD, PGM, TM_EN) (PGM_COL_SEL) for selecting a column to be programmed by decoding the address A [4: 0], a data latch circuit for storing program data, and a bit line BL And an output buffer for reading data and a comparison circuit for comparing the program data PD [23: 0] stored in the data latch with the read data program output signal DOUT [23: 0] of the output buffer .

If all the bits match when the corresponding bits of the program data PD [23: 0] and the program output signal DOUT [23: 0] are compared with each other, the comparison signal pfb is a logic high signal (= 1), and outputs a logic low signal (= 0) if one or more of the 24 bits do not coincide. The TM_EN (test mode enable) signal distinguishes between program verify read mode and read mode.

Figures 3a, 3b, and 3c show timing diagrams for each mode of operation of the eFuse OTP. FIG. 3A is a timing diagram in the program mode. In the program operation, when the PGM signal is activated from low to high with the address A [4: 0] and the input data DIN first applied, the OTP memory cell to be selected is programmed. And in program mode, the program input data DIN is used to program the eFuse OTP memory as well as to the program data latch circuitry.

FIG. 3B is a timing diagram in the read mode. When the RD signal is activated high, 24-bit output data is output to the program output signal DOUT [23: 0] port after the access time has passed. At this time, PGM signal should be kept low.

FIG. 3C is a timing diagram of the program verify read mode. When the RD signal and the TM_EN signal are simultaneously activated to high, the program data comparison circuit using the dynamic pseudo NMOS logic circuit can read the program data latched in the program data latch circuit, Compare the read data and output the comparison result to the comparison signal output terminal.

4 is a selection circuit (PGM_COL_SEL) for selecting a column to be programmed in the program mode. When entering the program mode, only the PGM_COL_SEL programmed by decoding the row address A [4: 0] is driven to VDD (= 5.5V) The unprogrammed PGM_COL_SEL signal maintains 0V. In the read mode, the PGM_COL_SEL [23: 0] signal remains at 0V.

And Figure 5 is a program data latch circuit in the form of a positive level-sensitive D latch. In program mode, program data DIN is stored in the program data latch circuit.

6 illustrates an output buffer circuit. In this circuit, the bit line (BL) is precharged to 0 V by the BL_PCG signal which is a bit line (BL) bit line precharge signal in the read mode and the program verify read mode. When the read word line (RWL) signal of the OTP cell is activated to 0.67 VDD, the bit line BL is pulled up to VDD by the pull-up load transistor MP1 or MP2. When the data of the eFuse OTP memory cell is sufficiently transmitted to the bit line BL, the output buffer senses the bit line (BL) voltage of VDD or 0V after the sense amplifier enable bar (SAENb) signal is activated to 0V, DOUT) Outputs data read to the port. However, the eFuse OTP cell may experience bit line (BL) sensing failure when the resistance of the programmed eFuse link decreases during the data retention time. Therefore, in the present invention, a variable pull-up load circuit (refer to Reference Document 5) is used in consideration of the variation of the programmed eFuse resistor.

In the program-verify-read mode after programming the eFuse, only the MP1 of the variable pull-up load transistors of FIG. 6 is turned on to test whether the eFuse resistor is normally programmed. In the read mode, only the MP2 having a smaller pull-up resistance than the MP1 is turned ON, so that even if the programmed eFuse resistance fluctuates low, the bit line BL is pulled up to sense normal data. Therefore, the difference between the eFuse resistances that can be sensed in the program verify read mode and the read mode becomes the bit line (BL) sensing margin resistance in the output buffer during the data retention time. On the other hand, when the programmed eFuse resistance is changed to a high level, the sensing margin of the bit line (BL) is increased.

Meanwhile, FIG. 7 illustrates a program data comparison circuit using a dynamic pseudo NMOS logic circuit. This comparison circuit compares the program data (PD) [23: 0], which is program data latched in the program data latch circuit, with the program output signal (DOUT) [23: 0] And the data is compared with each other. The program data comparison result is output to the comparison signal output terminal.

When the COMP_EN (compare enable) signal is 0V, the MATCH signal maintains the precharge state to VDD and the comparison signal pfb outputs VDD. In the program verify read mode, COMP_EN is activated high with the program output signal (DOUT) [23: 0] first set-up. If the 24-bit program data PD [23: 0] and the program output signal DOUT [23: 0] match each other, MATCH maintains VDD and the comparison signal pfb is output to VDD . If one of the 24-bit data is different, the MATCH signal is discharged to 0V and the comparison signal pfb outputs 0V.

MP1 in FIG. 7 is used to prevent the MATCH signal from falling to low due to the leakage current when all the 24-bit data match with the latch-back transistor.

Simulation result

In accordance with the present invention, a 24b eFuse OTP memory based on a 0.35 BCD process was designed. Table 3 shows the simulation results for the sensing resistance of the programmed eFuse link.

As shown in Table 3, the VDD = 4.5V, the FF model parameters, the eFuse sensing resistance in the program verify read mode of -40 and the read mode were simulated at 9k ohms and 4k ohms, respectively. In this case, the programmed eFuse resistor can be normally sensed as long as it does not drop below 4kΩ.

8A is a simulation result in a program verification read mode for a 24 bit eFuse OTP memory when programmed as '1' according to the present invention, and FIG. 8B is a simulation result of a 24 bit eFuse OTP memory when programmed as '0' This is the simulation result in the program verification read mode. When the RD signal is activated, the program output signal (DOUT) is output after the access time has elapsed. Thereafter, the COMP_EN signal is activated high, and the comparison signal pfb outputs the comparison result of the program data PD and the program output signal DOUT.

FIG. 9 shows a layout photograph of a 24-bit eFuse OTP memory designed using the 0.35 BCD process according to the present invention. The layout area is 289.9 μm and 163.65 μm (= 0.0475 mm 2).

conclusion

As described above, a program verify read mode is proposed to test whether the eFuse OTP memory is normally programmed in the package state according to the present invention. In the program verify read mode, the program data comparison circuit using the dynamic pseudo NMOS logic circuit compares the program data latched in the program data latch circuit with the read data read in the read mode, and outputs the comparison result to the comparison signal output terminal. Thus, it is possible to know whether the eFuse OTP memory is normally programmed through the comparison signal pfb output to one pin in the package state. Also, in the program verify read mode, it is designed to enable margin test for resistance fluctuation of eFuse link programmed during data retention time by using variable full - up load resistance circuit. The layout size of the 24b eFuse OTP memory designed using the Magnchip 0.35 BCD process according to the present invention is 289.9 mu m and 163.65 mu m (= 0.0475 mm < 2 >).

SL: Source line
BL: bit line
RWL: Read word line
MN1: Programmable transistor
MN2: Read transistor
eFuse: This fuse

Claims (4)

What is claimed is: 1. An eFuse, electrical fuse, one-time programmable (OTP) memory device for a power management IC (PMIC)
The fuse-or-notch memory device
Control logic for supplying an internal control signal to the operation mode according to the control signal;
A selection circuit receiving the internal control signal and selecting a column to be programmed by decoding the address;
A data latch circuit receiving the internal control signal and storing program data of the column selected by the selection circuit;
An apical cell array including aprotic cells receiving the internal control signal and receiving the program data of the data latch circuit;
An output buffer receiving the internal control signal and reading the program data of a bit line (BL) connected to the atopy cell array; And
And a comparison circuit which receives the internal control signal and compares the program data PD stored in the data latch with the program output signal DOUT output from the output buffer,
The comparison circuit compares the program data latched in the latch circuit with the read data read in the read mode to test whether the fuse-or-notch memory device is programmed normally in the package state, And outputting the comparison result as a comparison signal that is an output signal of the fuse type memory device. 2. The circuit of claim 1,
When the program data and the program output signal are compared with each other, the comparison signal outputs a logic high signal to indicate that all the bits match,
Wherein when the program data is compared with the program output signal, the comparison signal outputs a logic low signal if one or more bits do not coincide with each other. 2. The circuit of claim 1,
A comparison circuit using a dynamic pseudo-random logic circuit for comparing the program data latched in the data latch circuit with the program output signal which is read data read in a read mode and outputting a comparison result using the comparison signal; A highly reliable fuse-type memory device for a PCMCIA. The method according to claim 1,
Wherein the dual port is a fuse-type fuse cell. 2. The fuse-type memory device of claim 1, wherein the dual port is a fuse-type fuse cell.

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