KR101008459B1 - 칩본딩 방식을 개선한 스마트카드 제조방법 - Google Patents
칩본딩 방식을 개선한 스마트카드 제조방법 Download PDFInfo
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- KR101008459B1 KR101008459B1 KR1020100084767A KR20100084767A KR101008459B1 KR 101008459 B1 KR101008459 B1 KR 101008459B1 KR 1020100084767 A KR1020100084767 A KR 1020100084767A KR 20100084767 A KR20100084767 A KR 20100084767A KR 101008459 B1 KR101008459 B1 KR 101008459B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
- G06K19/07754—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
Abstract
본 발명은 양측에 제1,2접속단자가 열전도성을 갖는 열전달통로와 연결되는 보드에 칩이 실장된 COB모듈이 포함된 스마트 카드를 제조하는 방법에 있어서, 단부에 안테나단자를 갖추어 일측면 가장자리를 따라 루프형태로 안테나코일이 배선되고, 상기 칩이 삽입 배치되는 칩배치공이 관통형성된 안테나 시트를 제공하는 단계; 상기 안테나단자에 도전성을 갖는 도전볼을 적층하고 상기 제1,2접속단자가 상기 도전볼과 각각 대응되도록 상기 칩을 상기 칩배치공에 삽입 배치하는 단계; 상기 제1,2접속단자와 안테나단자가 간접열을 이용하여 접속될 수 있도록 가열봉으로 상기 열전달통로 측에 열과 압력을 제공하는 단계; 상기 보드가 삽입배치되는 보드배치공이 관통형성된 모듈시트를 상기 안테나시트에 적층하는 단계; 및 상기 안테나 시트 및 모듈시트의 외부면에 제1,2외부시트를 각각 적층하는 단계;를 포함하고, 상기 가열봉은 상기 열전달통로에 350~450℃ 범위의 열을 1~2초의 시간동안 제공하는 것을 특징으로 한다.
Description
도 2는 종래기술에 따라 제조되는 스마트 카드의 종단면도.
도 3은 본 발명의 제조방법에 따라 제조된 스마트 카드의 분리사시도.
도 4는 본 발명의 제1실시예에 따른 칩본딩 방식을 개선한 스마트카드 제조방법의 공정 순서도.
도 5는 본 발명의 제1실시예에 따라 제조된 스마트 카드의 종단면도.
도 6은 본 발명의 제2실시예에 따른 칩본딩 방식을 개선한 스마트카드 제조방법의 공정 순서도.
도 7은 본 발명의 제2실시예에 따라 제조된 스마트 카드의 종단면도.
120 : 모듈시트 122 : 보드배치공
130 : 안테나코일 시트 132 : 안테나코일
134 : 안테나단자 136 : 칩배치공
140 : 제2외부시트 150,250 : COB모듈(150,250)
151 : 칩 152,252 : 보드
153 : 제1,2접속단자 154,254 : 열전달통로
160 : 가열봉 B : 도전볼
Claims (6)
- 양측에 제1,2접속단자가 열전도성을 갖는 열전달통로와 연결되는 보드에 칩이 실장된 COB모듈(150,250)이 포함된 스마트 카드를 제조하는 방법에 있어서,
단부에 안테나단자를 갖추어 일측면 가장자리를 따라 루프형태로 안테나코일이 배선되고, 상기 칩이 삽입 배치되는 칩배치공이 관통형성된 안테나 시트를 제공하는 단계;
상기 안테나단자에 도전성을 갖는 도전볼을 적층하고 상기 제1,2접속단자가 상기 도전볼과 각각 대응되도록 상기 칩을 상기 칩배치공에 삽입 배치하는 단계;
상기 제1,2접속단자와 안테나단자가 간접열을 이용하여 접속될 수 있도록 가열봉으로 상기 열전달통로 측에 열과 압력을 제공하는 단계;
상기 보드가 삽입배치되는 보드배치공이 관통형성된 모듈시트를 상기 안테나시트에 적층하는 단계; 및
상기 안테나 시트 및 모듈시트의 외부면에 제1,2외부시트를 각각 적층하는 단계;를 포함하고,
상기 가열봉은 상기 열전달통로에 350~450℃ 범위의 열을 1~2초의 시간동안 제공하는 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법. - 제 1항에 있어서,
상기 압력은 200~250g/㎠인 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법. - 제 1항에 있어서,
상기 도전볼은 중량비가 Sn 96.5, Ag 3.0, Cu 0.5를 함유하도록 이루어지는 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법. - 제 1항에 있어서,
상기 열전달통로는 상기 보드의 양측에 각각 관통홀이 관통형성되고 상기 관통홀에 열전도성 물질이 충진되어 상기 제1,2접속단자와 각각 연결되는 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법. - 제 1항에 있어서,
상기 열전달통로는 상기 제1,2접속단자와 각각 연결되도록 열전도성을 갖는 박층이 코팅되는 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법. - 제 1항 내지 제 5항 중 어느 한 항에 있어서,
상기 가열봉에서 열전달통로 측에 제공되는 열과 압력은 상기 제1,2접속단자 중 어느 하나가 먼저 접속되고 나머지가 나중에 접속되도록 순차적으로 제공되는 것을 특징으로 하는 칩본딩 방식을 개선한 스마트카드 제조방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020100084767A KR101008459B1 (ko) | 2010-08-31 | 2010-08-31 | 칩본딩 방식을 개선한 스마트카드 제조방법 |
PCT/KR2010/009432 WO2012030026A1 (ko) | 2010-08-31 | 2010-12-28 | 칩본딩 방식을 개선한 스마트카드 제조방법 |
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KR1020100084767A KR101008459B1 (ko) | 2010-08-31 | 2010-08-31 | 칩본딩 방식을 개선한 스마트카드 제조방법 |
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CN109088162A (zh) * | 2018-08-17 | 2018-12-25 | 深圳市嘉姆特通信电子有限公司 | 散热及辐射兼用无线通信天线结构 |
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CN105117763B (zh) * | 2015-08-14 | 2019-01-29 | 深圳源明杰科技股份有限公司 | 智能卡及智能卡的制造方法 |
CN107706287B (zh) * | 2017-09-29 | 2019-05-14 | 新月光电(深圳)股份有限公司 | Cob光源制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910019719A (ko) * | 1990-05-30 | 1991-12-19 | 아베 후사코 | 공작물 상호간의 접합을 위한 공작물 가열장치 |
KR20030019521A (ko) * | 2003-02-06 | 2003-03-06 | 주식회사 제이디씨텍 | 납땜 방식에 의한 콤비형 아이씨 카드의 아이씨 칩 부착방법 |
KR20030019481A (ko) * | 2003-01-07 | 2003-03-06 | 주식회사 제이디씨텍 | 콤비형 아이씨 카드 및 그 제조 방법 |
KR100848465B1 (ko) * | 2007-12-03 | 2008-07-25 | 진영범 | 핫 에어를 이용한 와이어 도체 접속 장치 |
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FR2781298B1 (fr) * | 1998-07-20 | 2003-01-31 | St Microelectronics Sa | Procede de fabrication d'une carte a puce electronique et carte a puce electronique |
JP2000182017A (ja) * | 1998-12-18 | 2000-06-30 | Dainippon Printing Co Ltd | 接触型非接触型共用icカードおよびその製造方法 |
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- 2010-08-31 KR KR1020100084767A patent/KR101008459B1/ko active IP Right Grant
- 2010-12-28 WO PCT/KR2010/009432 patent/WO2012030026A1/ko active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910019719A (ko) * | 1990-05-30 | 1991-12-19 | 아베 후사코 | 공작물 상호간의 접합을 위한 공작물 가열장치 |
KR20030019481A (ko) * | 2003-01-07 | 2003-03-06 | 주식회사 제이디씨텍 | 콤비형 아이씨 카드 및 그 제조 방법 |
KR20030019521A (ko) * | 2003-02-06 | 2003-03-06 | 주식회사 제이디씨텍 | 납땜 방식에 의한 콤비형 아이씨 카드의 아이씨 칩 부착방법 |
KR100848465B1 (ko) * | 2007-12-03 | 2008-07-25 | 진영범 | 핫 에어를 이용한 와이어 도체 접속 장치 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109088162A (zh) * | 2018-08-17 | 2018-12-25 | 深圳市嘉姆特通信电子有限公司 | 散热及辐射兼用无线通信天线结构 |
CN109088162B (zh) * | 2018-08-17 | 2024-02-20 | 深圳市嘉姆特科技有限公司 | 散热及辐射兼用无线通信天线结构 |
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