KR101003723B1 - Class d amplification circuit - Google Patents

Abstract

In the class-D amplifier circuit, distortion at the time of inputting a small signal is realized.

The up / down counter 70 outputs a signal in which the delay amount in the delay amount variable circuit 50 increases and a signal in which the delay amount decreases. The output of both of these signals is generally done alternately or complementarily. More specifically, it is possible to increase the delay amount step by step with the former, and decrease the delay amount step by step with the latter. In addition, accordingly, the width of the output pulses OutP and OutM increases in steps or decreases in steps.

Class-D amplifier, up / down counter, delay variable circuit

Description

Class D amplifier circuit {CLASS D AMPLIFICATION CIRCUIT}

The present invention relates to a class-D amplifier circuit, and more particularly, to a class-D amplifier circuit capable of realizing distortion reduction at the time of inputting a small signal.

The class D amplifying circuit converts an input signal into a pulse width modulated signal having a constant amplitude to power amplify the pulse width modulated signal, and is used for power amplification of an audio signal, for example. Since the class D amplifier circuit operates with two values, it is possible to realize high efficiency by drastically reducing the loss of the transistor.

This class D amplifier circuit includes an integration circuit for integrating an input signal, a comparison circuit for comparing the output signal of the integration circuit with a predetermined triangle wave signal, and a pulse width amplifier for amplifying the output signal of the comparison circuit and outputting a pulse signal. And an output signal of the pulse width amplifier is fed back to the input side of the integrating circuit. The output signal of the pulse width amplifier becomes an analog signal for driving a load such as a speaker through a low pass filter made of a coil, a condenser, and the like. Recently, a filterless class D amplifier circuit in which a low pass filter has been omitted has also been put into practical use.

As described in Patent Literature 1, in the class D amplification circuit, a differential input method and a delay circuit are used to output the output pulses at the time of no signal in order to avoid power loss at the time of no signal and to prevent distortion at the time of the small signal. It is done to make duty ratio a few percent. FIG. 5 is a block diagram showing such a class D amplifier circuit 200. As shown in FIG. For the sake of convenience, only main parts are shown in this drawing, and a feedback circuit, an integration circuit, and the like are omitted. The class-D amplifier circuit 200 uses the triangular wave and the comparator 12a, 12b which the triangular wave generator circuit 20 outputs the input signal Vi + of the positive input terminal and the input signal Vi- of the negative input terminal, respectively. By comparison, the input signal is pulse width modulated.

Here, at the time of no signal input, as shown in FIG. 6, both the output signal A of the comparator 12a and the output signal B of the comparator 12b become a pulse of 50% of duty ratio. When these pulses are logically operated by a circuit composed of inverters 13a and 13b and NAND circuits 14a and 14b, the output signal of the positive output terminal OutP and the output signal of the negative output terminal via the output terminal circuit 40 are performed. OutM together eliminates pulse output when no signal is input. Thereby, the power loss at the time of no signal input can be reduced.

However, in general, a dead band occurs near the input crossover due to the accuracy of the comparator 12, the input / output characteristics of the output terminal circuit 40, or the like, so that the pulse signal output is lost or distorted at the time of no signal or minute signal input. Therefore, in the class-D amplifier circuit 200 of this example, the signal Bd is generated by using the delay circuit 30 of the delay amount W. FIG. Accordingly, as shown in Fig. 6, the pulse width W is output as the output signals OutP and OutM at the time of no signal, so that the modulation width at the time of inputting the small signal can be accurately reflected and the distortion can be reduced. have.

Patent Document 1: Japanese Patent Laid-Open No. 2006-42296

As described above, by outputting the pulse of width W at the time of no signal input, it is possible to surely reduce the distortion at the time of the minute signal input. However, only the countermeasure by the installation of the delay circuit 30 cannot completely exclude the influence of the dead band and the like near the input crossover described above. The case where the level of the input signal Vi + gradually rises above the amplitude center level will be described in detail.

First, as shown in Fig. 6, when the signal, i.e., the level of the input signal Vi + is the amplitude center level, the pulse of width W is output as the output signal OutP and the output signal OutM.

Next, when the level of the input signal Vi + rises only slightly from the amplitude center level, as shown in the microsignal of Fig. 6, the pulse width of the output signal OutM becomes slightly larger while the pulse of the output signal OutP is increased. The width is slightly smaller.

Next, when the level of the input signal Vi + rises further to reach the predetermined level, the pulse width of the output signal OutP becomes zero. This is because a plurality of inverters whose input capacitance gradually increases are connected in series to form an output terminal circuit 40. In other words, the transmission waveform becomes dull due to the input capacitance of the inverter. However, when the pulse width becomes narrower, the pulse voltage cannot be transmitted because the threshold voltage of the inverter cannot be exceeded. When the minimum pulse width that can be transmitted is set as the minimum pulse width Wmin, if the pulse width of the output signal of the NAND circuit 14b becomes less than or equal to Wmin, the output signal OutP always becomes a low level.

That is, according to the prior art, although the dead band at the time of the minute signal can be eliminated, there is a problem that the dead band near the predetermined level generated by the output terminal circuit 40 cannot be eliminated and distortion occurs.

This invention is made | formed in view of such a situation, and makes it a subject to reduce the distortion resulting from a dead band in a class-D amplifier circuit.

In order to solve the above problems, a class-D amplifier circuit according to the present invention includes pulse width modulation means for generating a first signal and a second signal by pulse width modulating an input signal, and generating a delayed second signal by delaying the second signal. And a delay means capable of controlling a delay time, an output pulse generation means for generating a first output pulse signal and a second output pulse signal that are externally output based on the first signal and the delay second signal, and the first Adjusting means for adjusting the pulse width of the output pulse signal and the second output pulse signal to have a predetermined width, wherein the adjusting means selects two or more of a predetermined delay time of N kinds (N is an integer of 2 or more) And delay time control means for controlling the delay time of the delay means to be different.

According to the present invention, the delay time is controlled by selecting two or more delay times among the N kinds of delay times, and as a result, the pulse width is adjusted to a predetermined width, so that the occurrence of a state in which the output pulse disappears is greatly suppressed. Therefore, distortion reduction at the time of inputting a small signal can be realized.

More specifically, the N types of delay times are different lengths [n (1), n (2),... , n (N) {n (1) <n (2) <.. <n (N)}], and the delay time controlling means comprises: n (1), n (2),... It is preferable to control the delay time of the delay means by selecting delay times having n (N) in this order.

According to the present invention, the delay time is controlled through the selection of various delay times ranging from shorter delay times to longer delay times, so that the adjustment of the pulse width can be performed in a comprehensive manner. Therefore, the distortion reduction effect at the time of inputting a small signal can be more effectively enjoyed.

Further, the delay time controlling means selects the delay time n (N-1), n (N-2),... After selecting the delay time having n (N). It is preferable to control the delay time of the delay means by selecting delay times having n (1) in this order.

In this case, the selection of the delay time is shorter to longer in sequence, followed by sequentially shorter, that is, in an emotional order, so that the specific configuration of the delay time control means can be made simpler. .

In addition, since the comprehensive adjustment of the pulse width is performed more suitably, the distortion reduction effect at the time of inputting a small signal can be more effectively received.

Further, the delay time controlling means selects the delay time having n (N), and then the n (1), n (2),... It is preferable to control the delay time of the delay means by selecting delay times having n (N) in this order.

In this case, the selection of the delay time can be made simpler by setting the delay time from the shorter to the longer one and then from the shorter to the longer one in the order of emotion.

In addition, since the overall adjustment of the pulse width is made more suitably, the effect of reducing distortion at the time of inputting a small signal can be more effectively received.

Embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram showing the configuration of a class-D amplifier circuit 100 according to the present embodiment. The same code | symbol is attached | subjected to the component similar to FIG.

As shown in the figure, the class D amplifier circuit 100 includes a positive input terminal and a negative input terminal, and a positive output terminal and a negative output terminal. The input signal Vin + is supplied to the positive input terminal, and the input signal Vin- is supplied to the negative input terminal. The pulse width modulated signal OutP is output from the positive output terminal, and the pulse width modulated signal OutM is output from the negative output terminal. That is, the input signal Vin is given in differential input format. The pulse width modulated signals OutP and OutM are connected to a load such as a speaker not shown. As a result, the load of the speaker or the like is operated by the difference signal between OutP and OutM. In addition, in this embodiment, although it is set as the filterless type D amplifier circuit which connects a load without using a low pass filter, it is good also as a general structure which connects a load via a low pass filter.

The class D amplifier circuit 100 includes a PWM signal generator X1 including resistors R1 to R6, capacitors C1 to C4, operational amplifiers 11, comparators 12a and 12b, and triangle wave generator circuit 20. A logic circuit section X2 composed of inverters 13a and 13b and NAND circuits 14a and 14b, and an adjusting section including an output stage circuit 40, a delay amount variable circuit 50 and an up / down counter 70 ( X3).

In the PWM signal generator X1, the input signal Vin + is supplied to the plus input terminal of the operational amplifier 11 through the resistor R1, and the feedback signal is supplied through the resistor R3. On the other hand, the input signal Vin- is supplied to the negative input terminal of the operational amplifier 11 through the resistor R2, and the feedback signal is supplied through the resistor R4. A T-type secondary differential circuit is provided between the positive output terminal and the negative input terminal of the operational amplifier 11 and between the negative output terminal and the positive input terminal, respectively. The differential circuit between the negative output terminal and the positive input terminal of the operational amplifier 11 is composed of the capacitors C1 and C3 and a resistor R5 provided between their connection point and ground. In addition, the differential circuit between the positive output terminal and the negative input terminal of the operational amplifier 11 is composed of the capacitors C2 and C4 and a resistor R6 provided between their connection point and ground. Since each differential circuit is provided in the feedback loop of the operational amplifier 11, the operational amplifier consisting of the operational amplifier and the differential circuit functions as an integrated circuit for synthesizing the input signal Vin and the feedback signal and performing secondary integration on it. To output the integral signal.

The triangular wave generating circuit 20 generates a triangular wave signal having a constant amplitude. The frequency of the triangle wave signal is set higher than the frequency of the input signal Vin. The highest frequency of the input signal Vin of this example is 20 Hz, and the frequency of the triangular wave signal is 200 Hz. In addition, the spectrum of the triangular wave signal may be diffused from the viewpoint of reducing unnecessary electron radiation.

The PWM signal generator X1 generates a pulse width modulated signal A and a signal B based on the triangular wave signal and the integrated signal. Here, the comparators 12a and 12b output a high level when the level of the integrated signal exceeds the level of the triangular wave signal, and outputs a low level when the level of the integrated signal falls below the level of the triangular wave signal.

The delay amount variable circuit 50 delays the output B to generate the output Bd. The delay amount variable circuit 50 can change the delay amount by the control signal CTL from the up / down counter 70.

2 is a block diagram showing an example of the configuration of the delay amount variable circuit 50 and the up / down counter 70. The up / down counter 70 counts clock signals (not shown) to increase the count value when the up signal is activated, and decrease the count value when the down signal is activated. The up / down counter 70 also outputs to the delay amount variable circuit 50 a control signal CTL of n (n is a natural number of two or more) bits representing a count value.

Each of the above-described up signal and down signal is complementarily active and non-active according to a predetermined criterion. Here, predetermined criteria are as follows, for example. That is, the up signal is active and the down signal is non-active during the period of K (K is a natural number of 2 or more) period of the first carrier signal, but the up signal is non-active during the K-1 period of the subsequent carrier signal. The down signal is active. Thereafter, these two states are repeated.

This switching will be described later how the class D amplifier circuit 100 according to the present embodiment operates.

The delay amount variable circuit 50 includes an inverter Inv10, a capacitor C11, an inverter Inv11, a constant current circuit 51, and a selection circuit 52 composed of TrP1 to TrP4 and TrN1 to TrN3. The inverter Inv10 charges and discharges the capacitor C11, but the magnitude of the driving current is determined by the current flowing through the transistor TrP1. As the drive current increases, the charge / discharge time of the capacitor C11 is shortened, so the delay time of the delay amount variable circuit 50 is shortened. On the other hand, when the drive current decreases, the charge / discharge time of the capacitor C11 becomes long, so the delay time of the delay amount variable circuit 50 becomes long.

The constant current circuit 51 and the selection circuit 52 have a function of adjusting the amount of current flowing through the transistor TrP1. The constant current circuit 51 has n constant current sources 51-1, 51-2, ... 51-n, and the selection circuit 52 is provided with n switches SW1, SW2, ... SWn. The n-bit control signal CTL controls on / off of the n switches SW1 to SWn, respectively. In this example, the current amounts of the constant current sources 51-1, 51-2, ... 51-n are set to be larger as the number of subscripts increases. The larger the count value of the up / down counter 70 is, the smaller the amount of current is selected from the constant current sources 51-1 to 51-n. The smaller the count value of the up / down counter 70 is, the more the constant current source 51-1 is. The control signal CTL controls the switches SW1 to SWn so as to select the large current amount from ˜51-n.

In addition, the structure of the delay amount variable circuit 50 is an example, and in this invention, the delay amount variable circuit by various structures which can switch a delay amount by the count value of the up-down counter 70 can be used.

The description returns to FIG. 1. The output A and the output Bd which delayed the output B by the delay amount variable circuit 50 are input to the logic circuit part X2, and the inversion signal of the output A and the NAND of the output Bd are input. A NAND output signal of the output signal and the inverted signals of the outputs A and Bd is generated. The difference of this output signal drives an external load such as a speaker. The output stage circuit 40 is comprised by connecting an inverter buffer in multiple stages.

By the above structure, the following operation is performed in this embodiment. In addition, below, when n in FIG. 2 is 3 for simplicity and clarity, ie, when the amount of delay can take three kinds of values of "small", "medium" and "large" relatively. A description will be made on the premise of this. In this case, K mentioned above becomes "3".

First, the up / down counter 70 receives an input of an up signal activated in a period of three periods of a carrier signal (down signal is non-active in that period). Therefore, the count value continues to increase step by step according to the number of clock signals input to the up / down counter 70. The up / down counter 70 also outputs a signal in which the delay amount in the delay amount variable circuit 50 increases.

As a result, the delay amount continues to increase in steps, and the pulse width also increases in steps.

In this case, the output pulses OutP and OutM are as shown in the first half of FIG. 3, for example. That is, the delay amount gradually increases in the small, medium, and middle directions, and the pulse width also gradually increases.

Next, the up / down counter 70 receives an input of an activated down signal in a period of two cycles of the next carrier signal (up signal is non-active in that period). Therefore, the count value continues to decrease step by step. The up / down counter 70 also outputs a signal in which the delay amount in the delay amount variable circuit 50 decreases.

Accordingly, the delay amount continues to decrease step by step, and the pulse width also continues to decrease step by step.

In this case, the output pulses OutP and OutM are as shown in the second half of FIG. 3, for example. That is, the delay amount gradually decreases from the above "large" state to medium and small, and the pulse width also gradually decreases.

After that, the above two operations are repeated. That is, the up / down counter 70 receives an active up signal or a down signal at each time interval T, whereby the delay amounts are small, medium, large, medium, small, medium, as shown in FIG. versus,… The transition between the three values is repeated sequentially. As a result, the pulse width eventually increases or decreases step by step as shown in FIG.

In the class D amplifying circuit 100 according to the present embodiment, the above operation is performed, so that the time for the output pulses OutP and OutM disappears can be made very short, and the occurrence of distortion in the minute input signal can be suppressed. have.

This becomes clearer by contrast with this embodiment and the case where the delay amount is unchanged. 4 shows examples of output pulses OutP and OutM in this case. In this case, the delay amount continues to take a constant value throughout the period. However, since there is a dead band near the predetermined level by the output terminal circuit 40, the output pulse disappears when the input signal is in the dead band. In Fig. 4, an example in which a pulse having a width less than or equal to the width Wmin is impossible due to the influence of the dead band or the like is output where a pulse having a width W1 is logically outputted.

In this way, the occurrence of distortion cannot be suppressed in the vicinity of the predetermined level.

In contrast, in the present embodiment, as described above, there is a very low possibility that such a problem may occur. For example, if the widths of the pulses P1 and P2 shown at both ends in FIG. 3 are smaller than the above-mentioned Wmin, the corresponding pulses P1 and P2 are also not outputted. In FIG. 3, both pulses P1 and P2 are not output. Since three pulses having a larger delay amount, i.e., a larger width, are inserted in P2), the output pulses do not completely disappear during the period.

In addition, when five pulses of different widths in FIG. 3 are considered as one integrated, pulses having a width obtained by averaging these pulse widths (hereinafter, referred to as "average width") are output in this period. can see. And, this average width may generally be smaller than the minimum value Wmin. In other words, in this aspect, it can be said that an output pulse exceeding the limit of the minimum value Wmin can be obtained.

As described above, in this embodiment, the time for eliminating the output pulses OutP and OutM can be made very short.

In addition, the said embodiment only shows an example of the class D amplifier circuit which concerns on this invention, and various modifications are possible. For example, in the above embodiment, the amount of delay is small, medium, large, medium, small, medium, large, ... by the action of the up / down counter 70. Are sequentially repeated (see FIG. 3), but in the present invention, small, medium, large, small, medium, large, small,... As described above, after the delay amount reaches the maximum value, the operation of sequentially returning to the minimum value may be adopted. In this case, the "reset signal" (not shown) which resets the count value of the up-down counter 70 may be used instead of the "down signal" in the above embodiment. For example, the count value of the up / down counter 70 is gradually increased by the input of the up signal for a predetermined time, and then returns to the initial value by the input of the reset signal.

In any case, in the case where the delay amount is repeatedly increased or decreased in a certain emotional manner, the specific configurations of the delay amount variable circuit 50 and the up / down counter 70 are configured more simply than in the case where the delay amount is repeated. You can get the advantage that you can.

However, in some cases, the amount of delay is more variably (for example, the form of repeating small, large, medium, small, large, medium, ..., and also the form of randomly and randomly changing). You may also have. The present invention also puts such a form within the scope.

In the above embodiment, n in Fig. 2 is "3", but the present invention is not naturally limited in this respect as well. In addition, the n should be 2 or more, but in the case of 3 or more, As described above, the increase or decrease is preferably performed in a form from small to sequentially increasing (or vice versa), whereby the adjustment of the pulse width is performed in a comprehensive manner so that the output pulses OutP and OutM This is because the effect of shortening the time for which the time lapses becomes very easy to be obtained more effectively.

1 is a block diagram showing the configuration of a class-D amplifier circuit 100 according to the present embodiment.

2 is a block diagram showing an example of the configuration of a delay amount variable circuit and an up / down counter.

3 is a diagram illustrating an example of an output pulse according to the class D amplifier circuit 100 according to the present embodiment.

4 is a diagram showing an example of an output pulse in the case where the up / down counter 70 of FIG. 1 does not exist and the delay amount is invariant.

Fig. 5 is a block diagram showing the structure of a conventional class D amplifier circuit using a delay circuit.

Fig. 6 is a diagram showing output pulses at the time of no signal input and at the time of small signal input.

<Explanation of symbols for main parts of the drawings>

11: operational amplifier 12a, 12b: comparator

20: triangle wave generator circuit 40: output stage circuit

50: variable delay circuit 70: up / down counter

100: Class D amplifier circuit X1: PWM signal generator

X2: logic circuit section X3: adjusting section

Claims (4)

Pulse width modulation means for pulse width modulating the input signal to produce a first signal and a second signal; Delay means for delaying said second signal to produce a delayed second signal and controlling a delay time; Output pulse generation means for generating a first output pulse signal and a second output pulse signal output to the outside based on the first signal and the delay second signal; And Adjusting means for adjusting a pulse width of said first output pulse signal and said second output pulse signal to a predetermined width: The adjusting means, And a delay time control means for controlling the delay time of the delay means to be different by repeatedly selecting a predetermined delay time of N kinds (N is an integer of 2 or more) in a predetermined order. The method of claim 1, The N types of delay times are different lengths [n (1), n (2),... , n (N) {n (1) <n (2) <.. includes a delay time with <n (N)}]; The delay time control means, N (1), n (2),... delay times with n (N), n (1), n (2),... , n (N), n (N-1), n (N-2),... A delay class of the delay means is controlled by selecting delay times in the order of n (2), and repeating the selection of this order. The method of claim 1, The N types of delay times are different lengths [n (1), n (2),... , n (N) {n (1) <n (2) <.. includes a delay time with <n (N)}]; The delay time control means, N (1), n (2),... delay times with n (N), n (1), n (2),... The class D amplifier circuit is characterized by controlling the delay time of the delay means by selecting the delay time in the order of n (N) and repeating the selection of this order. delete

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