CN107306117B

CN107306117B - Quaternary/ternary modulation selection circuit

Info

Publication number: CN107306117B
Application number: CN201610255432.6A
Authority: CN
Inventors: 吴顺达
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2016-04-22
Filing date: 2016-04-22
Publication date: 2020-11-27
Anticipated expiration: 2036-04-22
Also published as: CN107306117A

Abstract

A quaternary/ternary modulation selection circuit of an audio amplifier comprises a quaternary signal generating circuit and a ternary signal generating circuit, wherein the quaternary signal generating circuit is used for receiving an analog input signal to generate a quaternary signal, and the analog input signal comprises a forward input signal and a reverse input signal which are mutually complementary; the ternary signal generating circuit is used for generating a ternary signal according to the quaternary signal, wherein the ternary signal comprises a forward ternary wave and a reverse ternary wave; when the amplitude difference between the forward input signal and the reverse input signal is within a predetermined range around zero amplitude, the waveform of the forward ternary wave generated by the ternary signal generating circuit is equal to the waveform of the reverse ternary wave generated by the ternary signal generating circuit.

Description

Quaternary/ternary modulation selection circuit

Technical Field

The present invention relates to an audio amplifier, and more particularly, to a quaternary/ternary modulation selection circuit for an audio amplifier.

Background

The efficiency of the audio amplifier is a most important component of an audio system, and since the output waveform of the class D power amplifier is a modulated signal between two voltage levels (i.e., the supply voltage and the ground) rather than a generally linear waveform, ideally no current flows when the transistors of the output stage are turned on, so that the class D power amplifier has higher efficiency than other kinds of amplifiers, and is the most commonly used amplifier at present. The Modulation method generally applied to the class D power amplifier is Pulse Width Modulation (PWM), wherein the quaternary Modulation has the advantages of better Total Harmonic Distortion (THD), lower noise, easier operation under low power condition, and the like; ternary modulation has the advantages of better performance, better electromagnetic Interference (EMI) effect, and easier operation under low power conditions, so a quaternary/ternary modulation selection circuit that combines the above advantages becomes the most common architecture at present. However, when an audio amplifier has no input signal or the input signal is very small, there will be pulses with very short duty cycle (duty cycle) at the output terminal to cause power loss, and the circuit cannot detect the pulses, so there is a need for a quad/tri modulation selection circuit design that can solve the above power loss and distortion problem without input signal.

Disclosure of Invention

One objective of the present invention is to disclose a quadric/ternary modulation selection circuit of an audio amplifier and a related method.

According to an embodiment of the present invention, a quaternary/ternary modulation selection circuit applied to an audio amplifier is disclosed, the quaternary/ternary modulation selection circuit comprising: the four-element signal generating circuit is used for receiving an analog input signal to generate a four-element signal, wherein the analog input signal is provided with a forward input signal and a reverse input signal which are mutually complementary, and the four-element signal is provided with a forward four-element wave and a reverse four-element wave which are mutually complementary; the ternary signal generating circuit generates a ternary signal according to the quaternary signal, wherein the ternary signal comprises a forward ternary wave and a reverse ternary wave; when the amplitude difference between the forward input signal and the reverse input signal is within a preset range, a signal waveform of the forward ternary wave generated by the ternary signal generating circuit is the same as a signal waveform of the reverse ternary wave generated by the ternary signal generating circuit.

According to an embodiment of the present invention, a quaternary/ternary modulation selection method applied to an audio amplifier is disclosed, comprising: receiving an analog input signal to generate a quaternary signal, wherein the analog input signal has a forward input signal and a reverse input signal which are complementary to each other, and the quaternary signal has a forward quaternary signal and a reverse quaternary signal which are complementary to each other; generating a ternary signal according to the quaternary signal, wherein the ternary signal comprises a forward ternary wave and a reverse ternary wave; when the amplitude difference between the forward input signal and the reverse input signal is within a preset range, a signal waveform of the forward ternary wave generated by the ternary signal generating circuit is the same as a signal waveform of the reverse ternary wave generated by the ternary signal generating circuit.

Drawings

Fig. 1 is a schematic diagram of an audio amplifier having a quad/tri modulation selection circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a quad/tri modulation selection circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a ternary signal generating circuit according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of a ternary signal according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a pulse generation circuit according to an embodiment of the invention.

FIG. 6 is a signal diagram of a pulse generation circuit that generates two quad/tri-modulation selection circuits with 25% duty cycle pulses according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of the signals output by the quad/tri-ary modulation selection circuit after inserting two pulses with 25% duty cycle according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a detection circuit and a pulse generation circuit according to another embodiment of the invention.

Fig. 9 is a schematic diagram of the current suppressed by a plurality of pulses having a duty cycle of about 25% after an overcurrent is detected according to an embodiment of the present invention.

List of reference numerals

100 audio amplifier

110 gain stage

102 quaternary/ternary detection circuit

101 quaternary/ternary selection circuit

130 output stage

R1, R2 resistance

120 integrator

VIP and VIN analog input signal

OUTP, OUTN output signals

130 output stage

161. 162 filter

210 quaternary signal generating circuit

2101. 2102, 450 comparator

QP forward quad wave

QN reverse quad-wave

240 first selection circuit

2041. 2042, 2501, 2502 multiplexers

250 second selection circuit

220 ternary signal generating circuit

230 pulse generating circuit

2301. 7021 fixed duty cycle pulse generator

2302. 7022 counter circuit

Signals S2, S1, P1

301 delay circuit

302 generating unit

3011 first delay unit

3012 second delay unit

3021 first generation unit

3022 second generation unit

XOR1 and XOR2 exclusive-OR gate

DP ', DN' delayed signal

AND1, AND2, 4702, 4703, 4601 AND gate

4605. 4701 reverser

4602. 4603, 4704D type flip-flop

701 detection circuit

702 pulse generating circuit

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct or indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1 is a schematic diagram of an audio amplifier 100 having a quad/ternary modulation selection circuit 101 according to an embodiment of the present invention, in which the audio amplifier 100 is a class D amplifier, and the audio amplifier 100 includes a gain stage 110, an integrator 120, the quad/ternary modulation selection circuit 101, a quad/ternary detection circuit 102, an output stage 130, two feedback resistors R1 and R2, and two

filters

161 and 162, wherein the quad/ternary modulation selection circuit 101 is configured to select one of a quad signal, a ternary signal, and at least one pulse with a limited duty cycle, and the quad/ternary detection circuit 102 is configured to detect the output signals Vop and Von of the gain stage 110, and transmit a signal S2 to the quad/ternary modulation selection circuit 101 according to the output signals Vop and Von of the gain stage 110 to determine which signal should be output to the output stage 130 through the quad/ternary modulation selection circuit 101 The remaining components of the audio amplifier 100 are similar to the corresponding components of the conventional class-D power amplifier, and the detailed description is omitted herein for brevity since the skilled person will understand the functions thereof.

Fig. 2 is a schematic diagram of the quaternary/ternary modulation selection circuit 101 according to an embodiment of the present invention, and as shown in fig. 2, the quaternary/ternary modulation selection circuit 101 includes a quaternary signal generation circuit 210, a ternary signal generation circuit 220, and a pulse generation circuit 230. The quaternary signal generating circuit 210 is configured to receive the analog input signals VIP and VIN that are complementary to each other, wherein the quaternary signal generating circuit 210 coupled to the integrator 120 shown in fig. 1 includes two

comparators

2101 and 2102 for comparing the output signal of the integrator 120 with a triangular wave to generate a quaternary signal, wherein the quaternary signal includes a forward quaternary wave QP and a backward quaternary wave QN that are complementary to each other. The ternary signal generating circuit 220 is coupled to the quaternary signal generating circuit 210, and generates a ternary signal according to the forward quaternary wave QP and the backward quaternary wave QN, wherein the ternary signal includes a forward ternary wave TP and a backward ternary wave TN. The pulse generating circuit 230 includes a fixed duty cycle pulse generator 2301 and a counting circuit 2302, in which the fixed duty cycle pulse generator 2301 is used for generating a signal P1 including two pulses with 25% duty cycle according to the signal S2 to suppress an inrush current (inrush current); the counting circuit 2302 is used for receiving two pulses with a duty cycle of 25% and transmitting a signal S1. A detailed description of the pulse generating circuit 230 will be discussed in subsequent paragraphs.

The above-described inrush current normally occurs in consecutive pulses that are initiated when the quaternary/ternary modulation selection circuit 101 switches from the ternary modulation mode to the quaternary modulation mode and when the audio amplifier 100 is just started, and therefore, in this embodiment, the plurality of pulses with a fixed duty ratio are two pulses with a duty ratio of 25%, where the two pulses with a duty ratio of 25% are inserted before the quaternary signal is ready to be generated when the audio amplifier 100 is started or when the quaternary modulation enters quaternary modulation by the quaternary modulation to suppress the inrush current.

The four/three modulation selection circuit 101 further comprises a first selection circuit 240 and a second selection circuit 250, wherein the first selection circuit 240 comprises

multiplexers

2401 and 2402, wherein the

multiplexers

2401 and 2402 select one of the signal P1 and the four-element signal according to the signal S1 transmitted by the counting circuit 2302 of the pulse generation circuit 230, wherein the signal P1 comprises two pulses with 25% duty cycle, and the second selection circuit 250 comprises

multiplexers

2501 and 2502, wherein the

multiplexers

2501 and 2502 select one of the signal (i.e., the signal P1 or the four-element signal) selected by the first selection circuit 240 and the three-element signal to the output stage 130 according to the signal S2.

Fig. 3 is a schematic diagram of a ternary signal generating circuit according to an embodiment of the present invention, as shown in fig. 3, the ternary signal generating circuit 220 includes a delay circuit 301 And a generating unit 302, wherein the delay circuit 301 includes a first delay unit 3011 And a second delay unit 3012 for delaying the forward quaternary wave QP And the backward quaternary wave QN to generate a delayed signal DP And a delayed signal DN, respectively, And the generating unit 302 includes a first generating unit 3021 And a second generating unit 3022, wherein the first generating unit 3021 is configured to generate the forward ternary wave TP according to the delayed signal DN And the forward quaternary wave QP, And the second generating unit 3022 is configured to generate the backward ternary wave TN according to the delayed signal DP And the backward quaternary wave QN, in this embodiment, as shown in fig. 3, the first generating unit 3021 may be implemented by an exclusive or gate (XOR gate) 1 And an And gate (And gate) 1, the exclusive or gate XOR1 receives the delayed signal DN AND the forward quad-wave QP to generate a signal DP ', AND the AND gate AND1 receives the signal DP' AND the forward quad-wave QP to generate the forward tri-wave TP. Similarly, the second generating unit 3022 may be implemented by an exclusive or gate XOR2 AND an AND gate AND2, wherein the exclusive or gate XOR2 receives the delayed signal DP AND the inverse quad-wave QN to generate a signal DN ', AND the AND gate AND2 receives the signal DN' AND the inverse quad-wave QN to generate the inverse quad-wave TN. It should be noted that the above examples of implementing the first generating unit 3021 and the second generating unit 3022 are only illustrative and not intended to limit the present invention, and in other embodiments, the first generating unit 3021 and the second generating unit 3022 may be implemented by other logic gates as long as the purpose of the embodiment of fig. 3 can be achieved.

Fig. 4 is a waveform diagram of the ternary signal generating circuit 220 in fig. 3, as shown in diagram (a) of fig. 4, when the amplitude difference of the analog input signals complementary to each other of the audio amplifiers 100 or the amplitude difference of the analog input signals VIP and VIN complementary to each other of the quaternary/ternary modulation selecting circuit 101 is within a predetermined range (i.e., ± 1% of zero amplitude) above and below zero amplitude (zero amplitude), the forward quaternary wave QP and the backward quaternary wave QN are two square waves having the same duty ratio (e.g., 50% as shown). The waveforms of the delayed signals DP and DN are slightly delayed by the forward quad-wave QP and the backward quad-wave QN, respectively, in this embodiment, since the amplitude of the analog input signal VIP (i.e. 0V) is equal to the amplitude of the analog input signal VIN (i.e. 0V), the phase difference between the delayed signal DP and the forward quad-wave QP is about 28.8 degrees, and thus, as shown in sub-diagram (a) of fig. 4, the forward quad-wave TP has a pulse with a duty cycle of 8%. Similarly, the inverted ternary wave TN also has pulses with a duty cycle of 8%, such that if the gain (VOUTP-VOUTN)/(VIP-VIN) is set to 1, the differential output signal of the amplifier 100 approaches within the predetermined range of zero amplitude. Since the pulse width of the signal TP is equal to the pulse width of the signal TN, which can effectively solve the problems of power loss and distortion mentioned in the prior art, it should be noted that the delay amount of the delayed signals DP and DN in the present embodiment is only an example and is not a limitation of the present invention, and in practice, the delay of the delayed signals DP and DN depends on the capability of the circuit. Sub-diagram (B) of fig. 4 is a waveform diagram of a ternary signal when the analog input signals of the amplifiers 100 complementary to each other are slightly boosted, that is, the amplitude difference of the analog input signals of the audio amplifiers 100 complementary to each other or the amplitude difference of the analog input signals VIP and VIN of the quaternary/ternary modulation selection circuit 101 complementary to each other is not within a predetermined range above or below zero amplitude. As shown in diagram (B) of fig. 4, when the amplitude difference between the complementary analog input signals VIP and VIN slightly increases to 0.5V, the duty cycle of the positive ternary wave TP also increases (13% as shown in fig. 4), and the duty cycle of the negative ternary wave TN decreases (3% as shown in fig. 4). Fig. 4, sub-diagram (C), is a waveform diagram of the ternary signal when the amplitude difference between VIP and VIN, which are complementary to each other, continues to increase to 3V, and the amplifier 100 operates in the normal ternary mode, and only one of the forward ternary wave TP and the backward ternary wave TN has a waveform (in this embodiment, the forward ternary wave TP is shown).

FIG. 5 is a schematic diagram of a pulse generator 230 according to an embodiment of the present invention, in which, as shown in FIG. 5, a fixed duty cycle pulse generator 2301 of the pulse generator 230 includes a comparator 450, an AND gate 4601, a D-type flip-flop 4604 and an inverter 4605, wherein the comparator 450 is used to compare the triangular wave with the 1/4 supply voltage VDD (i.e., VDD/4) to generate a clock signal CLK with a duty cycle of 25%, the input of the AND gate 4601 is coupled to an output of the D-type flip-flop 4604 and the clock signal CLK with a duty cycle of 25% generates a signal P1 at an output terminal, the D-type flip-flop 4604 serves as a latch (latch) to transmit the supply voltage VDD to one of the inputs of the AND gate 4601, and as shown in FIG. 5, the forward four-wave flip-flop circuit receives a trigger signal after being inverted by the inverter, and the counter circuit 2302 includes two counters 4602 and 4603, An inverter 4701, two and gates 4702 and 4703, and a D-type flip-flop 4704, wherein counters 4602 and 4603 for generating a signal Q2 are implemented by D-type flip-flops and are coupled between the input of the and gate 4601 and one input of the and gate 4702, and the other input of the and gate 4702 is coupled to an output of the inverter 4701, wherein the inverter 4701 is configured to invert the forward quad-wave QP, and the D-type flip-flop 4704 serves as a latch to receive a signal S3 generated by the and gate 4702 to generate a signal S1 to the first selection circuit 240, and in addition, the input of the and gate 4703 is coupled to the signal S2 and the power supply signal PS, and an output of the and gate 4703 is coupled to reset (reset) terminals of the D-type flip-flops 4602, 4603, and 4704 to reset the D-type flip-flops.

When the audio amplifier 100 is activated by power-on, the activation signal PS has a logic value of 1, and when the audio amplifier 100 enters the audio amplifier 100 and enters quaternary modulation from ternary modulation, the signal S2 has a logic value of 1, if one of the signals PS, S2 is a logic value 1, D-type flip-

flops

4602, 4603, 4604 and 4704 will be reset accordingly, the clock signal CLK with 25% duty cycle is then transmitted to the output of and gate 4601 (i.e., signal P1), and enters

counters

4602 and 4603 and first selection circuit 240, after the

counters

4602 and 4603 receive two pulses with a duty cycle of 25%, a signal Q2 with a logic value of 1 is generated according to the characteristics of the counter implemented by the D-type flip-flop, the logic value of the signal S1 output by the D-type flip-flop 4704 is therefore 1, the quaternary signal is output by the first selection circuit 240 and the second selection circuit 250, and the audio amplifier 100 enters the quaternary modulation mode. When the audio amplifier 100 is turned on or enters quaternary modulation from ternary modulation, the audio amplifier 100 outputs two pulses with a duty ratio of 25% before the quaternary signal, and thus, the overcurrent can be effectively suppressed.

Fig. 6 is a signal diagram of a pulse generating circuit 230 for generating two quaternary/ternary modulation selecting circuits 101 with 25% duty cycle according to an embodiment of the present invention, as shown in fig. 6, if the signal S2 is logic value 1, the signal P1 becomes a clock signal with 25% duty cycle, and the first selecting circuit 240 and the second selecting circuit 250 transmit the signal P1 to the output stage 130, the signal Q2 generated by the

counters

4602 and 4603 becomes logic value 1 after the

counters

4602 and 4603 receive two 25% duty cycle pulses, and the signal S1 also becomes logic value 1 and is transmitted to the first selecting circuit 240, the quaternary signal will be transmitted to the output stage 130, and the amplifier 100 thus operates in the quaternary modulation mode.

Fig. 7 is a schematic diagram of signals output by the four/three element modulation selection circuit after inserting two pulses with duty ratio of 25% according to an embodiment of the present invention, and fig. 7 is a schematic diagram of signals output by the four/three element modulation selection circuit 101 according to the embodiments of fig. 5 and 6, as shown in fig. 7, two pulses with duty ratio of 25% are inserted when the audio amplifier is just started or enters the four element modulation mode by three element modulation, so as to suppress overcurrent accordingly.

In another embodiment of the present invention, the pulse with a limited duty cycle (e.g. 25%) is not limited to be inserted only when the audio amplifier 100 is just started or enters the quaternary modulation mode from the ternary modulation mode, but may be inserted immediately when the inrush current occurs. Fig. 8 shows a detection circuit 701 and a pulse generation circuit 702 according to another embodiment of the present invention, in this embodiment, a detection circuit 701 for detecting surge current at any time and a modified pulse generation circuit 702 are added according to the architecture of the quad/ternary modulation selection circuit shown in fig. 2, wherein the detection circuit 701 is implemented by a comparator and is used for comparing the load current IL output by the output stage 203 with a default current C1. If the load current IL is stronger than the default current C1, i.e. it represents that an inrush current occurs, the detection circuit 701 generates a signal OC _ W to the pulse generation circuit 702, and after receiving the signal OC _ W, the pulse generation circuit generates a plurality of pulses with a duty ratio close to 25% to the output stage to suppress the inrush current, in this embodiment, the plurality of pulses with limited duty ratios are eight pulses with a duty ratio of 25%, but this is not a limitation of the present invention, and if the inrush current still exists after outputting eight pulses with a duty ratio of 25% to the counting circuit 7022, the signal S1_ OCW is generated to the output stage to turn off the output stage, so as to avoid damage to the audio amplifier 100.

Fig. 9 is a schematic diagram of the current suppressed by a plurality of pulses with a duty ratio of about 25% (for example, the output current of the audio amplifier 200 is greater than a predetermined value) after the overcurrent is detected according to an embodiment of the present invention, as shown in fig. 8, if the detection circuit 701 is provided, the overcurrent can be suppressed at any time, rather than the damage of the audio amplifier 100 caused by the continuous increase of the overcurrent.

In the embodiments of fig. 5 to 9, the number of pulses to be inserted and the duty ratio thereof are not limited, the number of pulses depends on the number of counters included in the

counting circuits

2302 and 7022, and different duty ratios can be easily obtained by comparing the triangular waves with different voltage values, and designs that can generate a plurality of pulse signals with duty ratios of about 25% to suppress the inrush current are all within the scope of the present invention. Similarly, the structure of the ternary signal generating circuit 220 is not limited as long as the structure can generate the forward ternary wave TP and the backward ternary wave TN as shown in FIG. 4. In addition, the structure of the pulse generating circuit 230 in fig. 5 is only for illustration and is not a limitation of the present invention, and these designs should fall within the scope of the present invention as long as the signals S1 and P1 can be generated as described above.

The above-described embodiments are merely exemplary embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims

1. A quad/ternary modulation selection circuit for an audio amplifier, comprising:

a quaternary signal generating circuit for receiving an analog input signal to generate a quaternary signal, wherein the analog input signal comprises a forward input signal and a reverse input signal which are complementary to each other, and the quaternary signal comprises a forward quaternary wave and a reverse quaternary wave which are complementary to each other; and

a ternary signal generating circuit for generating a ternary signal according to the quaternary signal, wherein the ternary signal comprises a forward ternary wave and a reverse ternary wave;

when the amplitude difference between the forward input signal and the reverse input signal is within a predetermined range around zero amplitude, a waveform of the forward ternary wave generated by the ternary signal generating circuit is equal to a waveform of the reverse ternary wave generated by the ternary signal generating circuit; and is

When the amplitude difference between the forward input signal and the reverse input signal is not within the predetermined range of about zero amplitude, the waveform of the forward ternary wave generated by the ternary signal generating circuit and the waveform of the reverse ternary wave generated by the ternary signal generating circuit do not change simultaneously.

2. The quadric/ternary modulation selection circuit according to claim 1, wherein when the difference in the amplitudes of the forward input signal and the reverse input signal is not within the predetermined range around zero amplitude, a duty cycle of one of the forward ternary wave and the reverse ternary wave is greater than a duty cycle of the other of the forward ternary wave and the reverse ternary wave.

3. The quadric/ternary modulation selection circuit of claim 1, wherein the ternary signal generation circuit comprises:

a delay circuit for delaying the quaternary signal to generate a delayed signal; and

a generating unit for generating the ternary signal according to the delayed signal and the quaternary signal.

4. The quadric/ternary modulation selection circuit of claim 3, wherein the delayed signal comprises a forward delayed signal and a reverse delayed signal generated by delaying the forward quad wave and the reverse quad wave, respectively, and the generation unit comprises:

a first generating unit for generating the forward ternary wave according to the forward quaternary wave and the reverse delayed signal;

a second generating unit for generating the reverse ternary wave according to the reverse quaternary wave and the forward delayed signal.

5. The quad/ternary modulation selection circuit of claim 1, further comprising:

a pulse generating circuit for generating a plurality of pulses having a finite duty cycle; and

a selection unit for selecting one of the quaternary signal, the ternary signal and the plurality of pulses to an output stage of the audio amplifier.

6. The quadric/ternary modulation selection circuit of claim 5, wherein the selection unit outputs at least one pulse of the plurality of pulses to the output stage of the audio amplifier when the audio amplifier is enabled.

7. The quadric/ternary modulation selection circuit of claim 5, wherein the selection unit outputs at least one of the plurality of pulses to the output stage of the audio amplifier when an output current of the audio amplifier is greater than a predetermined current.

8. The quadric/ternary modulation selection circuit of claim 5, wherein the selection unit comprises:

a first selection circuit for selectively outputting the pulses or the quaternary signal according to a first selection signal; and

a second selection circuit for selectively outputting the ternary signal or an output of the first selection circuit to the output stage according to a second selection signal.

9. The quad/ternary modulation selection circuit of claim 8, wherein the pulse generation circuit comprises:

a first comparator for comparing a triangular wave with a voltage source to generate the plurality of pulses;

a counting unit coupled to the first comparator, wherein when the selecting unit starts to output the plurality of pulses to the output stage, the counting unit counts a number of pulses output by the selecting unit; and

a control circuit, coupled to the counting unit, for generating the first selection signal to the first selection circuit to stop outputting the plurality of pulses when the number of pulses output by the selection unit exceeds a default number.

10. The quad/ternary modulation selection circuit of claim 5, wherein the finite duty cycle is 25%.