CN112886933B - Class D audio amplifier, adaptive pulse width adjusting method thereof and electronic equipment - Google Patents

Class D audio amplifier, adaptive pulse width adjusting method thereof and electronic equipment Download PDF

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CN112886933B
CN112886933B CN202110043842.5A CN202110043842A CN112886933B CN 112886933 B CN112886933 B CN 112886933B CN 202110043842 A CN202110043842 A CN 202110043842A CN 112886933 B CN112886933 B CN 112886933B
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signal
reference voltage
pulse width
output
input
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CN112886933A (en
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刘凯
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers

Abstract

The application discloses a class D audio amplifier, a pulse width adjusting method thereof and electronic equipment, wherein the class D audio amplifier comprises a pulse width modulation module, a pulse width modulation module and a pulse width modulation module, wherein the pulse width modulation module is used for outputting a first pulse width modulation signal and a second pulse width modulation signal, and the input signal comprises two paths of differential signals; the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal which are output to a load to form a corresponding first delay signal and a corresponding second delay signal; the driving module is used for generating a first output signal and a second output signal which are output to a load according to the first delay signal and the second delay signal; and the minimum delay control module is used for outputting a minimum delay control signal to the pulse width adjusting module according to the input signal of the input signal so as to control the minimum value of the relative delay amount. The D-class audio amplifier can improve the signal distortion problem.

Description

Class D audio amplifier, adaptive pulse width adjusting method thereof and electronic equipment
Technical Field
The application relates to the technical field of integrated circuits, in particular to a class-D audio amplifier, a self-adaptive pulse width adjusting method thereof and electronic equipment.
Background
Class D audio amplifiers are a commonly used high efficiency amplifier for amplifying audio signals, and in systems using class D amplifiers, an analog input signal is converted into a series of pulse modulated signals having different pulse widths to drive audio speakers.
The output of the class D audio amplifier is generally full-wave modulated, and usually has two output terminals connected to two ends of the load, respectively, and the two output terminal signals under the static output are both 50% duty ratio square wave signals. Considering that the power consumption is in positive correlation with the output duty ratio when the output voltage is applied to the LC load, the smaller the duty ratio is, the lower the power consumption is under the same condition, and therefore the 50% duty ratio output regulation mode is undoubtedly more power-consuming than the narrow pulse width output regulation mode. Because class D audio amplifier is widely used in electronic audio equipment such as cell-phone, smart audio amplifier, along with portable electronic audio equipment's popularization, also higher and higher to audio power amplifier's consumption requirement, consequently, the mode that reduces output pulse width is also more and more adopted in audio power amplifier.
The narrow pulse width is easy to disappear in the transmission process due to the deviation of the device process in the circuit, and especially under the condition of small signal input, the problems of bottom noise and distortion are easy to be caused when narrow pulse width modulation is adopted.
Therefore, how to keep the total harmonic distortion normal when performing narrow pulse width modulation is a problem to be solved urgently.
Disclosure of Invention
In view of this, the present application provides a class D audio amplifier, a method for adaptive pulse width adjustment thereof, and an electronic device, so as to ensure that total harmonic distortion is normal as much as possible when performing narrow pulse modulation.
The technical scheme of the invention provides a D-type audio amplifier, which comprises: the pulse width modulation module is used for performing pulse width modulation on an input signal and outputting a first pulse width modulation signal and a second pulse width modulation signal, wherein the input signal comprises two paths of differential signals; the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal which are output to a load to form a corresponding first delay signal and a corresponding second delay signal; the driving module is used for generating a first output signal and a second output signal which are output to a load according to a first delay signal and a second delay signal, and the pulse width of the first output signal and the pulse width of the second output signal are changed along with the relative delay amount; and the minimum delay control module is used for outputting a minimum delay control signal to the pulse width adjusting module according to the input signal of the input signal so as to control the minimum value of the relative delay amount.
Optionally, the minimum delay control module is configured to output a corresponding minimum delay control signal when the amplitudes of the two paths of signals in the input signal are both smaller than a first threshold, and control the minimum value to be T1; and/or when the amplitude of any one path of signal in the input signals is larger than or equal to a first threshold value, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2 and T2> T1.
Optionally, the minimum delay control module includes a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and outputting a corresponding minimum delay control signal according to a comparison result.
Optionally, the comparing unit includes a first comparator, a second comparator, a first nor gate, and a first not gate; two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, two positive input ends are respectively connected to two differential signals in the input signals, output ends are both connected to the input end of the first NOR gate, and the output end of the first NOR gate is connected to the input end of the first NOR gate.
Optionally, the reference unit is further configured to generate a first offset reference voltage corresponding to the first threshold, where the first offset reference voltage is greater than the first reference voltage; the comparison unit is used for controlling the subsequent input signals to be compared with the first reference voltage when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, and controlling the subsequent input signals to be compared with the first offset reference voltage when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage.
Optionally, the comparing unit further includes a first transmission gate and a second transmission gate; the input end of the first transmission gate is used for connecting the first reference voltage, the control end of the first transmission gate is connected to the output end of the first not gate, and the inverted control end of the first transmission gate is connected to the output end of the first not gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; wherein the first offset reference voltage corresponds to the first threshold and is greater than the first reference voltage.
Optionally, the minimum delay control module is further configured to control the minimum value to be T3 when the amplitudes of the two paths of signals in the input signal are both greater than a second threshold, where the second threshold is greater than the first threshold, and T3< T2.
Optionally, the minimum delay control module includes a reference generation unit and a comparison unit; the reference generation unit is used for simultaneously generating a first reference voltage corresponding to the first threshold and a second reference voltage corresponding to a second threshold; the comparison unit is used for comparing the input signal with the first reference voltage and the second reference voltage and outputting a corresponding minimum delay control signal according to a comparison result.
Optionally, the reference generating unit is further configured to generate a second offset reference voltage corresponding to a second threshold, where the second offset reference voltage is greater than the second reference voltage; the comparison unit is used for controlling the subsequent input signal to be compared with the second reference voltage when the amplitude of at least one path of signal in the input signals is gradually reduced from being larger than the second offset reference voltage, and controlling the subsequent input signal to be compared with the second offset reference voltage when the amplitude of at least one path of signal in the input signals is gradually increased from being smaller than the second reference voltage.
Optionally, the comparing unit further includes a first comparing path, a second comparing path, and an exclusive nor circuit; the first comparison path includes: the two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, the two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, the output ends of the first comparator and the second comparator are both connected to the input end of the first NOR gate, and the output end of the first NOR gate is connected to the input end of the first NOR gate; the second compare path includes: the two positive input ends of the third comparator and the fourth comparator are simultaneously connected to a second reference voltage, the two negative input ends of the third comparator and the fourth comparator are respectively connected to two differential signals in the input signals, the output ends of the third comparator and the fourth comparator are both connected to the input end of the second NOR gate, and the output end of the second NOR gate is connected to the input end of the second NOR gate; the output ends of the first NOT gate and the second NOT gate are connected to the input end of the XOR circuit, and the output end of the XOR circuit is used for outputting the minimum delay control signal.
Optionally, the first comparison path of the comparison unit further includes a first transmission gate and a second transmission gate, an input terminal of the first transmission gate is used for connecting the first reference voltage, a control terminal of the first transmission gate is connected to an output terminal of the first not gate, and an inverted control terminal of the first transmission gate is connected to an output terminal of the first nor gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; the second comparison path further comprises a third transmission gate and a fourth transmission gate, wherein the input end of the third transmission gate is used for being connected to the second reference voltage, the control end of the third transmission gate is connected to the output end of the second NOR gate, and the inverted control end of the third transmission gate is connected to the output end of the second NOR gate; the input end of the fourth transmission gate is used for being connected to a second offset reference voltage, the control end of the fourth transmission gate is connected to the output end of the second NOR gate, and the inverted control end of the fourth transmission gate is connected to the output end of the second NOR gate; wherein the first offset reference voltage corresponds to a first threshold and is greater than the first reference voltage; the second offset reference voltage corresponds to a second threshold and is greater than the second reference voltage.
Optionally, the pulse width adjusting module includes: the pulse width detection unit is used for detecting whether pulses exist in the first output signal and the second output signal or not and outputting corresponding pulse width control signals; and the delay control unit is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal on the basis of the minimum value according to the pulse width control signal.
The present application further provides a method for adaptive pulse width adjustment of a class D audio amplifier, comprising: performing pulse width modulation on an input signal to generate a first pulse width modulation signal and a second pulse width modulation signal; adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal output to a load to form a corresponding first delay signal and a second delay signal; generating a first output signal and a second output signal which are output to a load according to a first delay signal and a second delay signal, wherein the pulse width of the first output signal and the pulse width of the second output signal are changed along with the relative delay amount; wherein the minimum value of the relative delay amount is controlled according to the magnitude of the amplitude of the input signal.
Optionally, the method for controlling the minimum value of the relative delay amount according to the magnitude of the input signal further includes: when the amplitudes of the two paths of signals of the input signal are smaller than a first threshold value, controlling the minimum value to be T1; and when the amplitude of at least one path of signals of the input signals is larger than the first threshold value, controlling the minimum value to be T2, wherein T2 is greater than T1.
Optionally, the method for controlling the minimum value of the relative delay amount according to the magnitude of the input signal further includes: providing a first reference voltage corresponding to the first threshold, comparing the input signal with the first reference voltage; when the amplitudes of two paths of signals of the input signal are both smaller than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T1; and when the amplitude of at least one path of signal is greater than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2.
Optionally, the method for controlling the minimum value of the relative delay amount includes: providing a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; when the amplitude of at least one of the input signals is gradually reduced from being larger than the first offset reference voltage, the subsequent input signal is controlled to be compared with the first reference voltage, and when the amplitude of at least one of the input signals is gradually increased from being smaller than the first reference voltage, the subsequent input signal is controlled to be compared with the first offset reference voltage.
Optionally, the method for controlling the minimum value of the relative delay amount further includes: and when the amplitudes of the two paths of signals of the input signal are both larger than the second threshold value, controlling the minimum value to be T3, wherein the second threshold value is larger than the first threshold value, and T3 is less than T2.
Optionally, the method for controlling the minimum value of the relative delay amount includes: providing a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; comparing the input signal to the first and second reference voltages; when the amplitudes of the two paths of input signals are smaller than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T1; when the amplitude of at least one path of signal in the input signals is greater than or equal to the first reference voltage and smaller than the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2; and when the amplitudes of the two paths of signals of the input signal are both greater than or equal to the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T3.
Optionally, the method for controlling the minimum value of the relative delay amount further includes: providing a first offset reference voltage corresponding to the first threshold, a second offset reference voltage corresponding to the second threshold, the first offset reference voltage being greater than the first reference voltage, the second offset reference voltage being greater than the second reference voltage; when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, controlling the subsequent input signals to be compared with the first reference voltage; when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage, controlling the comparison between the subsequent input signals and the first offset reference voltage; and when the amplitude of at least one of the input signals is gradually increased from being smaller than the second reference voltage, the subsequent input signal is controlled to be compared with the second offset reference voltage.
Optionally, the method for adjusting the relative delay amount between the second pwm signal and the first pwm signal according to the first output signal and the second output signal output to the load includes: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not and outputting corresponding control signals; and adjusting the relative delay amount according to the control signal.
Optionally, the method for adjusting the relative delay amount further includes: and delaying the first pulse width modulation signal by a fixed amount to form the first delayed signal.
Optionally, the method for forming the first output signal and the second output signal includes: performing differential operation on the first delay signal and the second delay signal and outputting two paths of differential operation signals; and respectively carrying out power amplification on the two paths of differential operation signals to generate the first output signal and the second output signal.
The technical solution of the present invention also provides an electronic device, including: a class D audio amplifier as claimed in any preceding claim.
The class-D audio amplifier adjusts the minimum value of the relative delay amount according to the amplitude of the input signal, reasonably limits the minimum pulse width according to different input signal ranges, and avoids the problem of signal distortion caused by over-small pulse width in the narrow pulse width modulation process.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a class D audio amplifier according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a pulse width detection unit of a class D audio amplifier according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a delay control unit of a class D audio amplifier according to an embodiment of the present application;
FIG. 4a is a block diagram of a minimum delay control module according to an embodiment of the present application;
FIG. 4b is a schematic diagram of a comparing unit of the minimum delay control module according to an embodiment of the present application;
FIG. 5a is a block diagram of a minimum delay control module according to an embodiment of the present application;
FIG. 5b is a schematic diagram of a comparing unit of the minimum delay control module according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a comparing unit of a minimum delay control module according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a comparing unit of a minimum delay control module according to an embodiment of the present application;
FIGS. 8a and 8b are schematic signal waveforms of the output signal of the class D audio amplifier according to an embodiment of the present application in a static state;
FIG. 9 is a schematic diagram of a class D audio amplifier according to an embodiment of the present application;
FIG. 10 is a signal waveform diagram illustrating the output signal of the class D audio amplifier according to an embodiment of the present application in the quiescent state;
FIG. 11 is a schematic diagram of a fixed delay unit of a class D audio amplifier according to an embodiment of the present application;
fig. 12 is a flowchart illustrating an adaptive pulse width adjusting method according to an embodiment of the present application.
Detailed Description
As described in the prior art, the prior art reduces power consumption by simply reducing the pulse width during static operation, which causes problems of noise reduction and distortion, and particularly, in the case of small signal input, the pulse width is inherently small, and if the pulse width during static operation is reduced, the distortion is easy to cause larger signal distortion. Therefore, the inventor provides a new class-D audio amplifier and a pulse width adjusting method thereof, which can perform feedback adjustment on a pulse width according to the pulse width in an output signal output to a load, adaptively adjust the pulse width, reduce the pulse width of the output signal as much as possible, and avoid introducing additional problems of bottom noise, distortion and the like.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of a class D audio amplifier according to an embodiment of the present invention.
In this embodiment, the class D audio amplifier includes: a pulse width modulation module 110, a driving module 120, a pulse width adjustment module 130, and a minimum delay control module 140.
The pulse width modulation module 110 is configured to perform pulse width modulation on an input signal and output a first pulse width modulation signal and a second pulse width modulation signal. The input signal includes two analog differential signals VOP0 and VON0.
The pulse width modulation module 110 comprises an operational amplifier AMP and a capacitor C 1 ～C 6 Resistance R 1 ～R 8 And the comparators comp1 and comp2 are coupled to form an integrator. The operational amplifier AMP is used for amplifying the signal via a resistor R 1 And a resistance R 2 A pair of differential signals VOP0 and VON0 coupled to the two input terminals respectively perform an integration operation, and output two amplified signals. A T-type differential circuit is connected between the positive input end and the positive output end of the operational amplifier AMP, and comprises a capacitor C 1 、C 3 And a resistance R 3 ，C 1 And C 3 A resistor R connected in series between the positive input end and the positive output end of the operational amplifier AMP 3 Is connected to C 1 And C 3 Between the connection point of (a) and the ground. A T-shaped differential circuit is also connected between the negative input end and the negative output end of the operational amplifier AMP, and comprises a capacitor C 2 、C 4 And a resistance R 4 ，C 2 And C 4 A resistor R connected in series between the positive input end and the positive output end of the operational amplifier AMP 4 Is connected to C 2 And C 4 Between the connection point of (a) and the ground. A feedback loop structure is respectively formed between the two input ends of the operational amplifier AMP and the two output ends of the class D audio amplifier, and the feedback loop structures are respectively connected with feedback resistors R5-R8 and a feedback capacitor C 5 And C 6 Feedback resistance R 5 、R 6 And a feedback capacitor C 5 Forming a T-shaped feedback circuit, a feedback resistor R 7 、R 8 And a feedback capacitor C 6 The T-shaped feedback circuit is formed and has a filtering function so as to inhibit the influence on the input end when the modulated high-frequency square wave signal is fed back to the operational amplifier AMP through the feedback loop. The feedback loop structure may improve the quality of the output signal, but is not a necessary structure.
The pwm module 110 may further include a preceding stage amplifying module, which includes an amplifier, and is configured to differentially amplify an input preceding stage audio analog signal, such as a differential signal, and output the analog differential signals VOP0 and VON0, and then perform an integration operation through an operational amplifier AMP.
The comparator comp1 and the comparator comp2 are respectively configured to modulate two amplified signals output by the operational amplifier AMP, compare the two amplified signals with a modulation signal generated by the modulation signal generator 111, and respectively output a first pulse width modulation signal VO1 and a second pulse width modulation signal VO2. The modulation signal is typically a triangular wave, and a triangular wave of a specific frequency and level value may be generated as a modulation signal by the modulation signal generator 111. When the level of the amplified signal exceeds the signal level of the triangular wave, the comparator outputs a high level; when the level of the amplified signal is lower than the signal level of the triangular wave, the comparator outputs a low level, so that the first pulse width modulation signal VO1 and the second pulse width modulation signal VO2 which are output are both modulated square wave signals with a certain duty ratio. In other embodiments, the modulation signal may also be a waveform signal with a periodic rising and falling slope, such as a sawtooth wave or a sinusoidal half wave. The frequency of the modulation signal is usually 400KHz to 800KHz, which is much higher than the frequency of the signal to be modulated.
The pulse width adjusting module 130 is configured to control a relative delay amount between the second pulse width modulation signal VO2 and the first pulse width modulation signal VO1 according to a first output signal VOP and a second output signal VON output to a load, so as to form a second delay signal VO3. In this embodiment, the pwm module 130 only delays the second pwm signal VO2 by a delay amount T to form a second delayed signal VO3; if the delay amount of the first pwm signal VO1 is 0, the relative delay amount between VO3 and VO1 is the delay amount T.
The driving module 120 is coupled to the output terminals of the comparators comp1 and comp2, and is at least used for performing power amplification on the first pulse width modulation signal VO1 and the second delay signal VO3 to generate a first output signal VOP and a second output signal VON for applying to a load to drive the load. The pulse widths of the first output signal VOP and the second output signal VON vary with the relative delay amount between the second delayed signal VO3 and the first pulse width modulated signal VO 1.
In this embodiment, the driving module 120 includes a differential logic unit 121 and driving output units 122a and 122b; the differential logic unit 121 is configured to perform differential operation on the first pulse width modulation signal VO1 and the second delay signal VO3, and output two differential operation signals GTA and GTB; the differential operation signal GTA outputs the first output signal VOP through the driving output unit 122a, and the differential operation signal GTB outputs the second output signal VON through the driving output unit 122 b.
In one embodiment, the differential logic unit 121 includes a differential operation logic circuit for performing a differential operation on the input VO1 and VO3, and the differential logic unit 121 may employ a differential operational amplifier. In this embodiment, the differential operation is a NAND operation. The driving output units 122a and 122b respectively include one or more stages of power buffers. The specific implementation circuit structure of the differential logic unit 121 and the driving output units 122a and 122b can be selected by those skilled in the art according to actual requirements, and is not limited herein.
Specifically, the pulse width adjusting module 130 delays the second pulse modulation signal VO2 to form a second delayed signal VO3, and adjusts the pulse widths of the first output signal VOP and the second output signal VON by adjusting the delay amount. If the pulse width adjustment module 130 detects that neither the first output signal VOP nor the second output signal VON has pulses, that is, both signals are at low level, the pulse width adjustment module 130 is configured to increase the delay amount of the second delayed signal VO3 to increase the pulse widths of the first output signal VOP and the second output signal VON until one of the signals has pulses; if at least one of the two signals is detected to be high level, that is, any one signal has a pulse, reducing the delay amount of the second delay signal VO3, and reducing the pulse width of the first output signal VOP and the second output signal VON; therefore, the pulse widths of the first output signal VOP and the second output signal VON are always limited to be close to the minimum pulse width controlled by the minimum delay amount, the first output signal VOP and the second output signal VON are guaranteed to have pulse output, the problems of bottom noise and distortion are reduced, the pulse width can be reduced as much as possible, and the power consumption is reduced.
In addition, in this embodiment, the pulse width adjustment module 130 is configured to detect the first output signal VOP and the second output signal VON that are finally output to the load end by the class D audio amplifier, and the final output signal is not lost or eliminated by a dead zone of the output driving module before being applied to the load.
In this embodiment, the pulse width adjusting module 130 specifically includes a level converting unit 133, a pulse width detecting unit 131, and a delay control unit 132. The level shifting unit 133 is coupled between the pulse width detecting unit 131 and the output terminal of the driving module 120, and is configured to perform level shifting on the first output signal VOP and the second output signal VON. Since the first output signal VOP and the second output signal VON are directly provided to the load, a typical level range is in a high voltage domain range, for example, 6.5V to 12.5V; the pulse width detection unit 131 adopts a logic circuit, and generally operates in a low voltage range, for example, 2.8V to 5.5V. The level conversion unit 133 converts the first output signal VOP and the second output signal VON from a high-voltage domain (PVDD) to a low-voltage domain (VDD) to form a first converted signal and a second converted signal. The level shift unit 133 may input the voltage of the PVDD domain to the drain terminal of the isolation tube through the ESD resistor, and clamp the voltage to the VDD domain to implement level shift. Those skilled in the art can select an appropriate level shift circuit to implement voltage shifting in a specific level range according to the requirement. The first converted signal corresponds to the first output signal VOP and the second converted signal corresponds to the second output signal VON.
The pulse width detection unit 131 is configured to detect whether the level-converted first converted signal and the level-converted second converted signal have pulses, and output corresponding control signals according to a detection result.
The delay control unit 132 is coupled to the pulse width detection unit 131, and is configured to adjust a delay amount of the second delay signal VO3 according to the control signal. The delay control unit 132 includes a charging structure, controls a charging and discharging process of the charging structure through a second pulse width modulation signal VO2, and outputs a delayed second delay signal VO3 after the charging and discharging are completed. The control signal may control the charging time within the charging structure, thereby controlling the delay amount of the second delay signal VO3, the faster the charging, the smaller the delay amount. The charging structure at least comprises a charging capacitor structure and a charging current source, the charging time can be adjusted by controlling the size of the charging current or controlling the size of the charging capacitor, and then the delay amount is adjusted, specifically, the negative correlation between the delay amount and the size of the charging current is positive correlation with the size of the charging capacitor.
In another embodiment of the present invention, it is also possible to determine whether the first output signal VOP and the second output signal VON have pulses by detecting signals output from any stage of buffer in the driving output units 122a and 122 b. Since the driving output unit 122a and the driving output unit 122b mainly amplify the power of the signal without changing the waveform of the signal, the signals output by each stage of buffers in the driving output unit 122a and the driving output unit 122b can also accurately reflect the pulse waveforms of the first output signal VOP and the second output signal VON, and the driving output unit 122a and the driving output unit 122b have a lower level range, and can directly detect the signal through the pulse width detection unit 131 without performing level conversion through the level conversion unit 133, so that the circuit structure of the pulse width adjustment module 130 can be simplified.
The minimum Delay control module 140 is connected to the pulse width adjustment module 130, and the input ends of two differential signals VOP0 and VOPN of the input signal, and is configured to output a minimum Delay control signal Delay _ CTRL to the pulse width adjustment module 130 according to the magnitude of the input signal, so as to control the minimum value of the relative Delay amount. The minimum value of the relative delay determines the minimum pulse width of the first output signal VOP and the second output signal VON. In some embodiments, the minimum delay control module 140 implements the detection of the input power by detecting the signal amplitude of the input signal. The larger the input signal amplitude, the greater the input power. The signal amplitude is the signal voltage value.
The pulse width adjustment module 130 adjusts the relative delay amount based on the minimum value of the relative delay amounts. Specifically, the minimum delay control module 140 may set the minimum value of the relative delay amount to be low enough when the amplitude of the input signal is close to 0 (i.e., in a static operating state), so that the minimum pulse widths of the first output signal VOP and the second output signal VON are low enough to sufficiently reduce power consumption; when there is an input signal, especially a small signal input, the minimum delay control module 140 may increase the minimum value of the relative delay amount appropriately, so that the minimum pulse widths of the first output signal VOP and the second output signal VON are increased, thereby avoiding the problem of signal distortion caused by too small pulse widths, and achieving a balance between low power consumption and low distortion.
In some embodiments, the minimum delay control module 140 is configured to control the minimum value to be T1 when the input signal is smaller than a first threshold, specifically, when the input signal amplitude is smaller than V1, the system is normally in a static operating state; and when the amplitude of the input signal is greater than or equal to a first threshold value, controlling the minimum value to be T2, wherein T2> T1.
In some embodiments, the minimum delay control module 140 may be further configured to control the minimum value to be T3 when the input signal is greater than the second threshold, where the second threshold is greater than the first threshold, and T3< T2, preferably, T3= T1. When the input signal is larger than the second threshold value, the input signal belongs to large signal input, the minimum value of the pulse width is reduced, signal distortion cannot be generated, and the power consumption during signal input can be further reduced.
The minimum Delay control module 140 outputs a corresponding minimum Delay control signal Delay _ CTRL according to the magnitude of the input signal, and can dynamically adjust the minimum value of the relative Delay amount in real time according to the continuous change of the input signal, so that the whole circuit realizes narrow pulse width modulation, reduces power consumption, and improves the signal distortion.
Fig. 2 is a schematic structural diagram of a pulse width detection unit 131 according to an embodiment of the invention.
In this embodiment, the pulse width detection unit 131 includes: an arithmetic circuit 1311, an add signal path 1312, and a subtract signal path 1313.
The operation circuit 1311 is configured to perform an and operation after performing a non-operation on the first output signal VOP and the second output signal VON respectively. Specifically, the non-operation circuit 1311 includes an inverter INV2 AND an inverse INV3 respectively connected to two output terminals of the level shift unit 133, AND an AND gate AND connected to the inverter INV2 AND the inverter INV 3.
The control signal output by the pulse width detection unit 131 includes the subtraction signal and the addition signal.
The add signal path 1312 is for outputting an add signal, includingA D flip-flop DFF 1 And a second D flip-flop DFF 2 Said first D flip-flop DFF 1 And a second D flip-flop DFF 2 The clock signal terminal of (2) receives the clock signal CKL1.
The subtract signal path 1313 is for outputting a subtract signal, and includes a third D flip-flop DFF 3 And a fourth D flip-flop DFF 4 Said third D flip-flop DFF 3 And a fourth D flip-flop DFF 4 The clock signal terminal of (2) inputs the clock signal CKL2.
The add signal output terminal is coupled to the third D flip-flop DFF through an inverter INV1 3 And said fourth D flip-flop DFF 4 Reset terminal (Reset), third D flip-flop DFF 3 Is connected to the fourth D flip-flop DFF 4 The fourth D flip-flop DFF 4 And the Q terminal of (a) is used as a subtraction signal output terminal.
When at least one of the VOP AND VON outputs a high level, the AND gate AND outputs a first D flip-flop DFF 1 And a second D flip-flop DFF 2 Outputting a low-level reset signal to enable DFF 1 And DFF 2 Is forced to reset to a low level. AND the AND gate AND outputs a high level when both VOP AND VON are low level, AND the addition signal becomes high level when there is no pulse at both VON AND VOP in two periods of CLK 1.
Inverter INV1 inverts the added signal and provides it to DFF 3 And DFF 4 When the added signal is high level, i.e. both VON and VOP are low level, the DFF 3 And DFF 4 The reset end is at low level, and the reduction signal is at low level; when at least one of VOP and VON is high level, the added signal is low level and is supplied to DFF via inverter INV1 3 And DFF 4 The reset terminal of (2) provides a high level reset signal, and the down signal goes high when both the up signal and the down signal are low in both periods of CLK 2.
Clock signal CLK1 is the clock that controls the add signal output from add signal path 1312 and clock signal CLK2 is the clock that controls the subtract signal output from subtract signal path 1313. The frequency of CLK1 may be greater than the frequency of CLK 2.
The frequency of the CKL1 is high, and a high-level adding signal needs to be output in time after the disappearance of the pulse is detected, so that the pulse width is increased in time, the state of disappearance of the pulse for a long time is avoided, and meanwhile, the CKL1 still needs to be out of an audio frequency range, so that the output signal of the pulse adjustment process is prevented from falling into the audio frequency range to generate noise. Since the audio frequency range is 20Hz to 20KHz, the frequency of CLK1 may be set to be greater than 20KHz. Further, to ensure that the large periodic envelope formed by the output does not enter the audio range, CLK1 may be greater than 100kHz.
Since the pulse width does not need to be immediately reduced when a pulse is detected, frequent switching of the addition signal and the subtraction signal can be avoided. While the frequency of CLK2 is also guaranteed to be outside the audio frequency range, the CLK2 frequency may even be less than 20Hz.
Preferably, the frequency of CLK1 is 400kHz and the frequency of CLK2 is 10Hz.
Fig. 3 is a schematic structural diagram of the delay control unit 132 according to an embodiment of the invention.
In this embodiment, the delay control unit 132 includes: a counting unit 1321 and a control circuit 1322.
The counting unit 1321 is configured to count according to a clock signal, and count once every clock rising edge occurs. In this embodiment, the counting unit 1321 includes a counter and related electronic devices and circuit structures, and the counter is a binary up-down counter, which can perform both up-down counting and down-down counting. The counting unit 1321 is configured to output an n-bit (bit) signal. In one embodiment, the counting unit 1321 is configured to output 3-bit binary coded signals, including 000 to 111, capable of counting from 0 to 8. In other embodiments, the counting unit 1321 is configured to output n-bit signals, which are implemented from 0 to 2 n Is counted.
The counting unit 1321 is configured to change a count value of the counting unit 1321 according to the control signal, i.e., the add signal and the subtract signal, output by the pulse width detection unit 131, and the control circuit 1322 is configured to adjust the delay amount according to the count value. In the control signal, the addition signal is used for increasing the counting value when being in high level, and the subtraction signal is used for reducing the counting value when being in high level.
In this embodiment, the control circuit 1322 includes a charging current source structure 1322a and a charging capacitor structure 1322b. The charging current source structure 1322a is composed of a current source Ib and a PMOS transistor MP 1 ～MP 4 NMOS transistor MN 1 ～MN 3 And (4) forming. The second pulse width modulation signal VO2 passes through MP 4 And MN 1 An inverter configured to couple to the charge capacitor structure 1322b; when MP 4 And MN 1 When the inverter outputs high level, the charging capacitor structure 1322b is charged; when the inverter outputs a low level, the charging capacitor structure 1322b is discharged. The charging current source structure 1322a charges the charging capacitor structure 1322b to form a signal delayed from VO2 and inverted from VO2, and then outputs a second delayed signal VO3 after pulse delay to VO2 through the inverter INV 2.
The current source Ib passes through MP 1 And MP 2 Composed current mirror, and MN 2 And MN 3 A current mirror configured to provide power to the MP 4 And MN 1 An inverter configured to provide a charging current to the charging capacitor structure 1322b. The larger the charging current is, the shorter the charging time is, the smaller the delay amount of VO3 relative to VO2 is, and the smaller the pulse widths of VOP and VON are; the smaller the charging current is, the longer the charging time is, the larger the delay amount of VO3 with respect to VO2 is, and the larger the pulse widths of VOP and VON are outputted. In this embodiment, the current source Ib is a fixed bias current.
The charging time of the capacitor is proportional to the capacitance value and inversely proportional to the charging current. The larger the capacitance value of the charging capacitor structure 1322b is, the longer the charging time is, the larger the delay amount of the VO3 relative to the VO2 is, and the larger the pulse width of the output VOP and VON is; the smaller the capacitance value is, the shorter the charging time is, the smaller the delay amount of VO3 with respect to VO2 is, and the smaller the pulse widths of VOP and VON are outputted.
In this embodiment, the current source Ib is a constant current. The charging capacitor structure 1322b comprises n charging capacitors C connected in parallel 1 ～C n Respectively through switches SW 1 ～SW n Ground, the other endThe PMOS transistor MP4 and the NMOS transistor MN1 are connected to the output end of the phase inverter formed by the PMOS transistor MP4 and the NMOS transistor MN1, namely the drain electrodes of the PMOS transistor MP4 and the NMOS transistor MN 1. The charging capacitor structure 1322b further includes an initial capacitor C 0 And an adjusting capacitor C ctrl Said initial capacitance C 0 One end of the transistor is grounded, and the other end of the transistor is connected to the drain electrodes of the MP4 and the MN 1; the adjusting capacitor C ctrl One end of which passes through a delay control switch SW 0 Ground, drain of MP4 and MN1, the Delay control switch SW being controlled by the minimum Delay control signal Delay _ CTRL 0 Make and break of (2). n is an integer of 2 or more.
The capacitance of the whole charging capacitor structure comprises an adjustable capacitance and a minimum capacitance, wherein the adjustable capacitance is formed by a charging capacitor C 1 ～C n Provide, while the minimum capacitance value C min From an initial capacitance C 0 And adjusting the capacitance C ctrl Provided is a method. Wherein, according to the adjusting capacitance C ctrl Corresponding delay control switch SW 0 On-off state of (C), minimum capacitance value min Can be C 0 Or C 0 +C ctrl . Controlling the Delay control switch SW by the minimum Delay control signal Delay _ CTRL 0 Can realize the minimum capacitance value C min And further realizes the control of the minimum value of the delay amount of VO3 with respect to VO2.
The switch SW 1 ～SW n Each bit signal of the n-bit signals output by the counting unit 1321 is controlled. In this embodiment, when the i-th bit signal is 0 (low level), the switch SW i Disconnecting; when the ith bit signal is 1 (high level), the switch SW i And conducting. Thus, at the minimum capacitance value C min Under certain conditions, when the counting unit outputs signals with n bits (bit) of 0, the switch SW 1 ～SW n All are conducted, and the capacitance value of the charging capacitor structure 1322b is the largest and is the charging capacitor C min ～C n Parallel capacitance value of (i.e. C) min +C 1 ……+C n The relative delay amount is maximum; when the counting unit outputs a signal with n bits being 1, each switch is turned off, and the capacitance value of the charging capacitor structure 1322b is the minimum capacitanceValue C min . In other embodiments, the corresponding relationship between the signal on each bit and the on/off of the switch may also be adjusted, for example, when the ith bit signal is 1, the switch SWi is turned off, and when the ith bit signal is 0, the switch SW is turned off i And conducting.
Can be set by setting C 1 ～C n The capacitance value of the charging capacitor structure 1322b is made larger as the count value of the counting unit 1321 is gradually increased. In one embodiment, the capacitor C may be caused to charge 1 To C n In (C) i Has a capacitance value greater than C1+ … … + C i-1 And i is an integer of 1 or more.
Minimum capacitance value C min The minimum relative delay amount of the second delayed signal VO3 with respect to the first pulse width modulation signal VO1 is determined. In other embodiments, a plurality of adjusting capacitors may be provided, and the minimum capacitance C may be adjusted in a wider range min 。
In another embodiment, the charging capacitor structure 1322b of the control circuit 1322 may further have a fixed charging capacitance, and the current source Ib in the charging current source structure 1322a may be a variable current source, and the delay amount is adjusted by adjusting the charging current outputted by the current source Ib. In one embodiment, the current source Ib may include n charge current sources Ib1 to Ibn connected in parallel, and the initial charge current Ib0 and the adjusted charge current Ib ctrl The initial charging current Ib0 is directly grounded, and the charging current Ib is adjusted ctrl And the grounding is realized by adjusting the switch. Ib1 to Ibn are grounded through switches K1 to Kn, and are coupled to the charging capacitor structure 1322b, and the on/off of each switch Ki is controlled by an n-bit signal output by the counting unit 1321, so as to control the magnitude of the charging current output by the charging current source structure 1322 a.
The adjusting switch is controlled by a minimum Delay control signal Delay _ CTRL, and the maximum charging current Imax of the whole charging current structure can be Ib0+ … + Ibn + Ib ctrl Or Ib0+ … + Ibn. Therefore, the maximum value of the charging current may be controlled by the minimum Delay control signal Delay _ CTRL, thereby implementing control of the minimum value of the relative Delay amount。
In one embodiment, ki is turned on when the ith bit signal is 0; ki is turned off when the ith bit signal is 1. Under the condition that the minimum delay control signal is fixed, when n-bit signals of the counting value are all 0, K1-Kn are conducted, the charging current is maximum, the charging time is minimum, and the delay quantity is minimum; when the n is the signal 1, K1-Kn is disconnected, the charging current is minimum, the charging time is longest, and the delay amount is maximum.
In other embodiments, the variable current source Ib and the charging capacitor structure with a variable capacitance value may be set at the same time, and the adjustment of the charging time may be implemented by adjusting the charging current and the size of the charging capacitor, so as to implement the adjustment of the relative delay amount.
Fig. 4a is a schematic structural diagram of a minimum delay control module according to an embodiment of the invention.
In this embodiment, the minimum delay control module 140 includes a reference generation unit 141 and a comparison unit 142, the reference generation unit 141 generating a first reference voltage Vref1 corresponding to a first threshold value of an input signal; the comparing unit 142 is configured to compare the input signal with the first reference voltage Vref1, and output a corresponding minimum Delay control signal Delay _ CTRL according to a comparison result. The reference generating unit 141 may include a reference generating circuit.
Fig. 4b is a schematic structural diagram of the comparison unit according to an embodiment of the present invention.
In this embodiment, the comparing unit 142 includes a first comparing path, and the first comparing path includes: a first comparator CMP41, a second comparator CMP42, and an or operation circuit.
In this embodiment, the or operation circuit includes a first NOR gate NOR41 and a first not gate INV41. In other embodiments, the or operation circuit may be implemented by other circuit structures as long as the or operation function can be satisfied.
The negative input ends of the first comparator CMP41 and the second comparator CMP42 are both connected to a first reference voltage Vref1; a positive input terminal of the first comparator CMP41 is used for connecting a differential signal VOP0 in the input signal, and comparing VOP0 with Vref1; the positive input terminal of the second comparator CMP42 is used for connecting the differential signal VON0 in the input signal, and comparing VON0 with Vref1. The output signals of the first and second comparators CMP41 and CMP42 are NOR-operated by the first NOR gate NOR41, and then inverted by the first NOR gate INV41, and then the minimum Delay control signal Delay _ CTRL is output.
When the amplitudes of both signals in VOP0 and VON0 are smaller than the first reference voltage Vref1, the first comparator CMP41 and the second comparator CMP42 both output a low level, the NOR41 outputs a high level, the INV41 outputs Delay _ CTRL as a low level, the minimum value of the relative Delay amount is controlled to be T1, T1< T2, corresponding to fig. 3, where Delay _ CTRL is a low level, the adjustment switch SW0 is controlled to be turned off, and the minimum charging capacitance value Cmin = C0.
When the amplitude of at least one of the signals VOP0 and VON0 is greater than the first reference voltage Vref1, at least one of the output signals of the comparator CMP41 and the comparator CMP42 is at a high level, the NOR41 outputs a low level, the INV41 outputs Delay _ CTRL at a high level, the minimum value of the relative Delay amount is controlled to be T2, corresponding to fig. 3, the Delay _ CTRL is at a high level, the adjustment switch SW0 is controlled to be turned on, and the minimum charging capacitance value Cmin = C0+ Cctrl.
Referring to fig. 5a, a schematic structural diagram of the minimum delay control module according to another embodiment of the present invention is shown.
In this embodiment, the minimum delay control block includes a reference generation unit 141a and a comparison unit 142a. The reference generating unit 141a is configured to generate a first reference voltage Vref1 corresponding to a first threshold, and a second reference voltage Vref2 corresponding to a second threshold. The comparing unit 142a compares the differential signals VON0 and VOP0 in the output signal with the first reference voltage Vref1 and the second reference voltage Vref2, and outputs a corresponding minimum Delay control signal Delay _ CTRL according to a comparison result. The first threshold is smaller than the second threshold, and the corresponding first reference voltage Vref1 is smaller than the second reference voltage Vref2.
Please refer to fig. 5b, which is a specific circuit structure diagram of the comparing unit 142a in fig. 5 a.
In this embodiment, on the basis of the first comparison path compared with the first reference voltage Vref1 shown in fig. 4b, a second comparison path compared with the second reference voltage Vref2 is further included, and specifically, the second comparison path includes: a third comparator CMP43, a fourth comparator CMP44, and an or operation circuit. The or operation circuit includes a second NOR gate NOR42 and a second NOR gate INV42 connected in sequence. In other embodiments, the or operation circuit may have other circuit structures as long as the or operation function is satisfied.
The positive input terminals of the third comparator CMP43 and the fourth comparator CMP44 are both connected to a second reference voltage Vref2; the negative input terminal of the third comparator CMP43 is used for connecting the differential signal VOP0 in the input signal, and comparing VOP0 with Vref2; the negative input terminal of the fourth comparator CMP44 is used for connecting the differential signal VON0 in the input signal for comparing VON0 with Vref2. The output signals of the third comparator CMP43 and the fourth comparator CMP44 are NOR-operated by the second NOR gate NOR42, and then inverted by the second NOR gate INV42, and the comparison result of the second comparison path is output.
The comparing unit 142a further includes an exclusive or circuit including an exclusive or gate XOR41 and a third not gate INV43, for performing an exclusive or operation on the signals output by the first not gate INV41 and the second not gate INV42. The output signals of the first and second not gates INV41 and INV42 sequentially pass through the XOR gate XOR43 and the third not gate INV43, and output the minimum Delay control signal Delay _ CTRL.
When VON0 and VOP0 are both less than Vref1, the first comparator CMP41 and the second comparator CMP42 both output a low level, NOR41 outputs a high level, and INV41 outputs a low level; the third comparator CMP43 and the fourth comparator CMP43 each output a high level, the NOR42 outputs a low level, and the INV42 outputs a high level; therefore, the XOR gate XOR41 outputs a high level, the minimum Delay control signal Delay-ctrl output by the third not gate INV43 is at a low level, and the minimum value of the control relative Delay amount is T1.
When at least one of the signals VON0 and VOP0 is greater than Vref1 and less than Vref2, at least one of the first comparator CMP41 and the second comparator CMP42 outputs a high level, the NOR41 outputs a low level, and the INV41 outputs a high level; at least one of the third comparator CMP43 and the fourth comparator CMP43 outputs a high level, the NOR42 outputs a low level, and the INV42 outputs a high level; therefore, the XOR gate XOR41 outputs a low level, the minimum Delay control signal Delay-ctrl output by the nor gate INV43 is at a high level, and the minimum value of the control relative Delay amount is T2.
When both of VON0 and VOP0 are greater than Vref2, the first comparator CMP41 and the second comparator CMP42 both output a high level, the NOR41 outputs a low level, and the INV41 outputs a high level; the third comparator CMP43 and the fourth comparator CMP43 both output a low level, NOR42 outputs a high level, and INV42 outputs a low level; therefore, the XOR gate XOR41 outputs a high level, the minimum Delay control signal Delay-ctrl output by the nor gate INV43 is at a low level, and the minimum value of the control relative Delay amount is T1.
Since the signal amplitude of the input signal may frequently swing on both sides of the first threshold and the second threshold, that is, the input signal amplitude swings on both sides of the first reference voltage and the second reference voltage, it is easy to cause the output lowest Delay control signal Delay _ ctrl to frequently switch high and low levels, which causes the circuit state to switch too frequently and the stability to decrease. To solve this problem, embodiments of the present invention further provide another comparison unit capable of avoiding frequent switching of the minimum relative delay amount.
Fig. 6 is a schematic structural diagram of a comparing unit in a minimum delay control module according to an embodiment of the present invention.
In this embodiment, the reference generating unit of the minimum delay control module generates the first offset reference voltage Vref1_ hys and the first reference voltage Vref1 corresponding to the first threshold at the same time, and Vref1_ hys > Vref1.
On the basis of the embodiment shown in fig. 4b, in this embodiment, the first comparison path of the comparing unit 142c for comparing the input signal with the first threshold further includes: a first transmission gate TG1 and a second transmission gate TG2. The input end of the first transmission gate TG1 is used for connecting a first reference voltage Vref1, the control end is connected to the output end of the first not gate INV41, and the inverted control end is connected to the output end of the first not gate NOR 41; the input end of the second transmission gate TG2 is used for being connected to a first offset reference voltage Vref1_ hys, the control end is connected to the output end of the first NOR gate NOR41, and the inverted control end is connected to the output end of the first NOR gate INV 41; the positive input end of the first comparator CMP41 is connected to the differential signal VOP0 in the input signal, the positive input ends of the second comparator CMP42 are respectively connected to the differential signal VON0 in the input signal, and two negative input ends are commonly connected to the output ends of the first transmission gate TG1 and the second transmission gate TG2.
When the circuit works in a static state, for example, when the input signal is 0, CMP41 and CMP42 both output a low level, NOR41 output signal PO1N is a high level, INV41 output Delay _ ctrl is a low level, the minimum value of the controlled Delay amount is T1, and the second transmission gate TG2 is controlled to be turned on, the negative input terminals of CMP41 and CMP42 are connected to the first offset reference voltage Vref1_ hys; as the input signal gradually increases, until at least one of VOP0 or VON0 is greater than Vref1_ hys, the NOR41 output signal PO1N becomes low, the INV41 output Delay _ ctrl becomes high, the control Delay amount minimum value is T2, the first transmission gate TG1 is turned on, the second transmission gate TG2 remains off, the negative input terminals of CMP41 and CMP42 are connected to the first reference voltage Vref1, and the subsequent output signal is compared with the first reference voltage Vref1.
When the input signal is gradually reduced from being larger than Vref1-hys, as the second transmission gate TG2 is conducted, the reference voltages of CMP41 and CMP42 are both Vref1 until the amplitude of the input signal is reduced to be smaller than Vref1, the outputs of CMP41 and CMP42 are both changed into low level, PO1N is changed into high level, delay _ ctrl is changed into low level, the minimum value of the relative Delay amount is controlled to be T1, the second transmission gate TG2 is controlled to be conducted, the first transmission gate TG1 is closed, and the subsequent signal is compared with the first offset reference voltage Vref1_ hys.
From the above analysis, when the amplitude of any one of the input signals gradually increases from being smaller than the first reference voltage, the larger Vref1-hys is used for comparing with the subsequent input signal; when the amplitude of any one signal is gradually reduced from being larger than the first offset reference voltage, comparing the signal with a subsequent input signal by using smaller Vref1; by respectively setting different reference voltages for comparison in the two processes of signal increase and signal decrease, after the Delay _ ctrl is switched, if the reverse variation amplitude of the input signal is within hys, the Delay _ ctrl is not switched any more, thereby avoiding frequent switching of the Delay _ ctrl.
Fig. 7 is a schematic structural diagram of a comparison unit in a minimum delay control module according to another embodiment.
The reference generation unit of the minimum delay control module simultaneously generates a first offset reference voltage Vref1_ hys and a first reference voltage Vref1, and a second reference voltage Vref2 and a second offset reference voltage Vref2_ hys corresponding to the second threshold, wherein Vref1_ hys > Vref1, and Vref2_ hys > Vref2.
On the basis of the embodiment of fig. 6, the comparing unit 142d further comprises a second comparing path for comparing the input signal with a second threshold value. The second comparison path further includes a third transmission gate TG3 and a fourth transmission gate TG4. The input end of the third transmission gate TG3 is used for connecting a second reference voltage Vref2, the control end is connected to the output end of the second NOR gate NOR42, and the inverted control end is connected to the output end of the second NOR gate INV 42; an input end of the fourth transmission gate TG4 is configured to be connected to a second offset reference voltage Vref2_ hys, a control end is connected to an output end of the second NOR gate INV42, and an inverted control end is connected to an output end of the second NOR gate NOR 42; a negative input terminal of the third comparator CMP43 is connected to the differential signal VOP0 in the input signal, a negative input terminal of the fourth comparator CMP44 is connected to the differential signal VON0 in the input signal, and two positive input terminals are commonly connected to output terminals of the third transmission gate TG3 and the fourth transmission gate TG4.
In this embodiment, when the apparatus operates in a static state, for example, when the input signal is 0, both CMP41 and CMP42 output a low level, PO1N is a high level, PO1 is a low level, the second transmission gate TG2 is controlled to be turned on, and the negative input terminals of CMP41 and CMP42 are connected to Vref1-hys; the CMP43 and the CMP44 both output high level, PO2 is low level, PO2N is high level, the fourth transmission gate TG4 is controlled to be conducted, and the positive input ends of the CMP43 and the CMP44 are connected to Vref2-hys; at this time, delay-ctrl is low, and the minimum value of the relative Delay amount is controlled to be T1.
When the input signal is gradually increased until at least one of VOP0 or VON0 is greater than Vref1_ hys and at least one of VOP0 or VON0 is less than Vref2-hys, PO1N becomes low level, PO1 becomes high level, the first transmission gate TG1 is controlled to be conducted, and the negative input ends of CMP41 and CMP42 are connected to Vref1; the outputs of both CMP43 and CMP44 remain at the high level, PO2 is at the low level, PO2N is at the high level, and the fourth transmission gate TG4 remains turned on; at this time, the Delay-ctrl signal is inverted to a high level, and the minimum value of the relative Delay amount is controlled to be T2.
When the input signals are increased to be larger than Vref2-hys, PO1N is still at a low level, PO1 is still at a high level, and the first transmission gate TG1 is controlled to be conducted; the CMP3 and CMP4 output a low level, PO2 becomes a high level, PO2N is a low level, the third transmission gate TG3 is controlled to be turned on, and the positive input terminals of the CMP43 and CMP44 are connected to Vref2; at this time, the Delay-ctrl signal is inverted to a low level, and the minimum value of the relative Delay amount is controlled to be T1.
Similarly, when the input signal is reduced from being larger than Vref2-hys to being smaller than Vref2 and larger than Vref1, the Delay-ctrl signal is inverted to a high level, and the minimum value of the relative Delay is controlled to be T2; when the input signal continues to drop to be less than Vref1, the Delay-ctrl signal is inverted to a low level, and the minimum value of the relative Delay amount is controlled to be T1.
From the above analysis, when the input signal increases, the input signal is compared with Vref1-hys and Vref2-hys; when the input signal decreases, the input signal is compared with Vref1 and Vref2.
Please refer to fig. 8a and 8b, which are waveform diagrams of respective signals in a static operating state.
In the static initial state (please refer to fig. 8 a), the input signal is smaller than the first threshold. In the initial state, the input signal is 0, and VO1 and VO2 are square wave signals with 50% duty ratio in the same time sequence. In the initial state, the add signal and the subtract signal are both low, the n-bit counting unit 1321 (see fig. 3) outputs the count value of 11 … … (n bits), the charging capacitance is the maximum, the VO3 delay is the maximum, and the pulse width of the output signal is the maximum.
Referring to FIG. 4b, at CLK2 (control signal reduction)Clock frequency of D flip-flop) when the second rising edge comes, the minus signal flips to high level, and the delay control unit 132 starts to adjust the delay amount of VO3, and the minimum value of the relative delay amount is set to T1 due to the action of the minimum delay control module 140 (see fig. 1), corresponding to fig. 3, the adjustment switch SW0 is turned off, and Cmin = C0; when the output value of the counting unit 1321 is gradually decreased to 00 … … (n bits), the switches SW1 to SWn are all turned off, and the capacitance value of the charging capacitor structure 1322b is the minimum, and is Cmin = C0; accordingly, the pulse widths of GTA and GTB (corresponding to VOP and VON) are from t 0 Decreasing to a minimum value tn defined by the charging capacitor C0, tn being determined by a minimum value T1 of the relative delay; thereafter, the count unit 1321 outputs 000 … … 0 which remains unchanged, so the pulse widths of VOP and VON are always at a minimum. In other embodiments, in the process of gradually decreasing the output value of the counting unit 1321 to 000 … …, when the dead time of the driving output units 122a and 122b is greater than or equal to the pulse width of a certain gear, the output pulse width is decreased to 0, and in two cycles of CLK1 clock, the pulse width detection unit 131 does not detect a pulse, the add signal changes to a high level, the subtract signal changes to a low level, the counting unit 1321 controls the switching circuit to increase the charging capacitance value, the delay is increased, so that the pulse width of the output signal reappears, and then the pulse width is controlled to decrease to the minimum value.
And when the input signal is greater than 0, entering a dynamic working state, including a small signal input state and a large signal input state. When the small signal is in the input state, i.e., the input signal is greater than the first threshold and less than the second threshold, the minimum delay control module 140 (see fig. 1) controls the minimum delay to T2, T2> T1, so that the minimum pulse width during the small signal input is greater than the minimum pulse width during the static operation, and at this time, even if the dead zone of the driving output units 122a and 122b exists, it can be ensured that pulses exist in VON and VOP all the time, thereby reducing the distortion of the small signal; and in a large signal input state, the input signal is larger than the second threshold value, and the minimum pulse width of the VON and the VOP is reduced through the minimum delay control module again, so that the power consumption is further reduced.
Fig. 9 is a schematic structural diagram of a class D audio amplifier according to another embodiment of the present invention.
In this embodiment, the pulse width adjusting module 130 further includes: a fixed delay unit 134, configured to delay the first pulse width modulation signal VO1 by a fixed amount to form a first delayed signal VO4. The delay control unit 132 is configured to delay the second pulse width modulation signal VO1 by a variable amount, so as to achieve variable adjustment of a relative delay amount between the first delayed signal VO4 and the second delayed signal VO3.
By delaying VO1 and VO2 by the fixed delay unit 134 and the delay control unit 132, respectively, it is possible to make the two branches as symmetrical as possible, and reduce signal distortion caused by mismatch factors introduced by delaying only VO 1. By adjusting the delay amount of the signal VO1 by the delay control unit 132, the delay amount between the signal VO3 and the signal VO4 is adjusted.
Please refer to fig. 10, which is a schematic diagram of waveforms of signals of the class D audio amplifier with the structure shown in fig. 9 in a static operating state.
In this example, VO4 has a fixed retardation with respect to VO 1; and VO3 is gradually decreased with respect to the delay amount of VO2 such that the relative delay amount between VO3 and VO4 is gradually decreased by the value T1. After performing differential operation on the signals VO4 and VO3, signals GTA and GTB are obtained, and the pulse widths of both signals are gradually reduced to a minimum pulse width tn determined by a minimum value T1 of the relative delay amount.
Fig. 11 is a schematic structural diagram of a fixed delay unit according to an embodiment of the invention.
In this embodiment, the fixed delay unit 134 includes: current source Ib 0 And a PMOS transistor MP 10 ～MP 40 NMOS transistor MN 10 ～MN 30 And (4) forming. The second pulse width modulation signal VO1 passes through MP 40 And MN 10 The formed inverter is coupled to the fixed capacitor Cm, and when the inverter outputs a high level, the fixed capacitor Cm is charged; and when the inverter outputs a low level, discharging the fixed capacitor Cm. Charging the fixed capacitor Cm to form a signal which is delayed to VO1 and is in inverse phase with VO1, and outputting a fixed delay signal after the pulse of VO1 is delayed through an inverter INV4No. VO4.
The current source Ib 0 By MP 10 And MP 20 Composed current mirror, and MN 20 And MN 30 A current mirror configured to provide power to the MP 40 And MN 10 An inverter configured to supply a charging current to the fixed capacitor Cm. The larger the charging current, the shorter the charging time, and the smaller the delay amount of VO4 with respect to VO 1. In this embodiment, the current source Ib 0 And the fixed capacitance Cm are held fixed so that VO4 and VO1 have a fixed amount of delay therebetween.
The embodiment of the present invention further provides an electronic device having the above class D audio amplifier, where the class D audio amplifier can adaptively adjust a pulse width according to an output signal, so as to ensure that the output signal has a pulse output all the time, thereby reducing the problems of noise and distortion, and also reducing the pulse width as much as possible, thereby reducing power consumption of the electronic device under certain application conditions.
The embodiment of the invention also provides a self-adaptive pulse width adjusting method.
Fig. 12 is a flowchart illustrating an adaptive pulse width adjusting method according to an embodiment of the invention.
The self-adaptive pulse width adjusting method comprises the following steps:
step S1201, the input signal is subjected to pulse width modulation, and a first pulse width modulation signal and a second pulse width modulation signal are generated.
The input signal may be a pair of differential signals, such as analog audio signals. The pulse width modulation comprises: performing integral operation on the pair of differential signals and outputting two amplified signals; the two amplified signals are compared with the modulation signal through a comparator respectively to generate a first pulse width modulation signal and a second pulse width modulation signal.
The modulation signal is typically a triangular wave having a particular frequency and level value. When the level of the amplified signal exceeds the signal level of the triangular wave, the comparator outputs a high level; when the level of the amplified signal is lower than the signal level of the triangular wave, the comparator outputs a low level; therefore, the output first pulse width modulation signal and the output second pulse width modulation signal are both modulated square wave signals with certain duty ratio. In other embodiments, the modulation signal may also be a waveform signal with a periodic rising and falling slope, such as a sawtooth wave or a sinusoidal half wave. The frequency of the modulation signal is usually 400KHz to 800KHz, which is much higher than the frequency of the signal to be modulated.
Step S1204: the minimum value of the relative delay amount is controlled according to the magnitude of the amplitude of the input signal.
In one embodiment, when the input signal is less than a first threshold, controlling the minimum value to be T1; and when the input signal is greater than or equal to the first threshold value, controlling the minimum value to be T2, wherein T2> T1. In other embodiments, the method further includes controlling the minimum value to be T3 when the input signal is greater than the second threshold, where the second threshold is greater than the first threshold, and T3< T2. In some embodiments, T3= T1.
In one embodiment, the method of controlling the minimum value of the relative delay amount includes: providing a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; comparing the input signal to the first and second reference voltages; when the input signal is smaller than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T1; when the input signal is greater than or equal to the first reference voltage and smaller than the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2; and when the input signal is greater than or equal to the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T3.
To avoid frequent switching of the minimum delay control signal, in some embodiments, a first offset reference voltage corresponding to the first threshold, a second offset reference voltage corresponding to the second threshold is provided, the first offset reference voltage being greater than the first reference voltage, the second offset reference voltage being greater than the second reference voltage; the input signal is compared with the first offset reference voltage and the second offset reference voltage when the input signal is gradually increased, and compared with the first reference voltage and the second reference voltage when the input signal is gradually decreased.
And step S1202, adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the first output signal and the second output signal output to the load to form a corresponding first delay signal and a corresponding second delay signal.
The method for controlling the relative delay amount comprises the following steps: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not, and outputting corresponding control signals; and adjusting the relative delay amount according to the control signal.
If no pulse is detected in the first output signal and the second output signal, increasing the delay amount and increasing the pulse width of the first output signal and the second output signal; if the pulse is detected, reducing the delay amount and reducing the pulse width of the first output signal and the second output signal; therefore, the pulse of the first output signal and the pulse of the second output signal are always limited to be close to the minimum pulse width, so that the first output signal and the second output signal are ensured to have pulse output, the problems of noise and distortion are reduced, the width of the pulse can be reduced as much as possible, and the power consumption is reduced.
The above-described adjustments of the relative delay amounts are based on the minimum value of the relative delay amounts set in step S1204. When the power of the input signal is smaller than a first threshold value, if a pulse is detected, the minimum pulse width which can be reached by the first output signal and the second output signal is determined by T1; when the power of the input signal is larger than the first threshold and smaller than the second threshold, the minimum pulse width which can be reached by the first output signal and the second output signal is determined by T2; when the power of the input signal is greater than the second threshold, the minimum pulse width that the first output signal and the second output signal can reach is determined by T3.
And the first output signal and the second output signal which are finally output to the load end by the D-type audio amplifier are detected, and the final output signal is not lost or eliminated by the dead zone of the output driving module before being applied to the load, so that the output pulse width of the first output signal and the second output signal can be reduced as much as possible without worrying about the phenomenon of no output caused by small pulse width.
In some embodiments, the second pwm signal is adjusted by a control circuit, the control circuit includes a charge/discharge structure, and the second pwm signal is delayed by charging or discharging the charge/discharge structure to output a second delayed signal. The delay amount is adjusted by controlling the charging time, and the longer the charging time is, the larger the delay amount is. In step S1203, the minimum value of the relative delay amount may also be controlled by controlling the minimum value of the charging time, and specifically, the minimum value of the relative delay amount may be controlled by controlling a minimum charging capacitance value and/or a maximum charging current value.
In some embodiments, the charging time may be adjusted in value by the count of a counter. Specifically, the delay amount may be adjusted by changing a count value of a counter according to the detection result. Specifically, when there is no pulse, the count value is increased to gradually increase the delay amount and increase the pulse width; when there is a pulse, the count value is decreased to gradually decrease the delay amount and decrease the pulse width. The delay amount may be adjusted by adjusting a charging capacitance value and/or a charging current between the second pwm signal output terminal and a ground terminal through the count value. The larger the charging capacitance value is, the longer the charging time is, the larger the delay amount is, and the output pulse width is increased; the smaller the charging capacitance value is, the shorter the charging time is, the smaller the delay amount is, and the output pulse width is reduced. The larger the charging current is, the shorter the charging time is, the smaller the delay amount is, and the output pulse width is reduced; the smaller the charging current is, the longer the charging time is, the larger the delay amount is, and the output pulse width increases. The count value may be an n-bit binary signal, thereby implementing 2 n A control quantity can be generated as 2 n Charging current, or 2 n A charging capacitance value. The above-mentioned oppositely chargingThe adjustment of the electric current can be realized by a plurality of current sources which can be selectively connected in parallel, and the adjustment of the charging current is realized by selecting one or more current sources to be connected into the circuit according to the counting value. The adjustment of the charging capacitor can be realized by a plurality of capacitors which can be selectively connected in parallel, and the proper capacitor or capacitors are selected to be connected into the circuit through the counting value, so that the adjustment of the charging capacitor is realized.
In some embodiments, the first pulse width modulated signal may also be delayed by a fixed amount to form the first delayed signal.
And step S1203, generating a first output signal and a second output signal which are output to a load according to the first delay signal and the second delay signal, wherein the pulse widths of the first output signal and the second output signal are changed along with the relative delay amount.
Specifically, the first and second delayed signals are power-amplified, and the level values of the first and second delayed signals are amplified to first and second output signals having ideal level values to be applied to a load to drive the load.
The power amplification specifically comprises performing a differential operation on the first delayed signal and the second delayed signal; and performing one-stage or multi-stage power amplification on the two paths of signals after the differential operation to form a first output signal and a second output signal.
The pulse width adjusting method adjusts the pulse width according to the output signal output to the load, realizes the pulse width adjustment of the output signal by adjusting the delay amount of the signal, ensures that the output signal has pulse output all the time, thereby reducing the problems of bottom noise and distortion, and can reduce the pulse width as much as possible, thereby reducing the power consumption of electronic equipment.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.

Claims (23)

1. A class D audio amplifier, comprising:
the pulse width modulation module is used for performing pulse width modulation on an input signal and outputting a first pulse width modulation signal and a second pulse width modulation signal, wherein the input signal comprises two paths of differential signals;
the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal which are output to a load to form a corresponding first delay signal and a corresponding second delay signal;
the driving module is used for generating a first output signal and a second output signal which are output to a load according to a first delay signal and a second delay signal, and the pulse width of the first output signal and the pulse width of the second output signal are changed along with the relative delay amount;
and the minimum delay control module is used for outputting a minimum delay control signal to the pulse width adjusting module according to the amplitude of the input signal so as to control the minimum value of the relative delay amount.
2. The class-D audio amplifier according to claim 1, wherein the minimum delay control module is configured to output a corresponding minimum delay control signal when the amplitudes of the two signals in the input signal are both smaller than a first threshold, and control the minimum value to be T1; and/or when the amplitude of any one path of signal in the input signals is larger than or equal to a first threshold value, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2 and T2> T1.
3. The class D audio amplifier according to claim 2, wherein the minimum delay control module comprises a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and outputting a corresponding minimum delay control signal according to a comparison result.
4. The class D audio amplifier according to claim 3, wherein the comparing unit comprises a first comparator, a second comparator, a first nor gate, and a first not gate; two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, two positive input ends are respectively connected to two differential signals in the input signals, output ends are both connected to the input end of the first NOR gate, and the output end of the first NOR gate is connected to the input end of the first NOR gate.
5. The class D audio amplifier of claim 4, wherein the reference generating unit is further configured to generate a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; the comparison unit is used for controlling the subsequent input signal to be compared with the first reference voltage when the amplitude of at least one path of signal in the input signals is gradually reduced from being larger than the first offset reference voltage, and controlling the subsequent input signal to be compared with the first offset reference voltage when the amplitude of at least one path of signal in the input signals is gradually increased from being smaller than the first reference voltage.
6. The class D audio amplifier of claim 5, wherein the comparing unit further comprises a first transmission gate, a second transmission gate; the input end of the first transmission gate is used for being connected with the first reference voltage, the control end of the first transmission gate is connected to the output end of the first not gate, and the inverted control end of the first transmission gate is connected to the output end of the first not gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; wherein the first offset reference voltage corresponds to the first threshold and is greater than the first reference voltage.
7. The class D audio amplifier of claim 2, wherein the minimum delay control module is further configured to control the minimum value to be T3 when the amplitudes of both of the two signals in the input signal are greater than a second threshold, wherein the second threshold is greater than the first threshold, and T3< T2.
8. The class D audio amplifier according to claim 7, wherein the minimum delay control module comprises a reference generating unit and a comparing unit; the reference generation unit is used for simultaneously generating a first reference voltage corresponding to the first threshold and a second reference voltage corresponding to a second threshold; the comparison unit is used for comparing the input signal with the first reference voltage and the second reference voltage and outputting a corresponding minimum delay control signal according to a comparison result.
9. The class D audio amplifier of claim 8, wherein the reference generating unit is further configured to generate a second offset reference voltage corresponding to a second threshold, the second offset reference voltage being greater than the second reference voltage; the comparison unit is used for controlling the subsequent input signal to be compared with the second reference voltage when the amplitude of at least one path of signal in the input signals is gradually reduced from being larger than the second offset reference voltage, and controlling the subsequent input signal to be compared with the second offset reference voltage when the amplitude of at least one path of signal in the input signals is gradually increased from being smaller than the second reference voltage.
10. The class D audio amplifier of claim 8, wherein the comparison unit further comprises a first comparison path, a second comparison path, and an exclusive-OR circuit; the first comparison path includes: the two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, the two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, the output ends of the first comparator and the second comparator are both connected to the input end of the first NOR gate, and the output end of the first NOR gate is connected to the input end of the first NOR gate; the second compare path comprises: the two positive input ends of the third comparator and the fourth comparator are simultaneously connected to a second reference voltage, the two negative input ends of the third comparator and the fourth comparator are respectively connected to two differential signals in the input signals, the output ends of the third comparator and the fourth comparator are both connected to the input end of the second NOR gate, and the output end of the second NOR gate is connected to the input end of the second NOR gate; the output ends of the first NOT gate and the second NOT gate are connected to the input end of the XOR circuit, and the output end of the XOR circuit is used for outputting the minimum delay control signal.
11. The class D audio amplifier of claim 10, wherein the first comparison path of the comparison unit further comprises a first transmission gate and a second transmission gate, the input terminal of the first transmission gate is connected to the first reference voltage, the control terminal is connected to the output terminal of the first not gate, and the inverted control terminal is connected to the output terminal of the first nor gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; the second comparison path further comprises a third transmission gate and a fourth transmission gate, wherein the input end of the third transmission gate is used for being connected to the second reference voltage, the control end of the third transmission gate is connected to the output end of the second NOR gate, and the inverted control end of the third transmission gate is connected to the output end of the second NOR gate; the input end of the fourth transmission gate is used for being connected to a second offset reference voltage, the control end of the fourth transmission gate is connected to the output end of the second NOR gate, and the inverted control end of the fourth transmission gate is connected to the output end of the second NOR gate; wherein the first offset reference voltage corresponds to a first threshold and is greater than the first reference voltage; the second offset reference voltage corresponds to a second threshold, and the second offset reference voltage is greater than the second reference voltage.
12. The class D audio amplifier of claim 1, wherein the pulse width adjustment module comprises:
the pulse width detection unit is used for detecting whether the first output signal and the second output signal have pulses or not and outputting corresponding pulse width control signals;
and the delay control unit is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal on the basis of the minimum value according to the pulse width control signal.
13. A method for adaptive pulse width adjustment for a class D audio amplifier, comprising:
performing pulse width modulation on an input signal to generate a first pulse width modulation signal and a second pulse width modulation signal;
adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal output to a load to form a corresponding first delay signal and a second delay signal;
generating a first output signal and a second output signal to be output to a load according to a first delay signal and a second delay signal, wherein the pulse widths of the first output signal and the second output signal are changed along with the relative delay amount;
wherein the minimum value of the relative delay amount is controlled according to the magnitude of the amplitude of the input signal.
14. The adaptive pulse width adjustment method according to claim 13, wherein the method of controlling the minimum value of the relative delay amount according to the magnitude of the amplitude of the input signal further comprises: when the amplitudes of the two paths of signals of the input signal are smaller than a first threshold value, controlling the minimum value to be T1; and when the amplitude of at least one path of signals of the input signals is larger than the first threshold value, controlling the minimum value to be T2, wherein T2 is greater than T1.
15. The adaptive pulse width adjustment method according to claim 14, wherein the method of controlling the minimum value of the relative delay amount according to the magnitude of the amplitude of the input signal further comprises: providing a first reference voltage corresponding to the first threshold, comparing the input signal with the first reference voltage; when the amplitudes of the two paths of signals of the input signal are smaller than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T1; and when the amplitude of at least one path of signal is greater than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2.
16. The adaptive pulse width adjustment method according to claim 15, wherein the method of controlling the minimum value of the relative delay amount includes: providing a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; when the amplitude of at least one of the input signals is gradually reduced from being larger than the first offset reference voltage, the subsequent input signal is controlled to be compared with the first reference voltage, and when the amplitude of at least one of the input signals is gradually increased from being smaller than the first reference voltage, the subsequent input signal is controlled to be compared with the first offset reference voltage.
17. The adaptive pulse width adjustment method of claim 14, wherein the method of controlling the minimum value of the relative delay amount further comprises: and when the amplitudes of the two paths of signals in the input signal are both larger than a second threshold value, controlling the minimum value to be T3, wherein the second threshold value is larger than the first threshold value, and T3 is less than T2.
18. The adaptive pulse width adjustment method of claim 17, wherein the method of controlling the minimum value of the relative delay amount comprises: providing a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; comparing the input signal to the first and second reference voltages; when the amplitudes of the two paths of input signals are smaller than the first reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T1; when the amplitude of at least one path of signal in the input signals is greater than or equal to the first reference voltage and smaller than the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T2; and when the amplitudes of the two paths of signals of the input signal are both greater than or equal to the second reference voltage, outputting a corresponding minimum delay control signal, and controlling the minimum value to be T3.
19. The adaptive pulse width adjustment method of claim 18, wherein the method of controlling the minimum value of the relative delay amount further comprises: providing a first offset reference voltage corresponding to the first threshold, a second offset reference voltage corresponding to the second threshold, the first offset reference voltage being greater than the first reference voltage, the second offset reference voltage being greater than the second reference voltage; when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, controlling the subsequent input signals to be compared with the first reference voltage; when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage, controlling the subsequent input signals to be compared with the first offset reference voltage; and when the amplitude of at least one of the input signals is gradually increased from being smaller than the second reference voltage, the subsequent input signal is controlled to be compared with the second offset reference voltage.
20. The adaptive pulse width adjustment method of claim 13, wherein the method of adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the first output signal and the second output signal output to the load comprises: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not and outputting corresponding control signals; and adjusting the relative delay amount according to the control signal.
21. The adaptive pulse width adjustment method of claim 13, wherein the method of adjusting the relative delay amount further comprises: and delaying the first pulse width modulation signal by a fixed amount to form the first delayed signal.
22. The adaptive pulse width adjustment method of claim 13, wherein the forming of the first output signal and the second output signal comprises: performing differential operation on the first delay signal and the second delay signal and outputting two paths of differential operation signals; and respectively carrying out power amplification on the two paths of differential operation signals to generate the first output signal and the second output signal.
23. An electronic device, comprising: a class D audio amplifier according to any of claims 1 to 12.
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