CN114094993B - Pulse width expansion circuit - Google Patents
Pulse width expansion circuit Download PDFInfo
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- CN114094993B CN114094993B CN202210062905.6A CN202210062905A CN114094993B CN 114094993 B CN114094993 B CN 114094993B CN 202210062905 A CN202210062905 A CN 202210062905A CN 114094993 B CN114094993 B CN 114094993B
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- switching tube
- tube
- switch tube
- load unit
- pulse width
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
Abstract
The invention relates to a pulse width expansion circuit, comprising: the load unit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and N load units; control signal is input to the first end of the first switch tube, the first end of second switch tube, and the second termination power of first switch tube, the third end of first switch tube with the second end of second switch tube is connected, the third end ground connection of second switch tube, the one end of each load unit is connected with tie point N1 respectively, the other end ground connection of each load unit, the second end and the tie point N1 of third switch tube are connected, the first end of third switch tube, the first end input control signal of fourth switch tube, the third end of third switch tube with the second end of fourth switch tube is connected, the third end ground connection of fourth switch tube. The invention inserts the disclosed pulse width expansion circuit between cascaded memory computing units, and can effectively solve the problem of pulse width distortion in memory computing.
Description
Technical Field
The invention relates to the technical field of data expansion, in particular to a pulse width expansion circuit.
Background
In memory calculation, as the number of cascaded memory calculation units increases, the pulse width representing the input data information is severely distorted, and the pulse width gradually narrows in propagation, which causes a larger error of the result of the memory calculation. The traditional pulse width expansion circuit is realized by adopting a mode of delaying an inverter chain or controlling the grid voltage of a transistor. The adoption of an inverter chain to delay and expand the pulse width brings huge area and power consumption overhead; the control gate voltage causes a large pulse width error. A small amount of pulse width expansion circuits can expand pulse width by adopting a mode of controlling capacitor charging, but fixed capacitor loads are used, and the pulse width cannot be flexibly configured according to requirements. In view of the above problems, how to effectively solve the problem of pulse width distortion in memory calculation is an urgent technical problem to be solved in the art.
Disclosure of Invention
The invention aims to provide a pulse width expansion circuit which is inserted between cascaded memory computing units and can effectively solve the problem of pulse width distortion in memory computing.
To achieve the above object, the present invention provides a pulse width expanding circuit, comprising:
the load unit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and N load units; wherein N is a positive integer greater than or equal to 1;
a control signal IN is input to a first end of the first switching tube and a first end of the second switching tube, a second end of the first switching tube is connected with a power supply, a third end of the first switching tube is connected with a second end of the second switching tube, a third end of the second switching tube is grounded, one end of each load unit is connected with a connection point N1, the other end of each load unit is grounded, a second end of the third switching tube is connected with a connection point N1, a control signal IN is input to the first end of the third switching tube and the first end of the fourth switching tube, the third end of the third switching tube is connected with a second end of the fourth switching tube, and a third end of the fourth switching tube is grounded; the connection point N1 is a point at which the third terminal of the first switch tube and the second terminal of the second switch tube are connected;
the ith load unit includes:
the 2i +3 switching tube, the 2i +4 switching tube, the ith inverter and the ith capacitor;
a first end of the 2i +3 switching tube is connected with an input end of the i-th inverter, a first end of the 2i +4 switching tube is connected with an output end of the i-th inverter, a second end of the 2i +3 switching tube and a second end of the 2i +4 switching tube are both connected with a connection point N1, a third end of the 2i +3 switching tube and a third end of the 2i +4 switching tube are both connected with one end of an i-th capacitor, and the other end of the i-th capacitor is grounded, wherein i is greater than or equal to 1, and i is less than or equal to N; the control signal CTRLI is respectively connected with the first end of the 2i +3 th switching tube and the input end of the i-th inverter.
Optionally, the circuit further comprises:
an inverter TN; the input end of the inverter TN is connected with a connection point N2, and the output end of the inverter TN outputs the adjusted pulse width; the connection point N2 is a point at which the third terminal of the third switching tube and the second terminal of the fourth switching tube are connected.
Optionally, the first switching tube, the third switching tube and the 2i +3 th switching tube in the ith load unit are all PMOS transistors;
and the second switch tube, the fourth switch tube and the (2 i + 4) th switch tube in the ith load unit are all NMOS transistors.
Optionally, the number N of load units is determined according to the pulse width.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention inserts the disclosed pulse width expansion circuit between cascaded memory computing units, and can effectively solve the problem of pulse width distortion in memory computing.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 shows a pulse width expanding circuit of the present invention with 3 load units as an example.
Description of the symbols:
1-a load unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a pulse width expansion circuit which is inserted between cascaded memory computing units and can effectively solve the problem of pulse width distortion in memory computing.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
The invention discloses a pulse width expansion circuit, which comprises: the load cell comprises a first switching tube M1, a second switching tube M2, a third switching tube M3, a fourth switching tube M4 and N load cells 1, wherein N is a positive integer greater than or equal to 1; a first end of the first switching tube M1 and a first end of the second switching tube M2 input control signals IN, a second end of the first switching tube M1 is connected to a power supply, a third end of the first switching tube M1 is connected to a second end of the second switching tube M2, a third end of the second switching tube M2 is grounded, one end of each load unit 1 is connected to a connection point N1, the other end of each load unit 1 is grounded, a second end of the third switching tube M3 is connected to a connection point N1, a first end of the third switching tube M3 and a first end of the fourth switching tube M4 input control signals IN, a third end of the third switching tube M3 is connected to a second end of the fourth switching tube M4, and a third end of the fourth switching tube M4 is grounded; the connection point N1 is a point at which the third terminal of the first switch tube M1 and the second terminal of the second switch tube M2 are connected.
The ith load unit 1 of the present invention includes: the circuit comprises a 2i +3 switch tube, a 2i +4 switch tube, an ith inverter and an ith capacitor; the first end of the 2i +3 switching tube is connected with the input end of the i-th phase inverter, the first end of the 2i +4 switching tube is connected with the output end of the i-th phase inverter, the second end of the 2i +3 switching tube and the second end of the 2i +4 switching tube are both connected with a connection point N1, the third end of the 2i +3 switching tube and the third end of the 2i +4 switching tube are both connected with one end of an i-th capacitor, the other end of the i-th capacitor is grounded, wherein i is greater than or equal to 1, and i is less than or equal to N. The control signal CTRLI is respectively connected with the first end of the 2i +3 th switching tube and the input end of the i-th inverter. Specific examples are: when i =1, the 2i +3 th switching tube is a switching tube M5, the 2i +4 th switching tube is a switching tube M6, the i-th inverter is an inverter T1, the i-th capacitor is a capacitor C1, and the control signal CTRLi is a control signal CTRL 1; when i =2, the 2i +3 th switching tube is a switching tube M7, the 2i +4 th switching tube is a switching tube M8, the i-th inverter is an inverter T2, the i-th capacitor is a capacitor C2, and the control signal CTRLi is a control signal CTRL 2; and so on.
As an optional implementation, the circuit of the present invention further includes: an inverter TN; the input end of the inverter TN is connected with a connection point N2, and the output end of the inverter TN outputs the adjusted pulse width; the connection point N2 is a point at which the third terminal of the third switching tube M3 and the second terminal of the fourth switching tube M4 are connected.
As an alternative embodiment, the first switch transistor M1, the third switch transistor M3 and the 2i +3 th switch transistor in the i-th load unit are all PMOS transistors; the first ends of the first switching tube M1, the third switching tube M3 and the 2i +3 switching tube in the ith load unit are grids; the second ends of the first switching tube M1, the third switching tube M3 and the 2i +3 switching tube in the ith load unit are source electrodes; the third ends of the first switch tube M1, the third switch tube M3 and the 2i +3 th switch tube in each load unit are drains.
The second switch tube M2, the fourth switch tube M4 and the 2i +4 th switch tube in the ith load unit are all NMOS transistors; the first ends of the second switch tube M2, the fourth switch tube M4 and the 2i +4 th switch tube in the ith load unit are grids; the second ends of the second switch tube M2, the fourth switch tube M4 and the 2i +4 th switch tube in the ith load unit are drains; and the third ends of the second switch tube M2, the fourth switch tube M4 and the 2i +4 th switch tube in the ith load unit are source electrodes.
In this embodiment, the number N of load units is determined according to the pulse width.
Example 2
In the present embodiment, 3 load units are taken as an example for discussion, and thus the structure of the configured pulse width expansion circuit is shown in fig. 1. When the input jumps from low level to high level, the transistor M4 is turned on, the connection point N2 can discharge to low level quickly through the transistor M4, and the output OUT of the inverter TN jumps to high level quickly; transistor M2 turns on, discharging the junction N1 voltage to a low level. When the input jumps from high level to low level, the transistors M1 and M3 are turned on, and the connection point N1 is initially low level, so the connection point N2 cannot be charged to high level quickly, and it is necessary to wait until the connection point N1 is charged to high level by M1 before the connection point N2 is charged to high level, and then the output OUT of the inverter TN can be changed to low level, so the output pulse width is expanded compared with the input pulse width. The charging speed of the connection point N1 can be adjusted by controlling the load of the connection point N1, and the configuration of the extended pulse width can be realized by configuring the load of the connection point N1. When the control signal CTRL1 is at a low level, the transistor M5 and the transistor M6 are turned on, and the load capacitor C1 is connected to the connection point N1; when the control signal CTRL2 is at a low level, the transistor M7 and the transistor M8 are turned on, and the load capacitor C2 is connected to the connection point N1; when the control signal CTRL3 is at a low level, the transistors M9 and M10 are turned on, and the load capacitor C3 is connected to the connection point N1. Therefore, the larger the number of low levels in the three control signals CTRL1, CTRL2, and CTRL3, the larger the load capacitance connected to the connection point N1, the slower the voltage at the connection point N1 rises, the later the time at which the connection point N2 changes to a high level, the later the time at which the output changes to a low level, and the larger the expanded pulse width. In practical use, the load capacitor connected to the connection point N1 can be configured according to requirements, so as to obtain the required pulse width.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (3)
1. A pulse width expansion circuit, the circuit comprising:
the load unit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and N load units; wherein N is a positive integer greater than or equal to 1;
a control signal IN is input to a first end of the first switching tube and a first end of the second switching tube, a second end of the first switching tube is connected with a power supply, a third end of the first switching tube is connected with a second end of the second switching tube, a third end of the second switching tube is grounded, one end of each load unit is connected with a connection point N1, the other end of each load unit is grounded, a second end of the third switching tube is connected with a connection point N1, a control signal IN is input to the first end of the third switching tube and the first end of the fourth switching tube, the third end of the third switching tube is connected with a second end of the fourth switching tube, and a third end of the fourth switching tube is grounded; the connection point N1 is a point at which the third terminal of the first switch tube and the second terminal of the second switch tube are connected;
the ith load unit includes:
the 2i +3 switching tube, the 2i +4 switching tube, the ith inverter and the ith capacitor;
a first end of the 2i +3 switching tube is connected with an input end of the i-th inverter, a first end of the 2i +4 switching tube is connected with an output end of the i-th inverter, a second end of the 2i +3 switching tube and a second end of the 2i +4 switching tube are both connected with a connection point N1, a third end of the 2i +3 switching tube and a third end of the 2i +4 switching tube are both connected with one end of an i-th capacitor, and the other end of the i-th capacitor is grounded, wherein i is greater than or equal to 1, and i is less than or equal to N; the control signal CTRLI is respectively connected with the first end of the 2i +3 th switching tube and the input end of the i-th inverter;
the first ends of the first switching tube, the third switching tube and the 2i +3 switching tube in the ith load unit are grids; the second ends of the first switching tube, the third switching tube and the 2i +3 switching tube in the ith load unit are source electrodes; the third ends of the first switching tube, the third switching tube and the 2i +3 th switching tube in each load unit are drain electrodes;
the first ends of the second switch tube, the fourth switch tube and the 2i +4 switch tube in the ith load unit are grids; the second ends of the second switch tube, the fourth switch tube and the 2i +4 th switch tube in the ith load unit are drain electrodes; the third ends of the second switch tube, the fourth switch tube and the 2i +4 th switch tube in the ith load unit are source electrodes;
the circuit further comprises:
an inverter TN; the input end of the inverter TN is connected with a connection point N2, and the output end of the inverter TN outputs the adjusted pulse width; the connection point N2 is a point at which the third terminal of the third switching tube and the second terminal of the fourth switching tube are connected.
2. The pulse width expansion circuit of claim 1, wherein the first switch tube, the third switch tube and the 2i +3 switch tube in the ith load unit are all PMOS transistors;
and the second switch tube, the fourth switch tube and the (2 i + 4) th switch tube in the ith load unit are all NMOS transistors.
3. The pulse width extension circuit of claim 1, wherein the number N of load cells is determined according to a pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062905.6A CN114094993B (en) | 2022-01-20 | 2022-01-20 | Pulse width expansion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062905.6A CN114094993B (en) | 2022-01-20 | 2022-01-20 | Pulse width expansion circuit |
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| Publication Number | Publication Date |
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| CN114094993A CN114094993A (en) | 2022-02-25 |
| CN114094993B true CN114094993B (en) | 2022-05-27 |
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| CN202210062905.6A Active CN114094993B (en) | 2022-01-20 | 2022-01-20 | Pulse width expansion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3925710B2 (en) * | 2002-11-14 | 2007-06-06 | 川崎マイクロエレクトロニクス株式会社 | Pulse width adjustment circuit |
| JP2008219683A (en) * | 2007-03-07 | 2008-09-18 | Seiko Epson Corp | Semiconductor integrated circuit |
| CN100514824C (en) * | 2007-03-28 | 2009-07-15 | 通嘉科技股份有限公司 | Switch type power converter and control circuit for pulse-width modulation |
| CN102025347B (en) * | 2009-09-21 | 2013-06-19 | 联咏科技股份有限公司 | Switch and control signal generator thereof |
| US20130176062A1 (en) * | 2012-01-06 | 2013-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Time delay circuit and method of generating time delayed signal |
| CN111541364B (en) * | 2020-03-31 | 2023-02-10 | 西安电子科技大学 | Dead time control circuit and control method for DC-DC converter |
| CN112886933B (en) * | 2021-01-13 | 2022-10-04 | 上海艾为电子技术股份有限公司 | Class D audio amplifier, adaptive pulse width adjusting method thereof and electronic equipment |
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