JP2008219683A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of changing the pulse width of reset signals depending on whether to disconnect a fuse while using a simple circuit configuration. <P>SOLUTION: The semiconductor integrated circuit includes: a plurality of first circuits serially connected between a first node to which the reset signals are supplied and a second node from which the reset signals are outputted and including a resistor, respectively; a plurality of second circuits connected in parallel between the second node and a reference potential and including a capacitor, respectively; and a logic circuit for adjusting the pulse width of the reset signals and performing output by executing a logical operation using the reset signals supplied to the first node and the reset signals output from the second node. The fuse is connected in parallel with the resistor in at least one of the plurality of first circuits, and the fuse is connected serially to the capacitor in at least one of the plurality of second circuits. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit capable of adjusting the pulse width of a reset signal output from a control circuit such as a CPU.

  In a semiconductor integrated circuit, circuits of each unit are reset by a pulse of a reset signal output from a control circuit such as a CPU. A standard is provided for the pulse width of the reset signal so that an appropriate reset operation is performed by distinguishing the pulse of the reset signal from external noise due to static electricity or the like.

  The pulse width of the reset signal can be adjusted by using a delay circuit that generates a delay by a time constant that is a product of a resistance value and a capacitance value. In the conventional semiconductor integrated circuit manufacturing process, when the pulse width of the reset signal does not meet the standard, the pulse width is adjusted by changing the resistance value or capacitance value of the delay circuit by modifying the metal wiring. However, for this purpose, it is necessary to recreate a mask for metal wiring used in the photolithography process, which increases labor and cost.

  As a related technique, Patent Document 1 below discloses a programmable delay line device that can change the delay amount without using an external control circuit for setting the delay amount. In this programmable delay line device, a terminal for inputting a control signal corresponding to each bit is connected to a power supply line via a resistance element, and a terminal for inputting a control signal is connected to another power supply line via a fuse. It is characterized by that.

According to this programmable delay line device, the level of the control signal can be selected depending on whether or not the fuse is blown, and the delay amount can be changed according to the level of the control signal. However, since many logic gates are used to change the delay amount according to the level of the control signal, there is a problem that the circuit scale increases.
JP-A-5-225795 (page 1-2, FIG. 1)

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit that can change the pulse width of a reset signal depending on whether or not a fuse is cut while using a simple circuit configuration. .

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention is connected in series between a first node to which a reset signal is supplied and a second node to which the reset signal is output, A plurality of first circuits each including a resistor, a plurality of second circuits connected in parallel between the second node and a reference potential, each including a capacitor, and a reset signal supplied to the first node And a logic circuit that adjusts and outputs the pulse width of the reset signal by performing a logical operation using the reset signal output from the second node and at least one of the plurality of first circuits. In one, a fuse is connected in parallel with the resistor, and in at least one of the plurality of second circuits, the fuse is connected in series with the capacitor.

  Here, the logic circuit obtains the logical product of the positive logic reset signal supplied to the first node and the reset signal with a delay output from the second node, thereby reducing the pulse width of the reset signal. An AND circuit that outputs the signal after being shortened by the delay time may be included.

  Alternatively, the logic circuit delays the pulse width of the reset signal by calculating the logical sum of the negative logic reset signal supplied to the first node and the reset signal with a delay output from the second node. An OR circuit that shortens the time and outputs the result may be included.

  Further, the logic circuit may include a buffer circuit that shapes a reset signal output from the second node.

  According to the present invention, the fuse is connected in parallel with the resistor in at least one first circuit constituting the delay circuit, and the fuse is connected in series with the capacitor in at least one second circuit constituting the delay circuit. As a result, the pulse width of the reset signal can be changed depending on whether or not the fuse is cut while using a simple circuit configuration.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration of a reset pulse width adjusting circuit included in the semiconductor integrated circuit according to the first embodiment of the present invention. In this reset pulse width adjustment circuit, a positive logic reset signal is supplied from a control circuit such as a CPU to an input terminal (node A). The reset signal passes through a plurality of first circuits connected in series (four circuits 11 to 14 are shown in FIG. 1) and is output to the node B. The circuits 11 to 14 include resistors R1 to R4, respectively. In at least one of the circuits 11 to 14 (three circuits 12 to 14 in FIG. 1), the resistors R2 to R4 are connected in parallel. Fuses F11 to F13 are connected to each other.

  Further, a plurality of second circuits (four circuits 21 to 24 are shown in FIG. 1) are connected in parallel between the node B and the reference potential (in this embodiment, the ground potential). ing. The circuits 21 to 24 include capacitors C1 to C4, respectively. In at least one of the circuits 21 to 24 (three circuits 22 to 24 in FIG. 1), the capacitors C2 to C4 are connected in series. Fuses F21 to F23 are connected to each other. The circuits 11 to 14 and the circuits 21 to 24 constitute a low-pass filter type delay circuit.

  In order to adjust the pulse width of the reset signal, a logic circuit that performs a logical operation using the reset signal supplied to the node A and the reset signal output from the node B is used. In FIG. 1, a buffer circuit 30 and an AND circuit 40 are shown as logic circuits. The buffer circuit 30 forms a reset signal with a delay output from the node B, and outputs the formed reset signal to the node C. The AND circuit 40 obtains the logical product of the positive logic reset signal supplied to the node A and the reset signal with a delay at the node C, thereby reducing the pulse width of the reset signal by the delay time, A reset signal whose width is adjusted is output to the output terminal (node D).

  Next, the operation of the reset pulse width adjustment circuit included in the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a waveform diagram showing an operation of the reset pulse width adjusting circuit shown in FIG.

  As shown in FIG. 2, the node A is supplied with a reset signal having a positive pulse with a pulse width of 20 μs, for example. The reset signal is delayed by a low-pass filter type delay circuit configured by the circuits 11 to 14 and 21 to 24 and is output to the node B. In FIG. 1, for example, assuming that each value of the resistors R1 to R4 is 20 kΩ, each value of the capacitors C1 to C4 is 50 pF, and the fuses F11 to F13 and F21 to F23 are not disconnected, the delay circuit The time constant is 4 μs. As a result, the reset signal output to the node B is accompanied by a delay substantially corresponding to the time constant 4 μs of the delay circuit.

  This delay time can be adjusted by cutting some of the fuses F11 to F13 and F21 to F23 using a laser or the like. By sequentially cutting the fuses F11 to F13, the series resistance values of the circuits 11 to 14 can be changed from the initial 20 kΩ to 40 kΩ, 60 kΩ, and 80 kΩ. As a result, the time constant of the delay circuit changes from the initial 4 μs to 8 μs, 12 μs, and 16 μs.

  Further, the parallel capacitance values of the circuits 21 to 24 can be changed from the initial 200 pF to 150 pF, 100 kΩ, and 50 kΩ by sequentially cutting the fuses F21 to F23. As a result, the time constant of the delay circuit changes from the initial 4 μs to 3 μs, 2 μs, and 1 μs.

  As shown in FIG. 2, the reset signal with a delay output from the node B is shaped by the buffer circuit 30 and becomes a reset signal at the node C. A high level pulse is output from the AND circuit 40 to the node D in a period in which the reset signal supplied to the node A is at a high level and the reset signal at the node C is at a high level. As a result, the pulse width of the reset signal is shortened by a delay time substantially corresponding to the time constant of the delay circuit. This delay time can be adjusted by cutting some of the fuses F11 to F13 and F21 to F23. In the logic circuit, the buffer circuit 30 shown in FIG. 1 may be omitted, and various other circuit configurations may be used.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing a configuration of a reset pulse width adjusting circuit included in the semiconductor integrated circuit according to the second embodiment of the present invention. In this reset pulse width adjustment circuit, a negative logic reset signal is supplied from a control circuit such as a CPU to an input terminal (node E). The reset signal passes through a plurality of first circuits connected in series (in FIG. 3, four circuits 11 to 14 are shown) and is output to the node F.

  In addition, a plurality of second circuits (shown by four circuits 21 to 24 in FIG. 3) are connected in parallel between the node F and the reference potential (in this embodiment, the ground potential). ing. The circuits 11 to 14 and the circuits 21 to 24 constitute a low-pass filter type delay circuit.

  In order to adjust the pulse width of the reset signal, a logic circuit that performs a logical operation using the reset signal supplied to the node E and the reset signal output from the node F is used. In FIG. 3, a buffer circuit 30 and an OR circuit 50 are shown as logic circuits. The buffer circuit 30 forms a reset signal with a delay output from the node F, and outputs the formed reset signal to the node G. The OR circuit 50 obtains the logical sum of the negative logic reset signal supplied to the node E and the reset signal with a delay at the node G, thereby reducing the pulse width of the reset signal by the delay time, A reset signal whose width is adjusted is output to the output terminal (node H).

  Next, the operation of the reset pulse width adjustment circuit included in the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a waveform diagram showing an operation of the reset pulse width adjusting circuit shown in FIG.

  As shown in FIG. 4, for example, a reset signal having a negative pulse with a pulse width of 20 μs is supplied to the node E. This reset signal is delayed by a low-pass filter type delay circuit composed of the circuits 11 to 14 and 21 to 24 and is output to the node F. The reset signal output to the node F is accompanied by a delay that substantially corresponds to the time constant of the delay circuit.

  Further, the reset signal with a delay output from the node F is shaped by the buffer circuit 30 and becomes a reset signal at the node G. A low level pulse is output from the OR circuit 50 to the node H in a period in which the reset signal supplied to the node E is at a low level and the reset signal at the node G is at a low level. As a result, the pulse width of the reset signal is shortened by a delay time substantially corresponding to the time constant of the delay circuit. This delay time can be adjusted by cutting some of the fuses F11 to F13 and F21 to F23. In the logic circuit, the buffer circuit 30 shown in FIG. 3 may be omitted, and various other circuit configurations may be used.

The block diagram which shows the reset pulse width adjustment circuit in 1st Embodiment. FIG. 3 is a waveform diagram showing an operation of the reset pulse width adjustment circuit shown in FIG. 1. The block diagram which shows the reset pulse width adjustment circuit in 2nd Embodiment. FIG. 4 is a waveform diagram showing an operation of the reset pulse width adjustment circuit shown in FIG. 3.

Explanation of symbols

  11-14 First circuit, 21-24 Second circuit, 30 Buffer circuit, 40 AND circuit, 50 OR circuit, R1-R4 resistor, C1-C4 capacitance, F11-F13, F21-F23 fuse

Claims (4)

A plurality of first circuits connected in series between a first node to which a reset signal is supplied and a second node from which the reset signal is output, each including a resistor;
A plurality of second circuits connected in parallel between the second node and a reference potential, each including a capacitor;
A logic circuit that adjusts and outputs the pulse width of the reset signal by performing a logical operation using the reset signal supplied to the first node and the reset signal output from the second node;
A fuse connected in parallel to the resistor in at least one of the plurality of first circuits, and in series with a capacitor in at least one of the plurality of second circuits. A semiconductor integrated circuit to which a fuse is connected.   The logic circuit obtains a logical product of a positive logic reset signal supplied to the first node and a reset signal with a delay output from the second node, thereby reducing a pulse width of the reset signal. 2. The semiconductor integrated circuit according to claim 1, further comprising an AND circuit that shortens the output by a delay time.   The logic circuit calculates a logical sum of a negative logic reset signal supplied to the first node and a reset signal with a delay output from the second node, thereby reducing a pulse width of the reset signal. The semiconductor integrated circuit according to claim 1, further comprising an OR circuit that shortens the output by a delay time.   The semiconductor integrated circuit according to claim 1, wherein the logic circuit includes a buffer circuit that shapes a reset signal output from the second node.

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