WO2024045269A1

WO2024045269A1 - Data sampling circuit, data receiving circuit, and memory

Info

Publication number: WO2024045269A1
Application number: PCT/CN2022/124414
Authority: WO
Inventors: 张志强; 严允柱
Original assignee: 长鑫科技集团股份有限公司
Priority date: 2022-08-31
Filing date: 2022-10-10
Publication date: 2024-03-07
Also published as: CN115133932A; CN115133932B

Abstract

A data sampling circuit, a data receiving circuit, and a memory. The data sampling circuit comprises: a comparison circuit and an adjustable driving circuit, wherein the comparison circuit is configured to receive first data, second data and a clock signal, compare the first data with the second data in response to the clock signal, and output a comparison result signal; the adjustable driving circuit is electrically connected to the comparison circuit, and is configured to receive the comparison result signal and an adjustment signal, drive the comparison result signal and output a first output signal; and a threshold voltage of the adjustable driving circuit is controlled by means of the adjustment signal.

Description

A data sampling circuit, data receiving circuit and memory

Cross-references to related applications

This disclosure is based on the Chinese patent application with the application number 202211050917.3, the filing date is August 31, 2022, and the invention name is "A data sampling circuit, data receiving circuit and memory", and claims the priority of the Chinese patent application, The entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to, but is not limited to, a data sampling circuit, a data receiving circuit and a memory.

Background technique

Data in integrated circuits are at risk of glitches during transmission. Glitch means that the circuit output waveform contains very short, regular or irregular pulses. Glitch is not useful for the design and may have adverse effects. Therefore, how to remove burrs is a problem that needs to be solved.

Contents of the invention

In view of this, embodiments of the present disclosure provide a data sampling circuit, a data receiving circuit and a memory, which can ensure signal stability and avoid errors.

The technical solution of the embodiment of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides a data sampling circuit. The data sampling circuit includes: a comparison circuit configured to receive first data, second data and a clock signal, and in response to the clock signal, compare the first data and the clock signal. The second data is compared and a comparison result signal is output; an adjustable driving circuit is electrically connected to the comparison circuit and is configured to receive the comparison result signal and the adjustment signal, drive the comparison result signal and output a third An output signal; the threshold voltage of the adjustable driving circuit is controlled by the adjustment signal.

In the above solution, the comparison result signal includes: a first result sub-signal and a second result sub-signal; the first output signal includes: a first output sub-signal and a second output sub-signal; and the adjustable drive circuit includes: : a first controllable inverter configured to receive the first result signal and the adjustment signal, adjust the threshold voltage of the first controllable inverter according to the adjustment signal, and output the first controllable inverter an output sub-signal; a second controllable inverter configured to receive the second result sub-signal and the adjustment signal, adjust the threshold voltage of the second controllable inverter according to the adjustment signal, and The second output sub-signal is output.

In the above scheme, the adjustment signal includes: N adjustment sub-signals; the first controllable inverter includes: a first PMOS tube, a first NMOS tube and N first control units; N is a positive integer; so The gate of the first PMOS transistor, the gate of the first NMOS transistor and the first terminals of the N first control units are all electrically connected to the input terminal of the first controllable inverter, and the The drain of the first PMOS transistor, the drain of the first NMOS transistor and the second terminals of the N first control units are all electrically connected to the output terminal of the first controllable inverter; The source of a PMOS tube is electrically connected to the power terminal, and the source of the first NMOS tube is electrically connected to the ground terminal; the control terminals of N first control units receive N regulator signals one by one, and N The third end of the first control unit is electrically connected to the ground end or the power end; each first control unit is configured to be turned on or off under the control of a corresponding adjustment sub-signal to adjust the Threshold voltage of the first controllable inverter.

In the above scheme, the second controllable inverter includes: a second PMOS transistor, a second NMOS transistor and N second control units; the gate of the second PMOS transistor, the gate of the second NMOS transistor. pole and the first terminals of the N second control units are electrically connected to the input terminal of the second controllable inverter, the drain of the second PMOS transistor, the drain of the second NMOS transistor The second terminals of the N second control units are electrically connected to the output terminal of the second controllable inverter; the source of the second PMOS tube is electrically connected to the power terminal, and the second NMOS tube The source electrode is electrically connected to the ground terminal; the control terminals of the N second control units receive the N regulator sub-signals one-to-one, and the third terminals of the N second control units are all electrically connected to the ground terminal. or the power supply end; each of the second control units is configured to be turned on or off under the control of the corresponding adjustment sub-signal to adjust the threshold voltage of the second controllable inverter.

In the above solution, each first control unit includes: a first adjustment transistor and a second adjustment transistor; the gate of the first adjustment transistor serves as the first terminal of the corresponding first control unit, and the first adjustment transistor The drain of the transistor serves as the second end of the corresponding first control unit, the gate of the second adjustment transistor serves as the control end of the corresponding first control unit, and the source of the second adjustment transistor serves as the corresponding first control unit. The third end of the control unit, the source of the first adjustment transistor is electrically connected to the drain of the second adjustment transistor; each of the second control units includes: a third adjustment transistor and a fourth adjustment transistor; The gate of the third adjustment transistor serves as the first terminal of the corresponding second control unit, the drain of the third adjustment transistor serves as the second end of the corresponding second control unit, and the gate of the fourth adjustment transistor serves as The corresponding control end of the second control unit, the source of the fourth adjustment transistor serves as the corresponding third end of the second control unit, and the source of the third adjustment transistor is electrically connected to the drain of the fourth adjustment transistor. pole.

In the above solution, the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all NMOS transistors; the source of the second adjustment transistor and the fourth adjustment transistor are The sources of the regulating transistors are all electrically connected to the ground terminal.

In the above scheme, the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all PMOS tubes; the source of the second adjustment transistor and the fourth adjustment transistor are The sources of the regulating transistors are all electrically connected to the power terminal.

In the above solution, among the N first control units, the equivalent device size of the i-th first control unit is set to 2i-1 times the equivalent device size of the 1st first control unit. ; Among the N second control units, the equivalent device size of the i-th second control unit is set to 2i-1 times the equivalent device size of the first second control unit; i is greater than Equal to 1 and less than or equal to N.

In the above solution, the data sampling circuit further includes: a latch unit, electrically connected to the comparison circuit, configured to receive the comparison result signal, latch the comparison result signal and output it as a second output signal; The latch unit includes an SR latch.

In the above solution, the comparison circuit includes: an input unit configured to receive the first data and the second data, and generate a differential signal according to the first data and the second data during the sampling stage; a comparison output a unit, electrically connected to the input unit, configured to acquire the differential signal, amplify and latch the differential signal to output the comparison result signal; a reset unit, electrically connected to the comparison output unit, is configured to receive the clock signal and reset the comparison output unit during the reset phase; a switch unit is electrically connected to the input unit and is configured to receive the clock signal and control the comparison circuit according to the clock signal. working status.

In the above solution, the input unit includes: a first transistor and a second transistor; the comparison output unit includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the gate of the first transistor receives The first data, the gate of the second transistor receives the second data; the source of the first transistor is electrically connected to the source of the second transistor, and the drain of the first transistor is electrically connected The source of the fifth transistor and the drain of the second transistor are electrically connected to the source of the sixth transistor; the gate of the third transistor is electrically connected to the gate of the fifth transistor. The gates of the four transistors are electrically connected to the gates of the sixth transistor, the drains of the third transistors are electrically connected to the drains of the fifth transistors, and the drains of the fourth transistors are electrically connected to the sixth transistors. The drain of The gate electrode of the third transistor and the gate electrode of the sixth transistor are also electrically connected to the first output terminal of the comparison circuit; the gate electrode of the third transistor, the gate electrode of the fifth transistor, the gate electrode of the fourth transistor The drain and the drain of the sixth transistor are also electrically connected to the second output terminal of the comparison circuit.

In the above solution, the reset unit includes: a seventh transistor, an eighth transistor and a ninth transistor; the switch unit includes: a tenth transistor; the gate of the seventh transistor, the gate of the eighth transistor, The gate electrode of the ninth transistor and the gate electrode of the tenth transistor both receive the clock signal; the gate electrode of the third transistor and the gate electrode of the fifth transistor are both electrically connected to the gate electrode of the seventh transistor. The drain, the gate of the fourth transistor and the gate of the sixth transistor are both electrically connected to the drain of the eighth transistor, and the source of the seventh transistor and the source of the eighth transistor are both electrically connected. The power terminal is electrically connected; the drain of the third transistor and the drain of the fifth transistor are both electrically connected to the source of the ninth transistor, and the drain of the fourth transistor and the sixth transistor are electrically connected. The drains of the ninth transistor are both electrically connected to the drain of the ninth transistor; the source of the tenth transistor is electrically connected to the ground terminal; the sources of the first transistor and the source of the second transistor are both electrically connected to the The drain of the tenth transistor.

Embodiments of the present disclosure also provide a data receiving circuit. The data receiving circuit includes M levels of the data sampling circuit described in the above solution; the data receiving circuit also includes: M levels of decision feedback equalization circuit; M is greater than 1. A positive integer; the data input terminals of the M-level decision feedback equalization circuits all receive initial data signals; the data input terminals of the data sampling circuits at each level are electrically connected to the output ends of the decision feedback equalization circuits at each level to correspond to receiving each The first data of each stage and the second data of each stage; the feedback input terminal of each stage of the decision feedback equalization circuit is electrically connected to the first output terminal of the data sampling circuit of M stages to receive M first output signals; M The first output signal serves as the feedback signal of each stage of the decision feedback equalization circuit.

An embodiment of the present disclosure also provides a memory, which includes the data sampling circuit described in the above solution.

In the above solution, the adjustment signal received by the data sampling circuit is the ZQ calibration signal generated by the ZQ calibration circuit in the memory.

In the above solution, the adjustment signal received by the data sampling circuit is the setting signal of the mode register in the memory.

In the above solution, the adjustment signal received by the data sampling circuit is the test code set in the test mode.

It can be seen that the embodiment of the present disclosure provides a data sampling circuit, a data receiving circuit and a memory. The data sampling circuit includes a comparison circuit and an adjustable driving circuit. Wherein, the comparison circuit is configured to receive the first data, the second data and the clock signal, respond to the clock signal, compare the first data and the second data, and output the comparison result signal; the adjustable drive circuit is electrically connected to the comparison The circuit is configured to receive the comparison result signal and the adjustment signal, drive the comparison result signal, and output the first output signal; the threshold voltage of the adjustable driving circuit is controlled by the adjustment signal. In this way, the adjustable drive circuit can adjust its threshold voltage according to the adjustment signal to avoid glitches in the first output signal it outputs, thereby ensuring signal stability and avoiding errors.

Description of drawings

Figure 1 is a schematic structural diagram of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 2 is a schematic structural diagram 2 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 3 is a signal schematic diagram 1 of the data sampling circuit provided by an embodiment of the present disclosure;

Figure 4 is a second signal schematic diagram of the data sampling circuit provided by an embodiment of the present disclosure;

Figure 5 is a signal diagram 3 of the data sampling circuit provided by an embodiment of the present disclosure;

Figure 6 is a signal diagram 4 of the data sampling circuit provided by an embodiment of the present disclosure;

Figure 7 is a schematic structural diagram three of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 8 is a schematic structural diagram 4 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 9 is a schematic structural diagram 5 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 10 is a schematic structural diagram 6 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 11 is a schematic structural diagram 7 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 12 is a schematic structural diagram 8 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 13 is a schematic structural diagram 9 of a data sampling circuit provided by an embodiment of the present disclosure;

Figure 14 is a signal diagram 5 of the data sampling circuit provided by an embodiment of the present disclosure;

Figure 15 is a schematic structural diagram of a data receiving circuit provided by an embodiment of the present disclosure;

Figure 16 is a schematic structural diagram 2 of a data receiving circuit provided by an embodiment of the present disclosure;

Figure 17 is a signal schematic diagram 1 of the data receiving circuit provided by an embodiment of the present disclosure;

Figure 18 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated below in conjunction with the accompanying drawings and examples. The described embodiments should not be regarded as limiting the present disclosure. Those of ordinary skill in the art will All other embodiments obtained without creative efforts belong to the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

If a similar description of "first/second" appears in the invention document, add the following explanation. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not mean Regarding the specific ordering of objects, it is understood that "first\second\third" may interchange the specific order or sequence where permitted, so that the embodiments of the disclosure described here can be used in other ways than those shown in the figures here. may be performed in any order other than that shown or described.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

FIG. 1 is an optional structural schematic diagram of a data sampling circuit provided by an embodiment of the present disclosure. As shown in FIG. 1 , the data sampling circuit 60 includes a comparison circuit 10 and an adjustable driving circuit 20 . The comparison circuit 10 is configured to receive the first data Sum_p, the second data Sum_n and the clock signal DQS, compare the first data Sum_p and the second data Sum_n in response to the clock signal DQS, and output a comparison result signal Com. The adjustable drive circuit 20 is electrically connected to the comparison circuit 10; the adjustable drive circuit 20 is configured to receive the comparison result signal Com and the adjustment signal CODE, drive the comparison result signal Com, and output the first output signal Out_1; the adjustable drive circuit 20 The threshold voltage is controlled by the adjustment signal CODE.

In the embodiment of the present disclosure, the threshold voltage of the adjustable drive circuit 20 is controlled by the adjustment signal CODE. Therefore, the adjustable drive circuit 20 can adjust its threshold voltage according to the adjustment signal CODE to avoid the occurrence of the first output signal Out_1 output by it. Glitch, thereby ensuring the stability of the signal and avoiding errors.

In some embodiments of the present disclosure, with reference to FIGS. 1 and 2 , the comparison result signal Com includes: a first result signal Com_A and a second result signal Com_B. The first output signal Out_1 includes: a first output sub-signal Out_A and a second output sub-signal Out_B. The adjustable driving circuit 20 includes: a first controllable inverter INV1 and a second controllable inverter INV2.

The first controllable inverter INV1 is configured to receive the first result sub-signal Com_A and the adjustment signal CODE, adjust the threshold voltage of the first controllable inverter INV1 according to the adjustment signal CODE, and output the first output sub-signal Out_A. The second controllable inverter INV2 is configured to receive the second result sub-signal Com_B and the adjustment signal CODE, adjust the threshold voltage of the second controllable inverter INV2 according to the adjustment signal CODE, and output the second output sub-signal Out_B.

In the embodiment of the present disclosure, the comparison circuit 10 shown in FIG. 1 can compare the first data Sum_p and the second data Sum_n in response to the clock signal DQS, and output the first result signal Com_A and the second result signal Com_B. The waveforms of the first result signal Com_A and the second result signal Com_B can reflect the voltage magnitude relationship between the first data Sum_p and the second data Sum_n. The waveforms of the first result signal Com_A and the second result signal Com_B may be as shown in Figure 3 or Figure 4 .

Combining Figures 1 and 3, when the clock signal DQS is at a high level, the comparison circuit 10 compares the first data Sum_p and the second data Sum_n. If the voltage of the first data Sum_p is less than the voltage of the second data Sum_n, the first result is The sub-signal Com_A drops from the high level briefly and then rises to the high level again, while the second result sub-signal Com_B drops from the high level to the low level. Here, before comparing the first data Sum_p and the second data Sum_n, the level of the output terminal of the comparison circuit 10 is reset to a high level. That is to say, during the comparison process, the first result sub-signal Com_A and The initial levels of the second result sub-signals Com_B are all high levels. At the same time, there will be transistor capacitance and some parasitic capacitance in the comparison circuit 10, which will cause the level of the first result signal Com_A to temporarily drop due to the capacitive coupling effect.

Correspondingly, with reference to Figures 1 and 4, when the clock signal DQS is at a high level, the comparison circuit 10 compares the first data Sum_p and the second data Sum_n. If the voltage of the first data Sum_p is greater than the voltage of the second data Sum_n, then The second result signal Com_B briefly drops from the high level and then rises to the high level again, while the first result signal Com_A drops from the high level to the low level.

In the embodiment of the present disclosure, combined with Figure 2 and Figure 3, if the first result sub-signal Com_A drops from high level briefly and then rises to high level again, there is a risk of glitches appearing in the first output sub-signal Out_A, that is, the first output sub-signal Out_A An output sub-signal Out_A may have a brief level mutation during the brief decline of the first result sub-signal Com_A. Correspondingly, combining Figure 2 and Figure 4, if the second result sub-signal Com_B drops from high level briefly and then rises to high level again, there is a risk of glitches appearing in the second output sub-signal Out_B, that is, the second output sub-signal Out_B The signal Out_B may have a brief level mutation during the brief decline of the second resultant signal Com_B. The first controllable inverter INV1 and the second controllable inverter INV2 can both adjust their threshold voltages according to the adjustment signal CODE. In this way, the occurrence of the first output sub-signal Out_A and the second output sub-signal Out_B can be avoided. Risk of burrs.

Figures 5 and 6 take a brief drop in the waveform of the first result sub-signal Com_A as an example to illustrate the impact of the threshold voltage Vm1 of the first controllable inverter on the waveform of the first output sub-signal Out_A. The situation in which the waveform of the second resultant signal Com_B drops temporarily can be understood with reference to Figures 5 and 6 .

Combining Figures 2 and 5, when the first resultant signal Com_A has a briefly declining waveform, if the threshold voltage Vm1 of the first controllable inverter INV1 is lower than the lowest voltage at which the first resultant signal Com_A drops, then The first output sub-signal Out_A remains low (that is, no glitch occurs). Combining Figure 2 and Figure 6, when the first result signal Com_A has a briefly declining waveform, if the threshold voltage Vm1 of the first controllable inverter INV1 is higher than the lowest voltage at which the first result signal Com_A drops, then A brief high level appears in the first output sub-signal Out_A (that is, a glitch appears).

It can be understood that the first controllable inverter and the second controllable inverter can adjust their own threshold voltages according to the adjustment signal to avoid burrs in the first output sub-signal and the second output sub-signal they output. , ensuring the stability of the signal and avoiding errors.

In some embodiments of the present disclosure, referring to Figure 7 or Figure 8, the adjustment signal includes: N adjustment sub-signals CODE<N-1:0>; the first controllable inverter INV1 includes: the first PMOS tube MP1, The first NMOS transistor MN1 and N first control units 201; N is a positive integer. The gate of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 and the first terminals of the N first control units 201 are all electrically connected to the input terminal IN of the first controllable inverter INV1. The first PMOS transistor The drain of MP1, the drain of the first NMOS transistor MN1 and the second terminals of the N first control units 201 are all electrically connected to the output terminal OUT of the first controllable inverter INV1. The source of the first PMOS transistor MP1 is electrically connected to the power terminal, and the source of the first NMOS transistor MN1 is electrically connected to the ground terminal. The control terminals of the N first control units 201 receive N regulator signals CODE<N-1:0> one by one, and the third terminals of the N first control units 201 are all electrically connected to the ground terminal or the power terminal.

In the embodiment of the present disclosure, each first control unit 201 is configured to be turned on or off under the control of the corresponding adjustment sub-signal to adjust the threshold voltage of the first controllable inverter. That is to say, under the control of the N regulator signals CODE<N-1:0>, some of the N first control units 201 will be turned on and the other part will be turned off, so that the first controllable inverter The threshold voltage is adjusted to the corresponding value. In this way, the threshold voltage of the first controllable inverter can be adjusted to avoid glitches in the first output sub-signal, ensuring signal stability and avoiding errors.

In some embodiments of the present disclosure, the second controllable inverter includes: a second PMOS transistor, a second NMOS transistor and N second control units; N is a positive integer. The gate of the second PMOS transistor, the gate of the second NMOS transistor and the first terminals of the N second control units are all electrically connected to the input terminal of the second controllable inverter. The drains of the two NMOS transistors and the second terminals of the N second control units are electrically connected to the output terminal of the second controllable inverter. The source of the second PMOS transistor is electrically connected to the power terminal, and the source of the second NMOS transistor is electrically connected to the ground terminal. The control terminals of the N second control units receive N adjuster signals one by one, and the third terminals of the N second control units are all electrically connected to the ground terminal or the power terminal.

It should be noted that the structure of the second controllable inverter can refer to the structure of the first controllable inverter INV1 shown in Figure 7 or Figure 8, wherein the second PMOS transistor corresponds to the first PMOS transistor MP1, and the second The NMOS transistor corresponds to the first NMOS transistor MN1, and the second control unit corresponds to the first control unit 201.

In the embodiment of the present disclosure, each second control unit is configured to be turned on or off under the control of the corresponding adjustment sub-signal to adjust the threshold voltage of the second controllable inverter. That is to say, under the control of N regulator signals, some of the N second control units will be turned on and the other part will be turned off, so that the threshold voltage of the second controllable inverter is adjusted to the corresponding value. . In this way, the threshold voltage of the second controllable inverter can be adjusted to avoid glitches in the second output sub-signal, ensuring signal stability and avoiding errors.

In some embodiments of the present disclosure, referring to FIG. 9 or FIG. 10 , each first control unit 201 includes: a first adjustment transistor Mc1 and a second adjustment transistor Mc2. The gate of the first adjustment transistor Mc1 serves as the corresponding first terminal of the first control unit 201, that is, the gate of the first adjustment transistor Mc1 is electrically connected to the input terminal IN of the first controllable inverter INV1. The drain of the first adjustment transistor Mc1 serves as the corresponding second terminal of the first control unit 201, that is, the drain of the first adjustment transistor Mc1 is electrically connected to the output terminal OUT of the first controllable inverter INV1. The gate of the second adjustment transistor Mc2 serves as the corresponding control terminal of the first control unit 201, that is, the gate of the second adjustment transistor Mc2 receives the adjustment sub-signal. The source of the second adjustment transistor Mc2 serves as the corresponding third terminal of the first control unit 201, that is, the source of the second adjustment transistor Mc2 is electrically connected to the ground terminal or the power terminal. The source of the first adjustment transistor Mc1 is electrically connected to the drain of the second adjustment transistor Mc2.

In some embodiments of the present disclosure, each second control unit includes: a third regulation transistor and a fourth regulation transistor. The gate of the third regulation transistor serves as the first terminal of the corresponding second control unit, that is, the gate of the third regulation transistor is electrically connected to the input terminal of the second controllable inverter. The drain of the third adjustment transistor serves as the second terminal of the corresponding second control unit, that is, the drain of the third adjustment transistor is electrically connected to the output end of the second controllable inverter. The gate of the fourth adjustment transistor serves as the control terminal of the corresponding second control unit, that is, the gate of the fourth adjustment transistor receives the adjustment sub-signal. The source of the fourth adjustment transistor serves as the third terminal of the corresponding second control unit, that is, the source of the fourth adjustment transistor is electrically connected to the ground terminal or the power terminal. The source of the third adjustment transistor is electrically connected to the drain of the fourth adjustment transistor.

It should be noted that the structure of the second control unit may refer to the structure of the first control unit 201 shown in FIG. 9 or FIG. 10 , where the third adjustment transistor corresponds to the first adjustment transistor Mc1 and the fourth adjustment transistor corresponds to the second adjustment transistor Mc1. Transistor Mc2.

In some embodiments of the present disclosure, the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all NMOS transistors, and the sources of the second adjustment transistor and the source of the fourth adjustment transistor are both electrically connected. Connect the ground terminal.

In the embodiment of the present disclosure, referring to FIG. 9 , the first adjustment transistor Mc1 and the second adjustment transistor Mc2 are both NMOS transistors, and the source of the second adjustment transistor Mc2 is electrically connected to the ground. When any regulator signal is "1" (ie, high level), the corresponding second regulator transistor Mc2 will be in a conductive state, that is, the corresponding first control unit 201 is turned on; when any regulator signal is " 0" (ie, low level), the corresponding second adjustment transistor Mc2 will be in a cut-off state, that is, the corresponding first control unit 201 will be cut off.

In the embodiment of the present disclosure, when the third adjustment transistor and the fourth adjustment transistor are both NMOS transistors, reference can be made to the circuit structure shown in FIG. 9 , where the third adjustment transistor corresponds to the first adjustment transistor Mc1 and the fourth adjustment transistor corresponds to the first adjustment transistor Mc1. Two regulating transistors Mc2.

In some embodiments of the present disclosure, the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all PMOS transistors, and the source electrode of the second adjustment transistor and the source electrode of the fourth adjustment transistor are both electrically connected. Connect the power terminal.

Referring to Figure 10, the first adjustment transistor Mc1 and the second adjustment transistor Mc2 are both PMOS transistors, and the source of the second adjustment transistor Mc2 is electrically connected to the power terminal. When any regulator signal is "0" (ie, low level), the corresponding second regulator transistor Mc2 will be in a conductive state, that is, the corresponding first control unit 201 is turned on; when any regulator signal is " 1" (ie, high level), the corresponding second adjustment transistor Mc2 will be in a cut-off state, that is, the corresponding first control unit 201 will be cut off.

In the embodiment of the present disclosure, when the third adjustment transistor and the fourth adjustment transistor are both PMOS transistors, reference can be made to the circuit structure shown in Figure 10, wherein the third adjustment transistor corresponds to the first adjustment transistor Mc1, and the fourth adjustment transistor corresponds to the Two regulating transistors Mc2.

In some embodiments of the present disclosure, among the N first control units, the equivalent device size of the i-th first control unit is set to 2 ^i-1 times the equivalent device size of the 1-th first control unit. . Correspondingly, among the N second control units, the equivalent device size of the i-th second control unit is set to 2 ^i-1 times the equivalent device size of the first second control unit. Among them, i is greater than or equal to 1, and less than or equal to N.

In the embodiment of the present disclosure, the equivalent device size of the first/second control unit refers to the device size equivalently calculated by taking the first/second control unit as a whole. Here, the device size may be the width of the MOS tube. Length ratio, that is, the ratio of channel width to channel length. For example, referring to Figure 9 or Figure 10, the first control unit 201 includes a first adjustment transistor Mc1 and a second adjustment transistor Mc2 connected in series, that is, the source of the first adjustment transistor Mc1 is electrically connected to the drain of the second adjustment transistor Mc2. , then, the equivalent device size of the first control unit 201 is the device size equivalently calculated by taking the series-connected first adjustment transistor Mc1 and the second adjustment transistor Mc2 as a whole.

In the embodiment of the present disclosure, the total value of the equivalent device size of the first/second control unit will affect the threshold voltage of the first/second controllable inverter, and the total value of different equivalent device sizes corresponds to different threshold voltages. Here, the total value of the equivalent device sizes of the first/second control units refers to the sum of the equivalent device sizes of all the turned-on first/second control units. Therefore, by controlling the conduction status of the first/second control unit, the total value of the equivalent device size of the first/second control unit can be controlled, thereby adjusting the threshold voltage of the first/second controllable inverter.

In the embodiment of the present disclosure, the equivalent device size of the i-th first/second control unit is set to 2 ^i-1 times the equivalent device size of the 1st first/second control unit, that is, The equivalent device sizes of the N first/second control units are set in sequence according to a multiple relationship of 1, 2, 4, 8..., so that more total equivalent device sizes can be combined. Examples are given below.

Assume that the smallest unit quantity of equivalent device size is a. If the equivalent device size of the i-th first/second control unit among the N first/second control units is set to 2 ^i-1 times of a, then, by controlling the N first/second control units The conduction of the unit can combine the total size of 2 ^N+1 equivalent devices, that is, 0~(2 ^N+1 -1)a. If the equivalent device size setting of each of the N first/second control units is set to a, then by controlling the conduction of the N first/second control units, Only N+1 equivalent device size total values can be combined, that is, 0~N*a.

It can be understood that since different total equivalent device sizes correspond to different threshold voltages, more total equivalent device sizes means a wider adjustment range for the threshold voltage. By setting the equivalent device sizes of the first/second control unit in the manner provided by the embodiments of the present disclosure, more total equivalent device sizes can be combined, thereby expanding the adjustment range of the threshold voltage.

In some embodiments of the present disclosure, as shown in FIG. 11 , the data sampling circuit further includes: a latch unit 30 . The latch unit 30 is electrically connected to the comparison circuit; the latch unit 30 is configured to receive the comparison result signal, latch the comparison result signal and output it as the second output signal Out_2; the latch unit 30 includes an SR latch 301.

In the embodiment of the present disclosure, referring to Figure 11, the two input terminals of the SR latch 301 respectively receive the first result sub-signal Com_A and the second result sub-signal Com_B in the comparison result signal, and the SR latch 301 converts the comparison result signal After latching, it is output through the inverter as the second output signal Out_2.

In some embodiments of the present disclosure, as shown in FIG. 12 , the comparison circuit 10 includes: an input unit 101 , a comparison output unit 102 , a reset unit 103 and a switch unit 104 . The input unit 101 is configured to receive the first data Sum_p and the second data Sum_n, and generate a differential signal according to the first data Sum_p and the second data Sum_n during the sampling stage. The comparison output unit 102 is electrically connected to the input unit 101; the comparison output unit 102 is configured to obtain a differential signal, amplify and latch the differential signal to output comparison result signals Com_A and Com_B. The reset unit 103 is electrically connected to the comparison output unit 102; the reset unit 103 is configured to receive the clock signal DQS and reset the comparison output unit 102 during the reset phase. The switch unit 104 is electrically connected to the input unit 101; the switch unit 104 is configured to receive the clock signal DQS and control the working state of the comparison circuit 10 according to the clock signal DQS.

In some embodiments of the present disclosure, as shown in FIG. 13 , the input unit 101 includes: a first transistor M1 and a second transistor M2. The comparison output unit 102 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. Among them, the gate of the first transistor M1 receives the first data Sum_p, and the gate of the second transistor M2 receives the second data Sum_n; the source of the first transistor M1 is electrically connected to the source of the second transistor M2; The drain of the fifth transistor M5 is electrically connected to the source of the fifth transistor M5; the drain of the second transistor M2 is electrically connected to the source of the sixth transistor M6; the gate of the third transistor M3 is electrically connected to the gate of the fifth transistor M5; the fourth transistor M4 The gate of the sixth transistor M6 is electrically connected to the gate; the drain of the third transistor M3 is electrically connected to the drain of the fifth transistor M5; the drain of the fourth transistor M4 is electrically connected to the drain of the sixth transistor M6; the third transistor M3 is electrically connected to the drain of the fifth transistor M5. The source electrode of M3 and the source electrode of the fourth transistor M4 are both electrically connected to the power supply terminal; the drain electrode of the third transistor M3, the drain electrode of the fifth transistor M5, the gate electrode of the fourth transistor M4 and the gate electrode of the sixth transistor M6 are also connected Electrically connected to the first output terminal of the comparison circuit 10; the gate electrode of the third transistor M3, the gate electrode of the fifth transistor M5, the drain electrode of the fourth transistor M4 and the drain electrode of the sixth transistor M6 are also electrically connected to the comparison circuit 10 the second output terminal.

Continuing to refer to FIG. 13 , the reset unit 103 includes: a seventh transistor M7 , an eighth transistor M8 , and a ninth transistor M9 . The switching unit 104 includes a tenth transistor M10. Among them, the gate of the seventh transistor M7, the gate of the eighth transistor M8, the gate of the ninth transistor M9 and the gate of the tenth transistor M10 all receive the clock signal DQS; the gate of the third transistor M3 and the fifth transistor The gate electrode of M5 is both electrically connected to the drain electrode of the seventh transistor M7; the gate electrodes of the fourth transistor M4 and the gate electrode of the sixth transistor M6 are both electrically connected to the drain electrode of the eighth transistor M8; the source electrode of the seventh transistor M7 and the gate electrode of the sixth transistor M6 are both electrically connected. The sources of the eight transistors M8 are all electrically connected to the power supply terminal; the drains of the third transistor M3 and the drains of the fifth transistor M5 are electrically connected to the sources of the ninth transistor M9; the drains of the fourth transistor M4 and the sixth transistor M6 are electrically connected. The drains of the first transistor M1 and the source of the second transistor M2 are both electrically connected to the drain of the tenth transistor M10. pole.

In the embodiment of the present disclosure, the working process of the comparison circuit 10 shown in FIG. 13 is divided into four stages, namely the reset stage, the sampling stage, the regeneration stage and the decision-making stage. FIG. 14 is an operation timing diagram of the comparison circuit 10. The operation process of the comparison circuit 10 will be described below in conjunction with FIG. 14.

The reset phase is before time t1. At this time, the clock signal DQS is low level, the tenth transistor M10 is triggered into the cut-off state by the clock signal DQS, and the input unit 101 and the comparison output unit 102 stop working; at the same time, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 is triggered into a conductive state by the clock signal DQS, and the reset unit 103 works to keep the first result signal Com_A output by the first output terminal and the second result signal Com_B output by the second output terminal at a high level.

The sampling stage is from time t1 to time t2. At the beginning of the sampling phase (i.e., time t1), the clock signal DQS changes to a high level. At this time, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are triggered by the clock signal DQS into the cut-off state, and the reset unit 103 stops. work; at the same time, the tenth transistor M10 is triggered into a conductive state by the clock signal DQS, the input unit 101 and the comparison output unit 102 work, and the first data Sum_p and the second data Sum_n are input to the comparison circuit 10 . Then, the first result signal Com_A and the second result signal Com_B start to fall from the high level. By the end of the sampling phase (i.e., time t2), the third transistor M3 is triggered into the conductive state by the low level of the second result signal Com_B, and the fourth transistor M4 is triggered into the conductive state by the low level of the first result signal Com_A. communication status.

It should be noted that during the sampling phase, since the voltages of the first data Sum_p and the second data Sum_n are different (that is, there is a voltage difference), the voltages of the first result signal Com_A and the second result signal Com_B decrease at different rates. Thereby, there is a voltage difference between the first result signal Com_A and the second result signal Com_B. In FIG. 14, since the voltage of the first data Sum_p is lower than the voltage of the second data Sum_n, the voltage of the second result signal Com_B decreases faster than the voltage of the first result signal Com_A, so that the second result signal Com_B The voltage of Com_B is lower than the voltage of the first result signal Com_A. Correspondingly, when the voltage of the first data Sum_p is higher than the voltage of the second data Sum_n, the voltage of the first result signal Com_A will decrease faster than the voltage of the second result signal Com_B. The voltage will be lower than the voltage of the second result signal Com_B.

The regeneration stage is from time t2 to time t3. At the beginning of the regeneration phase (i.e., time t2), the third transistor M3 and the fourth transistor M4 are triggered into a conductive state. The third transistor M3 and the fourth transistor M4 form a cross-coupling circuit, which acts through positive feedback. The voltage difference formed between the first resultant signal Com_A and the second resultant signal Com_B during the sampling phase is amplified. At the same time, the first transistor M1 and the second transistor M2 sense the differential input level (ie, the voltage difference between the first data Sum_p and the second data Sum_n) and generate a differential drain current to charge Vmidp and Vmidn relative to Input polarity has large signal swing. By the end of the regeneration phase (i.e., time t3), the voltage difference between the first result signal Com_A and the second result signal Com_B is amplified to a sufficient extent, so that the first result signal Com_A and the second result signal Com_B Com_B is regenerated into high level and low level respectively. If the voltage of the second data Sum_n is higher than the voltage of the first data Sum_p, as shown in Figure 14, the first result signal Com_A is regenerated to a high level, and the second result signal Com_B is regenerated to a low level; correspondingly , if the voltage of the first data Sum_p is higher than the voltage of the second data Sum_n, the first result sub-signal Com_A is regenerated to a low level, and the second result sub-signal Com_B is regenerated to a high level.

The decision-making stage is from time t3 to time t4. The comparison output unit 102 latches the levels of the first result sub-signal Com_A and the second result sub-signal Com_B to maintain the levels, and outputs the latched levels.

At the end of the current working cycle (i.e., time t4), the clock signal DQS switches to low level, the tenth transistor M10 is triggered by the clock signal DQS into the cut-off state, and the input unit 101 and the comparison output unit 102 stop working; at the same time, the seventh transistor M7 and the eighth transistor M8 are triggered into a conductive state by the clock signal DQS, and the reset unit 103 operates to raise the voltages of the first output terminal and the second output terminal of the comparison circuit 10 to a high level again.

It can be seen that the working process of the comparison circuit 10 is to compare the first data Sum_p and the second data Sum_n. If the voltage of the second data Sum_n is greater than the voltage of the first data Sum_p, the output first result sub-signal Com_A is high. level, the output second result sub-signal Com_B is low level; if the voltage of the first data Sum_p is greater than the voltage of the second data Sum_n, the output first result sub-signal Com_A is low level, and the output second result The sub-signal Com_B is high level; based on this, the level relationship of the input signal is determined.

Embodiments of the present disclosure also provide a data receiving circuit. The data receiving circuit includes: an M-level data sampling circuit and an M-level decision feedback equalization circuit, where M is a positive integer greater than 1. Among them, the data input terminals of the M-level decision feedback equalization circuit all receive the initial data signal; the data input end of each level of data sampling circuit is electrically connected to the output end of each level of decision feedback equalization circuit to correspondingly receive the first data and The second data of each level; each level of decision feedback equalization circuit, the feedback input end of which is electrically connected to the first output end of the M level data sampling circuit to receive M first output signals; the M first output signals serve as each level of decision feedback Feedback signal from the equalization circuit.

FIG. 15 illustrates the data receiving circuit in the case of M=4. As shown in Figure 15, the data receiving circuit 80 includes: a 4-level data sampling circuit 60 and a 4-level decision feedback equalization circuit 70. The first output end of the 4-level data sampling circuit 60 correspondingly outputs the first output signals DQ_I, DQ_IB, DQ_Q and DQ_QB; and the four feedback input terminals T1, T2, T3 and T4 of each stage of the decision feedback equalization circuit 70 receive the first output signals DQ_I, DQ_IB, DQ_Q and DQ_QB as their feedback signals.

Specifically, for the first-level decision feedback equalization circuit 70, its first feedback input terminal T1 receives the first output signal DQ_QB output by the fourth-level data sampling circuit, and its second feedback input terminal T2 receives the output of the third-level data sampling circuit. The first output signal DQ_Q, its third feedback input terminal T3 receives the first output signal DQ_IB output by the second-level data sampling circuit, and its fourth feedback input terminal T4 receives the first output signal DQ_I output by the first-level data sampling circuit ; For the second-level decision feedback equalization circuit 70, its first feedback input terminal T1 receives the first output signal DQ_I output by the first-level data sampling circuit, and its second feedback input terminal T2 receives the first output signal DQ_I output by the fourth-level data sampling circuit. An output signal DQ_QB, its third feedback input terminal T3 receives the first output signal DQ_Q output by the third-level data sampling circuit, and its fourth feedback input terminal T4 receives the first output signal DQ_IB output by the second-level data sampling circuit; for The first feedback input terminal T1 of the third-level decision feedback equalization circuit 70 receives the first output signal DQ_IB output by the second-level data sampling circuit, and its second feedback input terminal T2 receives the first output output by the first-level data sampling circuit. Signal DQ_I, its third feedback input terminal T3 receives the first output signal DQ_QB output by the fourth-level data sampling circuit, and its fourth feedback input terminal T4 receives the first output signal DQ_Q output by the third-level data sampling circuit; for the fourth The first feedback input terminal T1 of the first-stage decision feedback equalization circuit 70 receives the first output signal DQ_Q output by the third-stage data sampling circuit, and its second feedback input terminal T2 receives the first output signal DQ_IB output by the second-stage data sampling circuit. , its third feedback input terminal T3 receives the first output signal DQ_I output by the first-level data sampling circuit, and its fourth feedback input terminal T4 receives the first output signal DQ_QB output by the fourth-level data sampling circuit.

It should be noted that during data transmission, there is Inter-Symbol Interference (ISI). Inter-symbol crosstalk is due to the unsatisfactory overall system transmission characteristics, which causes the waveforms of the signals at the previous and previous time nodes to be distorted and broadened, and causes the previous waveform to have a long tail, which spreads to the sampling time of the signal at the current time node, thereby affecting the current time node. The signal is judged to cause interference. For example, a symbol originally judged to be a low level may be judged to be a high level due to the interference of inter-symbol crosstalk, and a symbol originally judged to be a high level may be judged to be a high level due to the interference of inter-symbol crosstalk. Low level, causing signal distortion.

Furthermore, the decision feedback equalization circuit can reduce or even eliminate the impact of inter-symbol crosstalk through feedback. For example, the decision feedback equalization circuit 70 shown in FIG. 15 can adjust its output data signal according to each first output signal received at its feedback input terminal, thereby reducing or even eliminating the impact of inter-code crosstalk. Here, the number of feedback signals received by the decision feedback equalization circuit is not limited to the four shown in Figure 15. The higher the frequency of data transmission, the more feedback signals are needed.

16 and 17 respectively show the clock signal generation circuit and the waveform of the generated clock signal. 15 to 17 , the clock signal generation circuit 50 generates clock signals DQS_0, DQS_90, DQS_180 and DQS_270, and the 4-level data sampling circuit 60 receives the clock signals DQS_0, DQS_90, DQS_180 and DQS_270 respectively. Since the phases of the clock signals DQS_0, DQS_90, DQS_180 and DQS_270 are sequentially different by 90°, and the data sampling circuit 60 outputs its first output signal in response to the clock signal, the first output signal output by the 4-level data sampling circuit 60 The phases of DQ_I, DQ_IB, DQ_Q and DQ_QB are also 90° different in sequence.

It can be understood that the decision feedback equalization circuit can reduce or even eliminate the impact of inter-symbol crosstalk through feedback, and improve the accuracy of transmitted data. At the same time, since the decision feedback equalization circuit uses the first output signal output by the data sampling circuit as its feedback signal, and the adjustable drive circuit in the data sampling circuit avoids glitches in the first output signal by adjusting the threshold voltage, this ensures The accuracy of the feedback signal received by the feedback equalization circuit is determined to avoid errors in the process of eliminating inter-symbol crosstalk, thereby further improving the accuracy of the transmitted data.

An embodiment of the present disclosure also provides a memory. As shown in FIG. 18 , the memory 90 includes a data sampling circuit 60 . The adjustable driving circuit in the data sampling circuit 60 receives the adjustment signal and adjusts its threshold voltage according to the adjustment signal.

In some embodiments of the present disclosure, referring to FIG. 18 , the adjustment signal received by the data sampling circuit 60 is a ZQ calibration signal generated by the ZQ calibration circuit in the memory 90 .

In some embodiments of the present disclosure, referring to FIG. 18 , the adjustment signal received by the data sampling circuit 60 is the setting signal of the mode register in the memory 90 .

In some embodiments of the present disclosure, referring to FIG. 18 , the adjustment signal received by the data sampling circuit 60 is a test code set in the test mode, that is, the adjustment signal received by the data sampling circuit 60 is a signal external to the memory 90 .

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a data sampling circuit, a data receiving circuit and a memory. The data sampling circuit includes a comparison circuit and an adjustable driving circuit. Wherein, the comparison circuit is configured to receive the first data, the second data and the clock signal, respond to the clock signal, compare the first data and the second data, and output the comparison result signal; the adjustable drive circuit is electrically connected to the comparison The circuit is configured to receive the comparison result signal and the adjustment signal, drive the comparison result signal, and output the first output signal; the threshold voltage of the adjustable driving circuit is controlled by the adjustment signal. In this way, the adjustable drive circuit can adjust its threshold voltage according to the adjustment signal to avoid glitches in the first output signal it outputs, thereby ensuring signal stability and avoiding errors.

Claims

A data sampling circuit, the data sampling circuit includes:

a comparison circuit configured to receive first data, second data and a clock signal, compare the first data and the second data in response to the clock signal, and output a comparison result signal;

An adjustable drive circuit is electrically connected to the comparison circuit, and is configured to receive the comparison result signal and the adjustment signal, drive the comparison result signal, and output a first output signal; the threshold voltage of the adjustable drive circuit is affected by controlled by the adjustment signal.
The data sampling circuit according to claim 1, wherein the comparison result signal includes: a first result sub-signal and a second result sub-signal; the first output signal includes: a first output sub-signal and a second output sub-signal. signal; the adjustable drive circuit includes:

A first controllable inverter configured to receive the first result signal and the adjustment signal, adjust the threshold voltage of the first controllable inverter according to the adjustment signal, and output the first Output sub-signal;

A second controllable inverter configured to receive the second result signal and the adjustment signal, adjust the threshold voltage of the second controllable inverter according to the adjustment signal, and output the second Output sub-signal.
The data sampling circuit according to claim 2, wherein the adjustment signal includes: N adjustment sub-signals; the first controllable inverter includes: a first PMOS tube, a first NMOS tube and N first Control unit; N is a positive integer;

The gate of the first PMOS transistor, the gate of the first NMOS transistor and the first terminals of the N first control units are all electrically connected to the input terminal of the first controllable inverter, so The drain of the first PMOS transistor, the drain of the first NMOS transistor and the second terminals of the N first control units are all electrically connected to the output terminal of the first controllable inverter; The source of the first PMOS tube is electrically connected to the power terminal, and the source of the first NMOS tube is electrically connected to the ground terminal; the control terminals of the N first control units receive the N adjuster signals one by one, N The third terminals of each of the first control units are electrically connected to the ground terminal or the power terminal;

Each of the first control units is configured to be turned on or off under the control of a corresponding adjustment sub-signal to adjust the threshold voltage of the first controllable inverter.
The data sampling circuit according to claim 3, wherein the second controllable inverter includes: a second PMOS tube, a second NMOS tube and N second control units;

The gate of the second PMOS transistor, the gate of the second NMOS transistor and the first terminals of the N second control units are all electrically connected to the input terminal of the second controllable inverter, so The drain of the second PMOS transistor, the drain of the second NMOS transistor and the second terminals of the N second control units are all electrically connected to the output terminal of the second controllable inverter; The source of the second PMOS tube is electrically connected to the power terminal, and the source of the second NMOS tube is electrically connected to the ground terminal; the control terminals of the N second control units receive the N adjuster signals one by one, N The third terminals of each of the second control units are electrically connected to the ground terminal or the power terminal;

Each of the second control units is configured to be turned on or off under the control of a corresponding adjustment sub-signal to adjust the threshold voltage of the second controllable inverter.
The data sampling circuit according to claim 4, wherein each of the first control units includes: a first adjustment transistor and a second adjustment transistor;

The gate of the first regulating transistor serves as the first terminal of the corresponding first control unit, the drain of the first regulating transistor serves as the second terminal of the corresponding first control unit, and the gate of the second regulating transistor The terminal serves as the control end of the corresponding first control unit, the source electrode of the second adjustment transistor serves as the third end of the corresponding first control unit, and the source electrode of the first adjustment transistor is electrically connected to the second adjustment transistor. the drain;

Each of the second control units includes: a third regulating transistor and a fourth regulating transistor;

The gate of the third adjustment transistor serves as the first end of the corresponding second control unit, the drain of the third adjustment transistor serves as the second end of the corresponding second control unit, and the gate of the fourth adjustment transistor The terminal serves as the control end of the corresponding second control unit, the source electrode of the fourth adjustment transistor serves as the third end of the corresponding second control unit, and the source electrode of the third adjustment transistor is electrically connected to the fourth adjustment transistor. the drain.
The data sampling circuit according to claim 5, wherein the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all NMOS tubes;

The source electrode of the second adjustment transistor and the source electrode of the fourth adjustment transistor are both electrically connected to the ground terminal.
The data sampling circuit according to claim 5, wherein the first adjustment transistor, the second adjustment transistor, the third adjustment transistor and the fourth adjustment transistor are all PMOS tubes;

The source electrode of the second adjustment transistor and the source electrode of the fourth adjustment transistor are both electrically connected to the power terminal.
The data sampling circuit according to claim 4, wherein,

Among the N first control units, the equivalent device size of the i-th first control unit is set to 2i-1 times the equivalent device size of the 1st first control unit;

Among the N second control units, the equivalent device size of the i-th second control unit is set to 2i-1 times the equivalent device size of the first second control unit; i is greater than or equal to 1, and less than or equal to N.
The data sampling circuit according to claim 1, wherein the data sampling circuit further includes:

A latch unit is electrically connected to the comparison circuit, configured to receive the comparison result signal, latch the comparison result signal and output it as a second output signal; the latch unit includes an SR latch.
The data sampling circuit according to claim 1, wherein the comparison circuit includes:

an input unit configured to receive the first data and the second data, and generate a differential signal according to the first data and the second data during the sampling stage;

a comparison output unit, electrically connected to the input unit, configured to acquire the differential signal, amplify and latch the differential signal to output the comparison result signal;

A reset unit, electrically connected to the comparison output unit, configured to receive the clock signal, and reset the comparison output unit during the reset phase;

A switch unit is electrically connected to the input unit and configured to receive the clock signal and control the working state of the comparison circuit according to the clock signal.
The data sampling circuit according to claim 10, wherein the input unit includes: a first transistor and a second transistor; the comparison output unit includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;

The gate of the first transistor receives the first data, and the gate of the second transistor receives the second data; the source of the first transistor is electrically connected to the source of the second transistor, so The drain of the first transistor is electrically connected to the source of the fifth transistor, and the drain of the second transistor is electrically connected to the source of the sixth transistor;

The gate of the third transistor is electrically connected to the gate of the fifth transistor, the gate of the fourth transistor is electrically connected to the gate of the sixth transistor, and the drain of the third transistor is electrically connected to the gate of the fifth transistor. The drain of the fifth transistor and the drain of the fourth transistor are electrically connected to the drain of the sixth transistor; the source of the third transistor and the source of the fourth transistor are both electrically connected to the power supply terminal;

The drain of the third transistor, the drain of the fifth transistor, the gate of the fourth transistor and the gate of the sixth transistor are also electrically connected to the first output terminal of the comparison circuit; The gate of the third transistor, the gate of the fifth transistor, the drain of the fourth transistor and the drain of the sixth transistor are also electrically connected to the second output terminal of the comparison circuit.
The data sampling circuit according to claim 11, wherein the reset unit includes: a seventh transistor, an eighth transistor and a ninth transistor; the switch unit includes: a tenth transistor;

The gate of the seventh transistor, the gate of the eighth transistor, the gate of the ninth transistor and the gate of the tenth transistor all receive the clock signal;

The gate electrode of the third transistor and the gate electrode of the fifth transistor are both electrically connected to the drain electrode of the seventh transistor, and the gate electrode of the fourth transistor and the gate electrode of the sixth transistor are both electrically connected to each other. The drain of the eighth transistor, the source of the seventh transistor and the source of the eighth transistor are both electrically connected to the power terminal; the drain of the third transistor and the drain of the fifth transistor The source electrode of the ninth transistor is both electrically connected, the drain electrode of the fourth transistor and the drain electrode of the sixth transistor are both electrically connected to the drain electrode of the ninth transistor; the source electrode of the tenth transistor is electrically connected to the source electrode of the ninth transistor. Connected to the ground terminal, the source electrode of the first transistor and the source electrode of the second transistor are both electrically connected to the drain electrode of the tenth transistor.
A data receiving circuit, the data receiving circuit includes M-level data sampling circuits according to any one of claims 1 to 12; the data receiving circuit further includes: M-level decision feedback equalization circuits; M is greater than 1 positive integer;

The data input terminals of the M-level decision feedback equalization circuit all receive initial data signals;

The data input terminal of each stage of the data sampling circuit is electrically connected to the output terminal of the decision feedback equalization circuit of each stage to receive the first data of each stage and the second data of each stage;

The feedback input terminal of each stage of the decision feedback equalization circuit is electrically connected to the first output terminal of the M-stage data sampling circuit to receive M first output signals; the M first output signals serve as the first output signals of each stage. Decision feedback equalization circuit feedback signal.
A memory including the data sampling circuit according to any one of claims 1 to 12.
The memory of claim 14, wherein the adjustment signal received by the data sampling circuit is a ZQ calibration signal generated by a ZQ calibration circuit in the memory.
The memory of claim 14, wherein the adjustment signal received by the data sampling circuit is a setting signal of a mode register in the memory.
The memory according to claim 14, wherein the adjustment signal received by the data sampling circuit is a test code set in a test mode.