CN104718699A - Method and apparatus for an active negative-capacitor circuit - Google Patents

Abstract

The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Description

For the method and apparatus of active negative capacitor circuit

The cross reference of related application

The title that the application applied on September 3rd, 2012 is that the previous U. S. application numbers 13/602,216 of " method and apparatus (Method and Apparatus for an ActiveNegative-Capacitor Circuit to Cancel the input Capacitance of Comparators) for the input capacitance of active negative capacitor circuit for eliminating comparator " has carried out prioity claim.The application is that the U. S. application of the common submission of " for reducing the method and apparatus (Method and Apparatus for Reducing the Clock Kick-Back of ADCComparators While Maintaining Transistor Matching Behavior) of the clock resilience of ADC comparator while keeping transistor to mate behavior " is relevant with the title that on September 3rd, 2012 submits to, and this application and the application are invented by same inventor and be combined in this by reference in full with it.

Background technology

Federal Communications Committee (FCC) in 60GHz frequency range (57GHz to 64GHz) be assigned with bandwidth spectrum.The target of wireless gigabit alliance (WiGig) is the standardization that will support up to this frequency band of the message transmission rate of 7Gbps.The integrated circuit formed in semiconductor element provides high-frequency operation in this millimetre wavelength frequency range.Some in these integrated circuits utilizes complementary metal oxide semiconductors (CMOS) (CMOS), silicon-germanium (SiGe) or GaAs (GaAs) technology to form crystal grain in the designs.Because WiGig transceiver uses digital to analog converter (DAC), the power supply of reduction affects the performance of DAC.

Complementary metal oxide semiconductors (CMOS) (CMOS) is the major technique for building integrated circuit.N-channel transistor and p channel transistor (MOS transistor) as one man reduce in the technology of the channel length of MOS transistor for this use fine rule technology (fine linetechnology).The power supply that a part in the current value of this technology comprises the channel length of 40nm, VDD equals 1.2V and the number of plies are the metal levels of 8 or more.This technology is usual and science and technology is proportional.

CMOS technology gives designer the ability forming very large system level design (being called as SOC (system on a chip) (SOC)) on a tube core.SOC is the complication system with millions of (the if not tens) transistors comprising analog circuit and digital circuit.Analog circuit is pure to be run in analog, and digital circuit pure digi-tal ground runs, and these two kinds of circuit typess can combine the circuit being formed and run under mixed signal pattern.

Such as, digital circuit only uses Digital Logic under its citation form, and some example can be the parts comprising at least one the following: processor, memory, control logic, digital I/O circuit, Reconfigurable logic and/or the hardware be programmed to as hardware emulator operation.Analog circuit only uses analog circuit under its citation form, and some example can be the parts comprising at least one the following: amplifier, oscillator, blender and/or filter.Mixed signal only uses digital circuit and analog circuit under its citation form, and some example can be the parts comprising at least one the following: digital to analog converter (DAC), analog to digital converter (ADC), programmable gain amplifier (PGA), Energy control.Phase-locked loop (PLL) and/or transistor row are domination process, voltage and temperature (PVT).The combination of digital logic component and analog circuit component seems to show to obtain picture mixed signal circuit; And then, personnel as acquainted in this area understand, the example provided is not exhaustive.

When in the adc continuous print analog signal being changed into digit time signal, one of key design parameter of transceiver occurs.Quick flashing ADC uses linear reference voltage source, carries out tap and put on one of Differential Input of many comparators in parallel this linear reference voltage source.The input analogue value is put on another Differential Input simultaneously providing the whole comparators compared very fast.Some key issues can occur in current conversion, comprising: 1) in these comparators and between the coupling of input transistors; 2) the clock resilience from the clock of these comparators enable to input signal; And 3) reduction of bandwidth between PGA and ADC and the bulky capacitor load of this interconnection.

In comparator and between the coupling of transistor use virtual (dummy) transistor, these dummy transistor have been used up valuable semiconductor regions and have been caused the increase of power dissipation due to the conductor length of the increase of data wire and clock line.If do not maintained the coupling of transistor, problem has just become mismatch condition.The bandwidth of ADC is subject to the restriction of input signal, and this input signal drives the input capacitance load of all comparators in parallel and interconnection.This makes the transistor width of the input transistors of comparator to have the upper limit.This transistor width may be inadequate, and cause matching problem to become more serious, and the width increasing transistor exceedes this upper limit and contributes to overcoming mismatch condition but cause the bandwidth of ADC to reduce.Need other scheme to solve mismatch condition, also allow to meet the expectation bandwidth simultaneously.

The clock resilience of the input signal from clock to grid usually by active transistor terminal between capacitive coupling and occur, that is, from the source terminal of MOS transistor and drain terminal to the gate overlap electric capacity of gate terminal.When the width of transistor increases, coupling capacitance increases, and which increases clock resilience.In addition, because the width of transistor increases, the power dissipation of system increases equally.The second aspect of clock resilience carries out timing to the transient performance of circuit between init state and stable state.The internal node of the circuit be timed goes back generated clock resilience in transient period process except the operating delay of increasing circuit.Providing the some solutions overcoming these shortcomings by reducing clock resilience, improving the performance of circuit thus.

The large grid capacitance of MOS transistor and the signal transmission between PGA and ADC can be postponed for the interconnection capacitance of the metal trace of these comparators that are coupled.Signal transmission between PGA and ADC causes path bandwidth to reduce due to electric capacity.Usually, the performance of ADC can be improved by the width increasing transistor to realize response more fast.But larger transistor (except increasing resilience and power loss) also increases the delay that signal transmits due to the larger grid capacitance of presenting to the output of PGA.It is crucial that data in interconnection between PGA and ADC transmit the performance of improvement system.To a kind of new technology be introduced, thus improve signal in the transmission of this key node and improve the bandwidth of signal captured.

Summary of the invention

Because supply voltage continues when integrated circuit convergent-divergent to reduce, the voltage margin of analog integrated circuit correspondingly reduces.This makes the design of high performance circuit (ADC system as in integrated circuit) more challenging.Therefore, the rational deployment realizing the comparator in the integrated circuit of ADC is very important for overcoming mismatch condition.Comparator requires that crucial transistor (as input transistors) matches each other with regard to its local environment.Due to the various processes for the manufacture of integrated circuit, the spatial layout feature of adjacent circuit can affect the behavior of transistor in current circuit by forming mismatch, the length increasing the input transistors of comparator contributes to overcoming this mismatch condition, but the input capacitance of comparator increases and performance reduces, thus causes the bandwidth of ADC to reduce.

Mismatch between transistor (especially input transistors) exports the comparator that will lead to errors.In addition, the unsuitable layout remarkable mismatch that all can cause in a comparator and between identical comparator in the fabrication process.These mismatches all can cause ADC to make erroneous decision.And then the layout designs of poor encapsulation increases unnecessary interconnect traces length by for signal and clock (especially for having the ADC of a large amount of comparator).These longer interconnect traces (being implemented as the differential signal with parallel routing) will dynamically reduce the bandwidth of system.Longer clock routing needs larger clock buffer, which increase overall power consumption, and more profoundly, by additional for generation clock jitter, this will cause problem as the bubble (bubble) in decoded result and lower ENOB (number of significant digit).Longer power line is introduced additional IR and is fallen, and this causes the mismatch between different comparator further.

Propose minimized for the misgivings of above-mentioned aspect simple layout technology in the present embodiment.The mismatch referring in the comparator that (dummy finger) reduces between input transistors except making the extra vacation of each comparator, is aligned to comparator just in time close to each other, thus makes all input transistors share an integrated active district.Thus, the vacation that the finger piece on the edge of active area serves as adjacent comparator refers to.

In another embodiment, the high speed fully differential comparator that is timed at (used in 60GHz transceiver) 2640MHz of the key concept of this ADC.Substantially, each comparator is made up of four parts: preamplifier level, and this preamplifier is sampled and amplified the input signal from previous stage or programmable gain amplifier (PGA); Catch level, this seizure level is timed the content catching preamplifier level; The crossing coupling transistor be timed for a pair, small-signal is regenerated as close to rail-to-rail signal to transistor by this; And output latch, this output latch locks aforementioned result after regeneration so that the Static CMOS Circuits after putting on.Timing is not carried out to preamplifier level; Therefore, preamplifier level is without undergoing initialization and transient performance effect.On the contrary, catching level uses clock signal the content of preamplifier level to be sent in memory refresh level.With pulse, timing is carried out to seizure level, timing is carried out to these pulses and minimizes with the clock resilience that memory refresh level is generated.

In another embodiment, owing to employing quick flashing ADC transducer, many comparators are placed to the input linked together with it in parallel.By the use in conjunction with unclocked preamplifier level, significantly reduce the clock resilience from many preamplifier levels to PGA.Because after preamplifier level, timing occurs in seizure and memory refresh level, catch level and forbid that clock resilience enters preamplifier level, in addition, owing to not carrying out timing to preamplifier level, eliminate it to be enabled or the transient response of anergy, reduce this part of clock resilience of preamplifier level thus.Therefore, above-mentioned some aspects of the design through discussion, even if when 17 comparators are driven by a differential signal source simultaneously, clock resilience creatively reduces.

The difference output of PGA is carried by the input difference grid capacitance of 17 comparators.Difference metallization traces is used for these 17 comparators and PGA to interconnect.The input capacitance of these comparators and the electric capacity of this metallization traces all add up to increase differential capacitance load.The differential capacitance load being supplied to PGA is very large and reduce the bandwidth of this signal path.Therefore, which imply that input difference transistor in comparator is not to should be excessive on width, to make input capacitance minimize and to reduce corresponding power dissipation.But the embodiment introduced in theory of the present invention allows the input gate of comparator to have large width transistor, which overcomes the performance degradation that the above-mentioned electric capacity in ADC comparator causes.Concept of the present invention uses the impact of the large input capacitance of active negative capacitor circuit for eliminating comparator.This elimination makes the electric capacity between PGA and ADC minimize and has expanded the gain characteristic of the interface between the input of the output of PGA and the first order of comparator.This active negative capacitance is intersect to NMOS substantially, and this intersection has NMOS and connects the capacitor of its source electrode, and each NMOS be biased by current source.

Describe various embodiments of the present invention and each side with reference to hereafter discussed details, and accompanying drawing will be shown to each embodiment.Below description is to displaying of the present invention and should be understood to limit the present invention.Describe many specific detail to provide fully understanding various embodiments of the present invention.But, in some cases, not to know or the details of routine is described, thus provide the Brief Discussion to embodiments of the invention.

Accompanying drawing explanation

Note that the accompanying drawing shown in this specification may be not necessarily to scale and the relative size of various elements in these sketches is schematically described.Invention described herein can be implemented in many different forms and should not be construed as limited to embodiment set forth herein.But, provide these embodiments, thus make this disclosure to be more detailed and complete, and the scope of the invention will be expressed completely for those of ordinary skill in the art.In other cases, do not illustrate in detail or describe the 26S Proteasome Structure and Function known, to avoid the description of unnecessarily fuzzy embodiments of the invention.Identical numeral refers to the similar elements in figure.

Figure 1A illustrates the circuit diagram of conventional comparator.

Figure 1B present conventional comparator and relate to clock resilience transistor terminal between the part of circuit diagram of coupling capacitance.

Fig. 2 depicts the sequential chart of conventional comparator.

Fig. 3 A shows the circuit diagram according to comparator of the present invention and rear operating block.

Fig. 3 B illustrates the symbol according to Fig. 3 A of the present invention.

Fig. 4 presents the block diagram according to comparator of the present invention.

Fig. 5 A illustrates the circuit diagram according to innovative comparator of the present invention.

Fig. 5 B depicts the reseting pulse generator used in the circuit diagram according to Fig. 5 A of the present invention.

Fig. 5 C shows the form of the voltage input and output of the inventive circuit illustrated according to Fig. 5 A of the present invention.

Fig. 5 D illustrates a part for the circuit diagram of the innovative comparator of Fig. 5 A, and this portion shows is according to two serial coupling capacitor of minimizing clock of the present invention resilience.

Fig. 6 A presents does not exist transistor M according to of the present invention ₂₁, M ₂₂, M ₂₃with the time stimulatiom of comparator circuit when pulse generator.

Fig. 6 B illustrates the time stimulatiom of the comparator circuit according to Fig. 5 A of the present invention.

Fig. 7 depicts the diagram according to resistor ladder of the present invention and comparator.

The input that Fig. 8 A shows current source and two comparators to one of conventional transistors layout.

Fig. 8 B present according to the input of current source of the present invention and two comparators to one of creative transistor layout.

Fig. 8 C present according to the input of current source of the present invention and two comparators to one of creative transistor layout.

Fig. 9 illustrates according to resistor according to the present invention ladder and the diagram of comparator with active negative capacitance.

Figure 10 A depicts the equivalent circuit diagram according to active negative capacitance of the present invention.

Figure 10 B illustrates the equivalent circuit diagram of the active negative capacitance according to single-ended version of the present invention.

Figure 11 shows according to the process, voltage and temperature (PVT) current source that put on the active negative capacitance of same-phase I and quadrature phase Q raceway groove of the present invention.

Figure 12 presents according to the curve chart and do not have with the frequency response of PGA and ADC of active negative capacitance circuit of the present invention.

Embodiment

The invention introduced in this specification may be used for any wired or wireless system or the design of any low supply voltage.These technology can be used for any Amplifier Design, ADC design or PGA and ADC Interface design.These technology can extend to other circuit design, and in these circuit design, the bandwidth needing to increase between two interfaces, clock resilience reduce or the transistor of coupling in circuit.

The comparator be timed in the first preamplifier level is illustrated in Figure 1A.The essential structure of the preamplifier level be timed comprises earthed switch M ₁, this earthed switch has the grid being coupled to clock CK.M ₁drain electrode 1-9 be coupled to two N-channel transistor M ₂and M ₃source electrode.M ₂by V _iN ^-driven, simultaneously M ₃by another differential input signal V _iN+driven.M ₂drain coupled to 1-1 and be coupled to the p channel transistor M controlled by same clock CK ₇drain electrode.M ₃drain electrode 1-2 be coupled to the p channel transistor M controlled by same clock CK ₁₂drain electrode.Ram cell is coupling between two node 1-1 and 1-2 and power vd D.The transistor of ram cell comprises M ₄, M ₅, M ₉and M ₁₀.Note, M ₄cross-couplings is to M ₅, and M ₉cross-couplings is to M ₁₀.N-channel transistor M ₄drain coupled to p channel transistor M ₉drain electrode.N-channel transistor M ₅drain coupled to p channel transistor M ₁₀drain electrode.Two of ram cell export 1-3 and 1-4 and are also coupled to transistor M ₈and M ₁₁and by the control of same clock signal C K.In addition, two of ram cell export by p channel transistor M ₆be coupled and be subject to the control of clock CK thus this unit of initialization.Therefore, this first order of preamplifier level uses single clock to carry out initialization and catches and is presented on two input node V _iN-and V _iN+the signal at place.

Substantially, use this topological structure, when clock CK overturns from low to high, tail transistor (M ₁) be drawn to earth terminal rapidly by the source electrode of these two input transistors, thus cause respectively by transistor M ₂and M ₃c _gs2and C _gs3(see Fig. 2 b) to the larger resilience of input signal, and disturbs the operation of other comparators.When clock is low from high tumble, the drain electrode of two input transistors will be precharged to VDD, result through C equally _gd2and C _gd3the resilience at input signal place.When comparator runs on higher frequency (such as, 2.64GHz), these resiliences become more serious.

In the Part II of circuit, output 1-3 and 1-4 of clock comparator is applied on inverter 1-5 and 1-6.These inverters are driving N channel transistor M respectively ₁₃and M ₁₄grid.These two N-channel transistor rewrite or maintain the data content in the cross-linked memory cell that is stored in and is made up of inverter 1-7 and 1-8.These outputs are drawn from the output of the cross-couplings memory cell of this coupling be made up of these two back-to-back inverters, and these outputs are V _n1-and V _p1+.

Be conceived to the preamplifier level be timed, when output 1-3 and 1-4 is coupled to be low as CK by p channel transistor, initialization carried out to unit.This transistor is marked as M ₆, and with CK, timing is carried out to it.When CK step-down, these two outputs of differential comparator become equal simultaneously.When clock CK is low, N-channel transistor M ₁anergy, and remaining whole p channel transistor M ₇, M ₈, M ₉, M ₁₀, M ₁₁and M ₁₂all be enabled, thus cause node 1-3 and 1-4 to be precharged to VDD.Once clock uprises enable M ₁, whole p channel transistor M ₆-M ₁₂become anergy, and by cross-linked transistor M ₄, M ₅, M ₉and M ₁₀the content amplification of the one RAM memory cell of composition is applied to N ditch sect M ₂and M ₃on signal difference.Before this unit can make a policy, transient performance occurs.This transient performance is because these two output nodes are all precharged to VDD under init state.When this unit becomes enable, transient state occurs, until circuit arrives stable state and finally captures input signal, at this point, and the voltage stabilization at node 1-1,1-2,1-3 and 1-4 place.Once this stable state occurs, then a RAM memory cell is by voltage stabilization at its output node 1-3 and 1-4 place, and then, the information caught is applied in the second level part of latch.Amplify in ram cell and catch and be applied to M ₂and M ₃on input.When differential voltage between these inputs reduces, before preamplifier has an opportunity to stablize, the resilience that this preamplifier and other preamplifiers produce can produce the result of mistake at node 1-3 and 1-4 place.This Part II comprises two inverter 1-5 and 1-6, and these two inverters are used for amplifying, isolation signals provide it to the 2nd RAM memory cell, and this memory cell is by M ₁₃and M ₁₄enable inverter 1-7 and 1-8 form.

Buffer interface provides the coupling from the first ram cell to the differential signal of the 2nd RAM memory cell.2nd RAM memory cell comprises inverter 1-7 and 1-8 be coupled back-to-back.Depend on and introduce the current value of this unit and this unit catches the value before having from the last time, the content of the 2nd RAM memory cell or by fresh content overwrite or maintain identical content.The output of comparator is voltage V _n1-and V _p1+.If the enable transistor of the output of one of inverter 1-5 or 1-6 overturns the content of the second ram cell, the transistor M of the 2nd RAM memory cell ₁₃and M ₁₄the content of this unit of overwrite.Note, in the initialized process of the first ram cell, node 1-3 and 1-4 is higher, thus prevents M ₁₃and M ₁₄overwrite second ram cell.If the logical zero content of the second ram cell is coupled to earth terminal, the transistor M of the 2nd RAM memory cell by the enable transistor of the output of inverter ₁₃and M ₁₄maintain the content of this unit.If logic one content of the second ram cell is coupled to earth terminal, the transistor M of the 2nd RAM memory cell by the enable transistor of the output of inverter ₁₃and M ₁₄switch the content of this unit.

Circuit in Figure 1A stands some defects: 1) earthed switch transistor M ₁be connected between VDD and memory cell, thus reduce voltage margin and reduce performance; 2) node 1-1,1-2 and 1-9 are caused transistor M from the transient performance being initialised to stable state by the first ram cell ₂and M ₃terminal between the larger voltage swing of potential capacitance signal feedback introduce input signal, resilience is introduced input signal by this transient performance, causes the inaccuracy of signal capture thus; 3) the transistor M be timed ₁and M ₆-M ₁₂resilience is introduced the internal node of transistor, thus affect the accuracy of input signal seizure; And 4) M ₁, M ₇and M ₁₂grid on conversion clock also reduce the accuracy of the signal caught along input signal is introduced in clock resilience.Finally, circuit needs larger clock driver to drive the capacitive load of all crystals pipe, improves the overall power dissipation of final circuit thus.

Figure 1B illustrates the simplification version of the schematic diagram in Figure 1A, and between the terminal showing transistor owing to affecting the clock resilience of circuit behavior and affecting each capacitor of internal node.Clock CK almost waves nearly full track (VDD to VSS), and a part for this clock is sent to the opposite side of capacitor by any electric capacity being coupled to clock line.Transistor M is respectively show in Figure 1B ₁in grid to capacitance of drain C _gd1with transistor M ₂and M ₃grid to source capacitance C _gs2and C _gs3.In addition, also respectively depict M ₂and M ₃grid to capacitance of drain C _gd2and C _gd3and M ₇and M ₁₂grid to drain transistor electric capacity C _gd7and C _gd12.These coupling capacitors contribute to showing how clock resilience acts on.When differential comparator is enabled, clock signal C K is converted to from zero and passes through C at node 1-9 in the lump _gd1iunjected charge.The electric charge injected at 1-9 place is also respectively by C _gs2and C _gs3be coupled to input node V _iN-and V _iN+.Fortunately, how many these two capacitor series connection, decrease clock resilience.But, be applied to p channel transistor M ₇and M ₁₂clock be also fed to node 1-1 and 1-2 respectively by grid to drain node.The voltage at these two some places is also by transistor M ₂and M ₃grid to capacitance of drain or C _gd2and C _gd3be coupled to input.Therefore, when clock is from a kind of change in polarity to another kind of polarity chron, the electric charge injected of clock signal is fed back to input node and is the Part I of clock resilience.

The Part II of clock resilience be preamplifier level from the transient performance being initialised to stable state, this transient performance introduces larger transient voltage at node 1-1,1-2 and 1-9 place and waves.Respectively, the transient voltage signals at node 1-1 place waves by capacitor C _gd2be coupled to input node V _iN-, the transient voltage signals at node 1-2 place waves by capacitor C _gd3be coupled to input node V _iN+, and the transient voltage signals at node 1-9 place waves by capacitor C _gs3and C _gs2be coupled to input node V _iN+and V _iN-.Transistor M ₂and M ₃terminal between these feedback capacity signals entering input node the Part II of clock resilience is responsible for and introduces inaccuracy when signal acquisition.

The advisory result that the clock resilience illustrating some node of the comparator described in Figure 1A in Fig. 2 causes.The waveform V on top _iDthe ideal curve figure of input signal.Ideal signal illustrates the input signal V when not having clock resilience _iN+to occur.The waveform V of centre and bottom _iN+input signal V with CK _iN+with the simulation result of CK.This CK waveform presents the rising edge 2-2 of the enable comparator be timed, and due to effect mentioned in the early time, ideal input signal at 2-1 as real input signal V _iN+shown in experienced by burr.Similarly, as CK waveform decline 2-4, due to the effect mentioned in the early time, real input signal V _iN+experience positive burr 2-3.Due to transistor terminal between electric capacity and be enabled and the transient performance of comparator of anergy, there are these burrs due to coupling capacitance when each clock changes.V _iN+signal follows the ideal input signal V with the burr that additional noise or clock resilience cause _iD.From input signal V _iN+extract data become more difficult due to these burrs and add the inaccuracy of analog-to-digital conversion.Therefore, determine that the error source of the magnitude of voltage of input signal occurs due to clock resilience substantially.Resilience is approximate positive and negative direction 200mV, and this causes producing error when we wish to catch ideal input signal.If resilience clock effect can reduce or reduce, then the accuracy of signal conversion will be improved.

In order to minimize the problems referred to above, introduce two main embodiment.First be remove the clock transistor in preamplifier level, thus make preamplifier by when not by amplifying signal when clock resilience signal disturbing and without undergoing being enabled and the larger transient performance of anergy.Second is use reseting pulse generator circuit to create " resets " signal, should to put on reset transistor thus initialization regenerative by " reset " signal catching level.This generator further creates " conducting (the pass) " signal being applied in the turn-on transistor caught in level, is somebody's turn to do the signal of " conducting " signal permission from preamplifier with correct sequential conducting to regenerative.Adjustment is somebody's turn to do " reset " signal with " conducting " signal resilience to be minimized.

The differential comparator of the timing of the preamplifier level eliminating comparator is illustrated in Fig. 3 A.The second level with clock CK is latched in rear Clocked operation block 3-5 and occurs.Depend on that when opening the second latch when catching data has an impact corresponding to order of accuarcy that is actual or ideal signal to signal acquisition.The preamplifier level illustrating unclocked comparator uses the Circnit Layout of transistor and load.The output of this circuit is coupled to rear Clocked operation block 3-5 by line 3-3 and 3-4.Bias voltage V _bbe applied to the transistor M in kinetic current source ₁₅and M ₁₆on.Transistor M ₁₅3-1 and M ₁₆the drain electrode of 3-2 is connected to difference transistor circuit separately.The the first difference transistor circuit being connected to 3-1 by by load coupling to the N raceway groove M of VDD ₁₇and M ₁₈composition.These loads can be made up of resistor and/or reactive component.This first difference transistor circuit has and is applied in M respectively ₁₇and M ₁₈grid on input signal V _iN-and V _rB.The the second difference transistor circuit being connected to 3-2 also by identical load coupling to VDD.Second difference transistor circuit is by the N raceway groove M being connected to node 3-2 ₁₉and M ₂₀composition.This second difference transistor circuit has and is applied in M respectively ₁₉and M ₂₀grid on input signal V _rAand V _iN+.Voltage V _rAand V _rBbe input reference signal and come from resistor row (will briefly introduce).The right pin of two differential pairs is from load Z ₂collect electric current, the left pin of differential pair is all from load Z simultaneously ₁collect electric current, wherein, load Z ₁and Z ₂all be coupled to VDD.M ₁₆, M ₁₉and M ₂₀transistor arrangement be called as differential levels 3-7.This differential levels 3-7 has current mirror (M ₁₆), the first input transistors (M ₁₉) and the second input transistors (M ₂₀).The output of differential levels is coupled to node 3-3 and 3-4.Transistor M ₁₅, M ₁₇and M ₁₈form the second differential levels.At transistor M ₁₈with transistor M ₂₀drain electrode place extract first of preamplifier level and export 3-3, and at transistor M ₁₉with transistor M ₁₇drain electrode place export 3-4 to second of preamplifier level and carry out tap.These two outputs are difference output.Note, do not carry out timing to this preamplifier level, in other words, it is unclocked at all.This should reduce clock resilience and improve the seizure to input signal.

All timing of this innovative comparator are applied on rear Clocked operation block 3-5 and export V to generate _p1+and V _n1-.Rear Clocked operation makes timing be separated with the preamplifier level of differential comparator and clock resilience is minimized.The symbol of differential comparator is illustrated in Fig. 3 B.It has four input signals and two output signals.Do not show bias voltage and supply voltage with this symbol; But, these two input signal V _iN+and V _iN-be shown in the inside of four inputs in left side, and the input of outside is two input reference voltage V _rAand V _rB, the output of differential comparator 3-6 is arranged on node V _p1+and V _n1-.

Fig. 4 illustrates the block representation of the differential comparator 3-6 shown in Fig. 3 B and Fig. 3 A.Preamplifier level 4-1 is by the driving of four input signals, and these four input signals are two reference signal V _rAand V _rBand input signal V _iN+and V _iN-.The output of preamplifier level 4-1 corresponds to the first two of showing in Fig. 3 A and exports 3-3 and 3-4.Remaining piece is the block in the rear Clocked operation block 3-5 shown in Fig. 3 A.Clock upper left side to be applied on reseting pulse generator 4-3 and generate two be applied in catch level reset and turn-on transistor on and the output of initializes memory block 4-2.This block catches the output on online 3-3 and 3-4 of preamplifier level and is put on buffer 4-4 and 4-5 by caught signal.Clock is also applied on the memory cell block 4-6 that is timed, and this memory cell block catches the output of these two buffer circuits.Then, the memory cell block 4-6 be timed is applied on memory cell block 4-7, thus generates two output V _p1+and V _n1-.Clock signal is also applied on the rear Clocked operation block of other comparators.

The more detailed analysis to Fig. 4 is illustrated in Fig. 5 A.Along Fig. 5 A top marker preamplifier level, catch level and memory refresh, two buffers and latched memory level.Use resistor R respectively ₁and R ₂replace load Z ₁and Z ₂.The reseting pulse generator 4-3 of Fig. 4 is schematically shown in Fig. 5 B.This circuit generates waveform sequential for catching level 5-1.Clock signal makes reseting pulse generator can production burst.This clock is applied on the first inverter 5-4 that 5-5 cushions.The output of 5-5 is CK1 and is applied in other parts of seizure level and memory circuitry.Clock CK1 is applied on inverter 5-6, and this inverter is coupled to inverter 5-7.The output of signal CK1 and inverter 5-7 is applied on NOR gate 5-10, and inverter 5-12 cushions this NOR gate to generate conduction pulses V _p.Meanwhile, the output of the inverter 5-8 that clock CK1 and inverter 5-7 drives is applied on the second NOR gate 5-9, and 5-11 cushions this second NOR gate to generate reset pulse V _r.These two signals (conducting and reset pulse) are applied in and catch on the reset of level 5-1 and turn-on transistor, these reset and turn-on transistor by transistor M ₂₁, M ₂₂and M ₂₃composition.Reset pulse (V _r) be applied in reset transistor M ₂₁on with will by transistor M ₂₄-M ₂₈the memory cell of composition resets.By conduction pulses (V _p) to two turn-on transistor M ₂₂and M ₂₃carry out timing, transfer transmits the content of preamplifier level and is passed in first memory cell be timed.Note, V _pand V _rall poor efficiencys, because M ₂₁, M ₂₂and M ₂₃it is P raceway groove.

Memory refresh level is by being coupled to the first inverter M ₂₇and M ₂₅and the second inverter M ₂₈and M ₂₆public clocked transistors M ₂₄composition.The output of the first inverter is coupled to the input of the second inverter.Similarly, the output of the second inverter is coupled to the input of the first inverter, thus is formed by CK1 via transistor M ₂₄the ram cell be coupled back-to-back of timing.Two outputs of ram cell 5-2 and 5-3 cushioned by buffer 1-5 and 1-6 respectively.Then, the output of inverter is applied in the latched memory level that is made up of back-to-back inverter 1-7 and 1-8.Each output of latched memory level has the N-channel transistor M be coupled with earth terminal ₂₉and M ₃₀.Depend on the value of the differential signal that inverter 1-5 and 1-6 provides, the interior of latched memory level can be switched and perhaps maintained and value identical before.The output of latched memory unit is V _p1+and V _n1-.

In the beginning (from trailing edge) of each clock cycle, when clock step-down, memory refresh level is by anergy.After one section of fixed delay, generate reset pulse, thus initialization is carried out to two outputs of memory refresh level.Node 5-2 and 5-3 is equal and on the threshold voltage of inverter 1-5 and 1-6, thus prevents last ram cell 1-7 and 1-8 to be overwritten.This step effectively reduces the chance of the error that resilience causes.Reset pulse is by after anergy, and conduction pulses is generated, thus is exported and the short circuit of memory refresh level by preamplifier.Depend on the pulse duration of this conduction pulses, still can export at preamplifier and observe slight resilience.Even so, be initialised because memory refresh level exports, resilience can not cause memory refresh level output switching activity to the polarity of mistake.But, in fact, from different comparator repeatedly resilience can feedthrough to preamplifier level input node and damage its correctness.

The dotted line frame 5-13 of Fig. 5 C illustrates two conditions for comparator given in Fig. 5 A.Listed first condition is V _iN+-V _iN-be greater than the difference V of reference voltage _rA-V _rB, the then output V of circuit _p1+it will be logic one.Listed second condition is V _iN+-V _iN-be less than V _rA-V _rB, the then output V of circuit _p1+it will be logical zero.

Coupling capacitance between the terminal illustrating the transistor in a part for the circuit of Fig. 5 A in Fig. 5 D.V _ppulse is generated by clock signal C K1 and this signal is rail-to-rail waves and can via grid to source capacitance C _gs22and M ₂₀drain-to-gate electric capacity cause by transistor M ₂₂clock resilience.C _gd20transmission signal on 3-3 is also passed to input signal V _iN+.Note, there are two series capacitors, thus make at V _iN+terminal place senses the signal V of clock _preduced before.In order to realize the performance that can match in excellence or beauty, as shown in Figure 1A, when clock and channel transistor are positioned at the base stage of clock comparator, the transistor width in Fig. 5 A can be reduced for shown circuit.Overlap capacitance between the terminal of transistor minimizes by this reduction of width, and this is that minimizing will at V _iN+another reason of the clock resilience of any type of being sensed of input voltage place.In addition, because do not need to carry out initialization to this circuit, under preamplifier level is in the stable situation eliminating a part of clock resilience.The simulation curve figure of the circuit shown in Fig. 5 A is presented in Fig. 6 A and Fig. 6 B.

Minimizing of clock resilience is illustrated between Fig. 6 A and Fig. 6 B.In fig. 6, three waveforms are shown; Top is ideal signal V _iD, M signal is CK1 and bottom signal is Vc=V _e, because the seizure level 5-1 in Fig. 5 A has been shorted alternative.Note, because clock CK1 changes, the clock resilience of Vc experience more than 700 millivolts.This clock resilience of internal node can at input node V _iN+the remarkable change in voltage of upper introducing, this will affect the ideal signal be just applied in.

In order to reduce resilience, introduce two mainly amendments: 1) remove the transistor be timed in preamplifier level, thus make preamplifier level to continue when not disturbing by clock resilience to amplify this signal; And 2) create reset pulse generative circuit (shown in Fig. 5 B) to generate the reset of carefully location and conduction pulses to control innovative comparator.

In fig. 6b, catch level 5-1 in order to the simulation result of Fig. 6 A replace mentioned by short circuit, and upper waveform is CK1.Ensuing two waveforms correspond respectively to reset pulse V _rwaveform and conducting voltage pulse V _p.Reset pulse generative circuit generates " reset " pulse of the reset transistor for catching level and " conducting " pulse for the turn-on transistor that catches level.Reset pulse initialization regenerative, signal is sent to regenerative from preamplifier level with suitable sequential via the turn-on transistor caught in level by conduction pulses simultaneously.Next waveform is Vc signal, the very little resilience of about 100 millivolts of this signal experience, and bottom waveforms is difference waveform V simultaneously _dF.Difference waveform V _dFshow waveform V _ewith the difference of the waveform on node 5-2.Marked Vc, V in fig. 5 _ewith 5-2 node.Nethermost waveform is applied on inverter 1-6, and signal is passed to the latched memory level generating rail-to-rail voltage by this inverter.This waveform is put on latched memory level to generate the final output of comparator.

Note, when the result with Fig. 6 A compares, the resilience in Fig. 6 B declines significantly.In preset time window and V _ptrailing edge compare, adjustment V _rrising edge, thus resilience is minimized.This can be realized by the size of the inverter/door suitably specifying the reset pulse generative circuit in Fig. 5 B.The adjustment of this sequential ensure that for by transistor M ₂₄until M ₂₈first memory cell be timed of composition meets the retention time of certain amount.This realization result in the control signal waveform (V shown in Fig. 6 B _pand V _r).Can find out, make conduction pulses anergy (V _puprise) before, enable memory refresh level (CK1 uprises).This can not change the observed result of preamplifier output significantly based on slower memory regenerative.Because preamplifier will have other half clock cycle sampled input signal, this overlap can not cause the error of next sample.Equally, Fig. 6 A illustrates when not having isolation/reset pulse, and preamplifier level exports (Vc=V _e) by completely by the distortion of the resilience being generated institute.

4 quick flashing ADC in Fig. 7 are made up of 17 comparators, and wherein 15 are divided into 16 parts with reference to voltage, simultaneously two other instruction overflow/underflow.In order to generate 4 binary codes, analog input is divided into 2 ⁴=16 level, this only needs 15 comparators (comparator #2-#6), and therefore the output of comparator #1 and #7 is only overflow/underflow designator.The thermometer code that comparator array generates is eliminated circuit through bubble and is then converted into binary code, and this binary code is changed into 220MSa/s (million samples are per second) by next stage from 2640MSa/s antitone sequence.

The key concept of this ADC is the high speed fully differential comparator be timed at 2640MHz.Substantially, each comparator is made up of four parts: preamplifier level, and this preamplifier is sampled and amplified the input signal (PGA) from previous stage; Catch level; Have the regenerative of cross-coupled pair, this regenerative is timed to regenerate small-signal and amplifies the signal going to next stage; And latch stage, this latch stage locks comparative result after regeneration, thus provides signal to ensuing Digital CMOS circuit.

In order to work in 2640MHz clock frequency, comparator must provide high dc gain with regenerated signal within the time period allowed, and minimizes metastability issues in addition.On the other hand, rapid regeneration result in the strong resilience noise at the input node place of preamplifier, and due to Miller feedback effect (Miller feedbackeffect), when being applied to the input signal in preamplifier level and being less, noise may result in the decision-making of mistake.In addition, when as carried out timing to preamplifier level in whole realization mode, large input transistors is also subject to the impact of clock resilience.

The comparator with large width transistor can run rapidly, but directly can load 17 comparators due to PGA, and the input capacitance of comparator can be very large, the output of the PGA that slows down thus.In addition, if employ large width transistor in preamplifier level, power constraint will be exceeded.

The innovative comparator circuit with the clock resilience of minimizing shown in Fig. 5 A is make use of for 17 times in ADC shown in the figure 7.This ADC is flash converter, because all 17 comparators run to calculate conversion all simultaneously.Because all comparators run simultaneously, enter input signal V _iN+with _iN-clock resilience add 17 times of single comparator.This may introduce multiplication effect at input signal place, presents importance clock resilience being reduced to the minimum possible level in comparator, because repeatedly employ this comparator.

Replace the resistor ladder of generation 33 reference voltages, employ the resistor ladder with 16 resistor segment, and between these resistor segment to the connection of the input of comparator be unconventional.Substantially, this implementation is relative to V _r8symmetrical.V _iN+can or higher or lower than V _iN-, and V _iN+=V _iNthe point at place is arranged on and exports V _p8border.

Two internal input signal V of the comparator in Fig. 7 _iN+and V _iN-the output of programmable gain amplifier is connected to from circuit of advancing (proceedingcircuit).Outside input reference signal is tapped into the resistor row formed by 16 resistor 7-2 to 7-9.Note, " ... " on all these lines represents at this region memory at more resistor and comparator.By resistor registration at VDD and current source I ₁between, this current source is connected to VSS.This resistance string provides can by electric current I ₁vDD and V adjusted _thsegmentation dividing potential drop between+△.

Clock generating circuit works in an identical manner in each comparator.Local clock generation circuit avoids the clock jitter outside amount.Reduce the performance that shake improves ADC.

As described earlier, there are 17 comparators, and first comparator being coupled to resistor string is assessed for underflow (underflow) and overflow (overflow) with last comparator.The negative outside input of underflow comparator (Comp#0) is connected to VDD, and positive outside input is simultaneously connected to V _th+ △.Therefore, resistor is arranged as each comparator provides two input reference signals or voltage.The negative outside input of overflow comparator (Comp#16) is connected to V _th+ △, positive outside input is simultaneously connected to VDD.As input signal (V _iN+and V _iN-) remain on V _thtime in scope between+△ and VDD, comp#0 is in logic high (1) and com#16 is in logic low (0), and representing respectively does not have underflow or do not have overflow.But, as input signal (V _iN+and V _iN) difference be greater than (VDD-V _th-△) boundary time, comp#16 is set to indicate the logic high (1) of overflow.Further, as input signal (V _iN+and V _iN-) difference be less than-(VDD+V _th+ △) boundary time, comp#0 is set to indicate the logical zero (0) of underflow.

Remaining comparator (#1-#15) will be for remaining on V _thanalog signal figure in the boundary of+△ and VDD.Such as, the external negative terminal of comparator 1# is connected to the top of resistor 7-3, and the top of this resistor is voltage V _r15, and the lower end of the resistor 7-9 of its external positive terminal in resistor string is connected to V _r0.This comparator generates V _p1.Similarly, V is generated _p15comparator #15 make its external positive terminal be connected to resistor V _r16the VDD on top, and make its external negative terminal be connected to V in resistor string _r0bottom.Then, the output of these comparators from Comp#15 to Comp#1 generates one 1 and then many zero, and V is depended in the differentiation between one and zero _iN+and V _iN-input voltage.Such as, in dotted line frame 7-1, if V _iN+-V _iN-be greater than V _r15-V _r1, then the output V of comparator #15 _p15+equal numeral one.On the other hand, if V _iN+-V _iN-be less than V _r15-V _r1, then the output V of comparator #15 _p15+equal digital zero.When input voltage increases, more one will be added into numeric string.This string is changed into the digital binary signals of 4 by bubble elimination.

When clock signal propagates through all comparators, due to different clock delays, " bubble " may appear at output temperature meter code place.The basic bubble elimination circuit following hard on comparator array can compensate this effect.Substantially, for each thermometer code, 3 different temperatures meter codes corresponding to 3 continuous level be spent to export.If these two more high level be all " 0 " and " 1 " corresponding to minimum level, then only have two level that ought be higher to be all that " 0 " stylish thermometer code " 1 " is just generated as corresponding to minimum level.Such as, whereabouts is generated the same of new thermometer code and door by Vn10, Vn9 and Vp8.In this case, (Vp10=1 (Vn10=0) is meaned when there is bubble at Vp9, Vp9=0 (Vn9=1), and Vp8=1 (Vn8=0)) time, " 1 " at Vp8 place will be dropped the bubble eliminating Vp9 place.

Analog comparator comprises difference channel, and this difference channel needs to compare two different voltages.These two voltages are each other more close, more need the difference channel in comparator to distinguish less difference.In the process of this important difference of small voltage difference, any inhomogeneities in difference channel becomes and more exposes.The key feature maintaining inhomogeneities is the coupling of the transistor used in the difference channel of comparator.Transistor coupling is a Consideration in the manufacture process of transistor, because the local terrain differences of the neighbouring environment of transistor can affect the formation of transistor.Ideally, local landform should be identical for each transistor, and a kind of mode realizing this part thing is that dummy transistor is placed on active transistor side, thus local environment is looked the same for active transistor.But dummy transistor has used up region on tube core and the size of increasing circuit, increase cost thus and reduced performance due to larger distance.Replace dummy transistor, innovative step abuts against together by difference transistor, makes the active transistor of a differential pair play dummy transistor like this for the second differential pair.

There is following problem in the design process and traded off.Mismatch between transistor (especially input transistors to) (A _vTH=4-5mV/um) will the mistake of comparator be caused to export.This transistor has width W and length L.In order to mismatch be remained on well 0.2LSB (~ 8mV) below, it is required for having 60nm channel length, being greater than the width of 8um.

By the displaying in Fig. 8 A, Fig. 8 B and Fig. 8 C, understanding of the coupling of transistor better.Fig. 8 A and Fig. 8 B shows the layout of the current source of input transistors and two comparators.The method of Fig. 8 A routine presents layout, and Fig. 8 B and Fig. 8 C is to create the layout that Modeling Technology illustrates embodiment simultaneously, wherein, eliminates the needs to dummy transistor.This allows the transistor in two comparators of Fig. 8 B and Fig. 8 C closely to encapsulate with having no gap, thus provide uniform environment for Local treatment, in this way, not only the mismatch between different comparator is minimized, and layout also becomes compacter, thus allow the shorter wiring distance of signal and clock.

Fig. 8 A illustrates the layout of the Part I of the differential levels of N number of comparator, and this comparator is by V _bthe current mirror driven and V _iN+and V _rAthe differential pair composition driven.The layout of the Part II of the differential levels of [N+1] individual comparator, this comparator is by V _bthe current mirror driven and V _iN+and V _rAthe differential pair composition driven.In order to ensure all transistors the same run, due to the local environmental conditions on integrated circuit, virtual grid are inserted near active circuit, thus change surface and structure in landform, make all crystals pipe in active circuit regions areas all experience similar neighborhood effect like this.But these virtual grid have been used up valuable semiconductor regions and have been caused N number of comparator to be moved to more away from [N+1] individual comparator.

Creationary improvement is all removed by virtual for Interventional grid and is placed to closer to each other by each comparator, makes the active transistor of the first differential levels become dummy transistor like this for the second differential levels and vice versa.In the fig. 8b to this has been displaying, wherein, the Part I of the differential levels of N number of comparator is now near the part of the differential levels of [N+1] individual comparator.Now, the active transistor of N number of comparator, close to the active transistor of [N+1] individual comparator, eliminates the needs to dummy transistor.Which eliminate the waste of area, reduce any trough of clock and other signals, and improve the performance of circuit.

The perfect crystal pipe circuit of N number of and [N+1] individual comparator is illustrated in Fig. 8 C.The layout of showing in low portion 8-1 and Fig. 8 B is just the same.Upper part 8-2 illustrates other differential levels in the preamplifier level of comparator.Use metal 3 (M ₃) drain electrode of the respective transistor in upper part and low portion coupled together and is not illustrated.Metal 3 connects to be understood well in the art and not to be needed further explanation.Left-half presents the transistor layout of N number of comparator, and this comparator comprises input signal V _b, V _iN+, V _iN-, V _rAand V _rB.Right half part presents the transistor layout of [N+1] individual comparator, and this comparator comprises input signal V _b, V _iN+, V _iN-, V _rAand V _rB.

In order to reduce the mismatch in a comparator and between comparator, all input transistors and current source thereof are placed with substitute (dummy) that is just in time close to each other thus that serve as each other.

Realize collapsible resistor ladder to simplify the wiring from resistor ladder to differential comparator, wherein, cost is the complexity wiring that whereabouts bubble eliminates circuit.Comparator is closer to each other, thus shared transistor vacation refers to.

Fig. 9 illustrate innovative circuit with improve the programmable gain amplifier (PGA) of advancing to these 17 comparators all Differential Input between signal bandwidth transmission.Larger input gridistor region contributes to being minimized by the mismatch condition of ADC comparator but introducing larger input capacitance.Use active negative capacitor circuit to eliminate the impact of the large input capacitance of comparator.This active negative capacitance is cross-linked N raceway groove pair substantially, and wherein, this N raceway groove is to having its source-coupled capacitor together.Electric current in each N-channel transistor carried by a current source.Each in these comparators is at its V _iN+and V _iN-nodes presents input capacitance.In addition, each comparator occupy a region on a semiconductor die and this region use add 17 times.Therefore, relate to larger overall region, and in order to the output of PGA signal being transmitted to the input signal V of all 17 comparators _iN+and V _iN-, input signal needs the trace between PGA and each comparator or metal interconnected.This trace introduces significant capacitance and this electric capacity adds the input capacitance of comparator to.The interconnection of this difference comprises differential capacitance load, and this differential capacitance load comprises the capacitance of drain of the electric capacity of this interconnection, the input capacitance of these comparators and PGA.Integral capacitor causes reducing between the interface circuit of signal bandwidth between PGA and the first order of comparator.This is the key limited features of systematic function.

In order to overcome this shortcoming, develop M demonstrated in Figure 9 ₃₁and M ₃₂the cross-linked negative capacitance circuit 9-1 of creativeness.M ₃₁and M ₃₂drain terminal be coupled to node V _iN+and V _iN-.Cross-coupled circuit sensing V _iN+and V _iN-transformation contributing to accelerate it and change or shorten delivery time section.By combining two current source 9-2 and 9-3 being coupled to power supply (in this case, earthing power supply voltage or VSS), further increase performance.Capacitor C ₁₀contribute to stablizing this two transistor M ₃₁and M ₃₂the voltage at source electrode place.Thus, this circuit contributes to accelerating to change and increases the bandwidth of this key interface joint between the output of PGA and the input of these 17 comparators.

The equivalent electric circuit illustrating cross-coupled circuit in Figure 10 A represents.Input to circuit is by electric current I _1Nbe applied to the voltage source 10-1 of the left-hand component of the expression transistor 10-2 of circuit, this transistor has g _m(V _y-V _s1), and be r across this current source ₀₁impedance.The low portion of current source 10-2 is at node V _s1place is connected to R _s1.Node V _s1by capacitor C ₁₀be coupled to node V _s2.M at right-hand side ₃₂equivalent transistor, this equivalent transistor has g by parallel connection _m(Vx ~ V _s2) current source 10-3 and resistor r ₀₂composition.Upper node V _ybe connected to the negative terminal of input voltage 10-1.Mutual conductance acts on reverse voltage in the opposing legs difference relative to the voltage in himself pin.When this voltage difference increases, mutual conductance increase contributes to reducing voltage difference, improves the bandwidth gain of this interface node thus.Figure 10 B illustrates identical circuit, and except this circuit is single-ended expression now, wherein, present current source 10-5 represents mutual conductance gm (~ Vx-V _s1) and with there is V _1Nthe voltage source 10-4 of the voltage of/2 connects.The lower end of current source 10-5 is via R _sand 2C ₁₀be coupled to earth terminal.

By solving the small-signal equivalent circuit in Figure 10 A, suppose r ₀₁=r ₀₂=r ₀, R _s1=R _s2=R _s, and C ₁₀=C.The equiva lent impedance of looking to this circuit is:

$\frac{\mathrm{Vin}}{\mathrm{Iin}}\left(s\right)=-\frac{2(\mathrm{ro}+\mathrm{Rs}+\mathrm{gm}*\mathrm{ro}*\mathrm{Rs}+2\mathrm{ro}*\mathrm{Rs}*\mathrm{sC})}{(\mathrm{gm}*\mathrm{ro}-1)(2\mathrm{Rs}*\mathrm{sC}+1)}$

Ignore current source impedance, Wo Menyou:

$\frac{\mathrm{Vin}}{\mathrm{Iin}}\left(s\right)=-\frac{\mathrm{gm}*\mathrm{ro}+2\mathrm{ro}*\mathrm{sC}+1}{\mathrm{sC}(\mathrm{gm}*\mathrm{ro}-1)}$

If we ignore the channel length modulation of input transistors further, it becomes:

$\frac{\mathrm{Vin}}{\mathrm{Iin}}\left(s\right)=-\frac{2}{\mathrm{gm}}-\frac{1}{\mathrm{sC}}$

Last equation illustrates impedance and depends on g _mwith the value of C.

As depicted in figure 11, in chip, employ cross-couplings negative capacitance circuit for twice.First negative capacitance circuit is applied in corresponding to V _{iN+_I}and V _{iN-_I}synchronous analog signal input voltage on, simultaneously the second negative capacitance circuit acts on V _{iN+_Q}and V _{iN-_Q}quadrature phase analog signal on.These two groups of input signals provided by the difference output of two PGA.The current source of these transistors is by the transistor M being coupled to the controlled analog circuit of process, voltage and temperature digital ₃₃showing, this analog circuit generates electric current I R ₁.This circuit can be complete analogue enlargement or completely numerically controlled, but it uses two kinds of combinations controlled to realize the IR expected in this case ₁value.Current mirror M ₃₃voltage is applied to M ₃₄, M ₃₅, M ₃₆and M ₃₇grid, thus provide the electric current carefully controlled, this electric current is applied on drain electrode 11-1,11-2,11-3 and 11-4 of these transistors.As shown in Figure 11, M ₃₈, M ₃₉and C ₁₃, and M ₄₀, M ₄₁and C ₁₄be coupled to these nodes.These two cross-linked negative capacitance circuits improve the performance between the input of programmable gain amplifier (PGA) and corresponding A/D C thereof.Capacitor C ₁₃be placed in by M ₃₈and M ₃₉between the source electrode of the formed first cross-linked circuit, capacitor C simultaneously ₁₄be placed in M ₄₀and M ₄₁between the source electrode of the formed second cross-linked circuit.Although not shown, each in individual cross-coupled circuit can be subject to the control of independent and different analog control devices or current mirror thus perform additional function, if expected like this.

In fig. 12, shown by curve 12-1 and measure the response of the output of the PGA of driving 17 comparators of not exploitation of innovation type crossing coupling transistor with square wave.This curve has the cut-off frequency of about 0.88GHz.When exploitation of innovation type cross-coupled circuit, curve 12-2 illustrates the response of circuit between the output of programmable gain amplifier and this 17 comparators.The curve show the peak value of response, the bandwidth 720MHz of circuit is pushed out to about 1.6GHz by this peak value.Depict the gain at the 1.5DB point place between two curves.This provides the performance of improvement at this key interface place.Therefore, the signal bandwidth between PGA and ADC improves 720MHz.

In this type of design, although ADC itself has 1dB bandwidth (approximate 1.3GHz) (rear layout simulation), when Direct driver 17 comparators, the Bandwidth Dynamic ground of PGA declines (2.6dB under 880MHz declines).In this equiva lent impedance, there is negative capacitance component, this capacitive component may be used for the impact of the input capacitance eliminating ADC and increases bandwidth.Figure 12 shows the effect of negative capacitance circuit in the mode of emulation.Under the help of negative capacitance circuit, the 1.5dB bandwidth of PGA increases to 1.6GHz from less than 880MHz.

Provide some general introduction of certain in the inventive apparatus for unclocked pre-amplifier system.

A kind of comparator device comprises a first unclocked preamplifier level, is coupled to one of this first unclocked preamplifier level seizure level and is coupled to a memory refresh level of this seizure level, thus, this seizure level receive one reset and Continuity signal so that data are sent to this memory refresh level from this first unclocked preamplifier level.At least one buffer is coupled to this memory refresh level, and a latched memory is grade coupled to this buffer.A reseting pulse generator creates this reset and Continuity signal.Clock this memory refresh level enable and this clock also this reseting pulse generator enable.First differential levels of a first unclocked preamplifier level, near second differential levels of a second unclocked preamplifier level, makes this first differential levels active transistor play a dummy transistor of an active transistor of this second differential levels like this.This first unclocked preamplifier comprises: be coupled to one first first load exported of first differential levels and second differential levels, be coupled to one second second load exported, first input signal being coupled to this first differential levels and first input reference signal of this first differential levels and this second differential levels and be coupled to second input signal and second input reference signal of this second differential levels, wherein load can be a resistive load.

A kind of device comprises: one first first load exported being coupled to first differential levels and second differential levels, be coupled to one second second load exported of this first differential levels and this second differential levels, be coupled to first input signal and first input reference signal of this first differential levels, be coupled to second input signal and second input reference signal of this second differential levels, this first output is coupled to the 3rd output by first turn-on transistor, this second output is coupled to one the 4th output by second turn-on transistor and the 3rd output is coupled to the 4th output by a reset transistor.3rd output and the 4th exports and is coupled to a memory refresh level, and this memory refresh is grade coupled at least one buffer.3rd differential levels, near this second differential levels, makes an active transistor of the 3rd differential levels be used from the effect of a dummy transistor of an active transistor of this second differential levels like this.A latched memory is grade coupled to this buffer.This first and second turn-on transistor receives a Continuity signal so that data are sent to this memory refresh level from this first output and this second output.This reset transistor receives a reset signal to carry out initialization to the 3rd output and the 4th output that are coupled to this memory refresh level.

One makes the minimized method of clock resilience, the method comprises the following steps: one first of first unclocked preamplifier level output is coupled to first turn-on transistor, one second of this first unclocked preamplifier level output is coupled to second turn-on transistor, this first turn-on transistor is coupled to one first input of a memory refresh level, this second turn-on transistor is coupled to one second input of this memory refresh level, a reset transistor is coupling between this first input of this memory refresh level and this second input, this first and second turn-on transistor enable and adjust this reset transistor to reduce clock resilience in this time window in a time window, clock resilience is made to minimize thus.This memory refresh is grade coupled at least one buffer.The method comprises: make a second unclocked preamplifier level near this first unclocked preamplifier level, an active transistor of first differential levels in this first unclocked preamplifier level is made to be used from the effect of a dummy transistor of an active transistor of first differential levels in this second unclocked preamplifier like this, and by grade coupled to this buffer for a latched memory.This first and second turn-on transistor receives a Continuity signal so that data are sent to this memory refresh level from this first output and this second output.This reset transistor receive a reset signal with to this memory refresh level this first export and this second export carry out initialization.

Provide for some general introduction of certain in the inventive apparatus of negative capacitance system.

A kind of negative capacitance device comprises: the first node being coupled to a drain electrode of a first transistor and a grid of a transistor seconds, be coupled to a Section Point of a drain electrode of this transistor seconds and a grid of this first transistor, be coupling in a capacitor between a source electrode of this first transistor and a source electrode of this transistor seconds, first current mirror between this source electrode being coupling in a supply voltage and this first transistor and second current mirror between this source electrode being coupling in this supply voltage and this transistor seconds.This device also comprises first amplifier, and this first amplifier generates the differential signal that is coupled to this first and second node.This first amplifier can be a programmable gain amplifier.This device also comprises multiple amplifier, and the plurality of amplifier driven by this differential signal being coupled to this first and second node.Each amplifier in the plurality of amplifier comprises a preamplifier of a comparator.A coupling is formed between this first amplifier and the plurality of amplifier.This preamplifier of this comparator is a unclocked preamplifier.These preamplifier levels are close to each other, make an active transistor of first differential levels in a first preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second preamplifier level.

A kind of method increasing the transmission bandwidth of differential signal, the method comprises the following steps: amplify a differential input signal thus provide a differential signal of a differential capacitance load between driving first node and a Section Point, this first node is coupled to a drain electrode of a first transistor and a grid of a transistor seconds, this Section Point is coupled to a drain electrode of this transistor seconds and a grid of this first transistor, by a capacitor-coupled between a source electrode and a source electrode of this transistor seconds of this first transistor, by first current mirror coupled between a supply voltage and this source electrode of this first transistor, by second current mirror coupled between this supply voltage and this source electrode of this transistor seconds and cause drive this differential capacitance load within shorter time period, increase this transmission bandwidth of this differential signal thus.First amplifier generates this differential input signal, and this differential input signal of multiple amplifier accepts.This differential capacitance load comprises a differential capacitance, a differential-input capacitance of the plurality of amplifier and the differential drain electric capacity of this first amplifier that a difference interconnects.This first amplifier is a programmable gain amplifier.Each amplifier in the plurality of amplifier is the unclocked preamplifier of a comparator.The method comprises: make multiple unclocked preamplifier level close to each other, make an active transistor of first differential levels in a first unclocked preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second unclocked preamplifier level.

A kind of device comprises: first amplifier, this first amp couples to first node and a Section Point; A differential capacitance load, this differential capacitance load coupling is to this first node and this Section Point; This differential capacitance load between the multiple drain electrodes being coupling in the multiple transistors in a crossing coupling transistor circuit; A current source, this current source is coupled to a source electrode of each transistor; And a capacitor, this capacitor-coupled is between these source electrodes of these transistors.This device also comprises the multiple amplifiers being coupled to this first node and this Section Point, and this first amplifier differential signal drives this first node and this Section Point.Each amplifier in the plurality of amplifier is a unclocked preamplifier of a comparator.This first amplifier is a programmable gain amplifier.This preamplifier level is close to each other, make an active transistor of first differential levels in a first preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second preamplifier level.

Finally, understanding foregoing description is only displaying to principle of the present invention.Appearance is intended to be proposed at this by various change, improvement and amendment, and within the spirit and scope of the present invention.But the present invention can embody in many different forms, and should not be construed as limited to the embodiment listed by this.On the contrary, provide these embodiments so that this disclosure will be thoroughly with complete, and scope of the present invention will be passed on fully to those skilled in the art.Understand, although various embodiments of the present invention difference is not repelled mutually, according to these principles, when not deviating from the spirit and scope of the present invention, those skilled in the art can find out multiple amendment.Such as, circuit has doctrine of equivalents, that is, P raceway groove converts N raceway groove to, VDD and VSS exchanges, moves to other power supplys etc. relative to the position of other power measurement voltages, current source.Semiconductor element can comprise silicon, germanium, 3 SiC 2/graphite, GaAs, silica etc.Although use CMOS to describe circuit, identical circuit engineering can be applied to depletion mode transistor and BJT or bipolar circuit, because technology allows formation current source and power supply follower for this reason.When specifying transistor, this transistor can be the transistor as N-MOS or P-MOS.CMOS or silicon-on-insulator (SOI) technology provide two kinds of enhancement type channel type: N-MOS (N raceway groove) and P-MOS (P raceway groove) transistor or transistor.In addition, by using the communication technology as time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), OFDM (OFDM), ultra broadband (UWB), Wi-Fi, WiGig, bluetooth etc., network and portable system can wirelessly exchange messages.This network can comprise telephone network, Internet protocol (IP) network/local area network (LAN) (LAN), self-organizing network, local router and even other portable system.

Claims (20)

1. a negative capacitance device, comprising:

A first node, this first node is coupled to a drain electrode of a first transistor and a grid of a transistor seconds;

A Section Point, this Section Point is coupled to a drain electrode of described transistor seconds and a grid of described the first transistor;

A capacitor, this capacitor-coupled is between a source electrode and a source electrode of described transistor seconds of described the first transistor;

First current mirror, this first current mirror coupled is between a supply voltage and the described source electrode of described the first transistor; And

Second current mirror, this second current mirror coupled is between described supply voltage and the described source electrode of described transistor seconds.

2. device as claimed in claim 1, comprises further:

First amplifier, this first amplifier generates the differential signal that is coupled to described first and second nodes.

3. device as claimed in claim 2, wherein

Described first amplifier is a programmable gain amplifier.

4. device as claimed in claim 2, comprises further:

Multiple amplifier, the plurality of amplifier driven by the described differential signal being coupled to described first and second nodes.

5. device as claimed in claim 4, wherein

Each amplifier in described multiple amplifier comprises a preamplifier of a comparator.

6. device as claimed in claim 4, wherein

A coupling is formed between described first amplifier and described multiple amplifier.

7. device as claimed in claim 5, wherein

The described preamplifier of described comparator is a unclocked preamplifier.

8. device as claimed in claim 5, wherein

Described preamplifier level is close to each other, make an active transistor of first differential levels in a first preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second preamplifier level.

9. increase a method for the transmission bandwidth of differential signal, the method comprises the following steps:

Amplify a differential input signal thus provide described differential signal, described differential signal drives a differential capacitance load between a first node and a Section Point;

Described first node is coupled to a drain electrode of a first transistor and a grid of a transistor seconds;

Described Section Point is coupled to a drain electrode of described transistor seconds and a grid of described the first transistor;

By a capacitor-coupled between a source electrode and a source electrode of described transistor seconds of described the first transistor;

By first current mirror coupled between a supply voltage and the described source electrode of described the first transistor;

By second current mirror coupled between described supply voltage and the described source electrode of described transistor seconds; And

Cause and drive described differential capacitance load within shorter time period,

Increase the described transmission bandwidth of described differential signal thus.

10. method as claimed in claim 9, wherein, first amplifier generates described differential input signal, and differential input signal described in multiple amplifier accepts.

11. methods as claimed in claim 10, wherein

Described differential capacitance load comprises a differential capacitance, a differential-input capacitance of described multiple amplifier and the differential drain electric capacity of described first amplifier that a difference interconnects.

12. methods as claimed in claim 10, wherein

Described first amplifier is a programmable gain amplifier.

13. methods as claimed in claim 10, wherein

Each amplifier in described multiple amplifier is a unclocked preamplifier of a comparator.

14. methods as claimed in claim 13, further comprising the steps:

Make multiple unclocked preamplifier level close to each other, make an active transistor of first differential levels in a first unclocked preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second unclocked preamplifier level.

15. 1 kinds of devices, comprising:

First amplifier, this first amp couples to first node and a Section Point;

A differential capacitance load, this differential capacitance load coupling is to described first node and described Section Point;

Described differential capacitance load between the multiple drain electrodes being coupling in the multiple transistors in a crossing coupling transistor circuit;

A current source, this current source is coupled to a source electrode of each transistor; And

A capacitor, this capacitor-coupled is between described multiple source electrode of described multiple transistor.

16. devices as claimed in claim 15, comprise further:

Multiple amplifier, the plurality of amp couples is to described first node and described Section Point.

17. devices as claimed in claim 16, comprise further:

A differential signal of described first amplifier drives described first node and described Section Point.

18. devices as claimed in claim 17, each amplifier in wherein said multiple amplifier is a unclocked preamplifier of a comparator.

19. devices as claimed in claim 17, wherein said first amplifier is a programmable gain amplifier.

20. devices as claimed in claim 18, wherein

Described preamplifier level is close to each other, make an active transistor of first differential levels in a first preamplifier level play a dummy transistor like this, this dummy transistor is used for an adjacent differential level in a second preamplifier level.