JP4466695B2 - Class D amplifier circuit - Google Patents

Description

  The present invention relates to a class D amplifier circuit, and more particularly, to a class D amplifier circuit capable of reducing distortion when a minute signal is input.

  The class D amplifier circuit converts an input signal into a pulse width modulation signal having a constant amplitude and amplifies the power of the pulse width modulation signal, and is used, for example, for power amplification of an audio signal. Since the class D amplifier circuit operates with two values, the loss of the transistor can be greatly reduced, and there is an advantage that high efficiency can be realized.

  This class D amplifier circuit integrates an input signal, a comparator circuit that compares an output signal of the integrator circuit with a predetermined triangular wave signal, and amplifies the output signal of the comparator circuit to output a pulse signal. And an output signal of the pulse width amplifier is fed back to the input side of the integrating circuit. The output signal of the pulse width amplifier becomes an analog signal that drives a load such as a speaker through a low-pass filter including a coil and a capacitor. In recent years, a filterless class D amplifier circuit without a low-pass filter has been put into practical use.

  As described in Patent Document 1, the class D amplifier circuit uses a differential input method and a delay circuit to avoid power loss during no signal and to prevent distortion during a minute signal. The duty ratio of the output pulse at the time is set to several percent. FIG. 5 is a block diagram showing such a class D amplifier circuit 200. For convenience, only the main part is shown in this figure, and the feedback circuit, the integration circuit, and the like are omitted. The class D amplifier circuit 200 compares each of the input signal Vi + at the positive input terminal and the input signal Vi− at the negative input terminal with the triangular wave output from the triangular wave generation circuit 20 by using the comparators 12a and 12b. Pulse width modulate the signal.

  Here, when no signal is input, as shown in FIG. 6, both the output signal A of the comparator 12a and the output signal B of the comparator 12b are pulses with a duty ratio of 50%. When these pulses are subjected to a logical operation by a circuit composed of inverters 13a and 13b and NAND circuits 14a and 14b, both the output signal OutP at the positive output terminal and the output signal OutM at the negative output terminal via the output stage circuit 40 are both. No pulse output when no signal is input. Thereby, the power loss at the time of no signal input can be reduced.

However, in general, a dead zone occurs in the vicinity of the input crossover due to the accuracy of the comparator 12 and the input / output characteristics of the output stage path 40. Therefore, there is no pulse signal output when there is no signal or when a minute signal is input, or distortion occurs. ing. Therefore, in the class D amplifier circuit 200 of this example, the signal Bd is generated by using the delay circuit 30 having the delay amount W. As a result, as shown in FIG. 6, since a pulse having a width W is output as the output signals OutP and OutM when there is no signal, the modulation width when a minute signal is input can be accurately reflected, and distortion can be reduced.
JP 2006-42296 A

  As described above, by outputting a pulse having a width W when no signal is input, it is possible to reduce distortion when a minute signal is input. However, it is not possible to completely eliminate the influence of the dead zone or the like in the vicinity of the input crossover described above only by coping with such a delay circuit 30 installation. A specific description will be given on the assumption that the level of the input signal Vi + gradually increases from the amplitude center level.

First, as shown in FIG. 6, when there is no signal, that is, when the level of the input signal Vi + is the amplitude center level, a pulse having a width W is output as the output signal OutP and the output signal OutM.
Next, when the level of the input signal Vi + slightly increases from the amplitude center level, the pulse width of the output signal OutM slightly increases while the pulse width of the output signal OutP slightly decreases as shown in the case of the minute signal in FIG. Become.
Next, when the level of the input signal Vi + further increases and reaches a predetermined level, the pulse width of the output signal OutP becomes zero. This is because the output stage circuit 40 is configured by connecting a plurality of inverters whose input capacitance gradually increases in series. That is, the transmission waveform becomes dull depending on the input capacity of the inverter, but if the pulse width becomes narrow, the threshold voltage of the inverter cannot be exceeded and pulse transmission becomes impossible. Assuming that the minimum pulse width that can be transmitted is the minimum pulse width Wmin, when the pulse width of the output signal of the NAND circuit 14b is equal to or less than Wmin, the output signal OutP is always at a low level.
In other words, according to the conventional technique, even if the dead zone at the time of a minute signal can be eliminated, the dead zone near the predetermined level generated by the output stage circuit 40 cannot be eliminated, and there is a problem that distortion occurs.

  The present invention has been made in view of such a situation, and an object of the present invention is to reduce the distortion caused by the dead zone in the class D amplifier circuit.

In order to solve the above problems, a class D amplifier circuit according to the present invention includes a pulse width modulation unit that generates a first signal and a second signal by performing pulse width modulation on an input signal, and delays the second signal. A delay unit that generates a delayed second signal and controls a delay time, and generates a first output pulse signal and a second output pulse signal that are output to the outside based on the first signal and the delayed second signal. Output pulse generating means, and adjusting means for adjusting the pulse width of the first output pulse signal and the second output pulse signal to be a predetermined width, wherein the adjusting means has a predetermined N Delay time control means for controlling the delay time of the delay means to be different by repeatedly selecting a delay time of a seed (N is an integer of 2 or more) in a predetermined order .

According to the present invention, the delay time by the delay time of the N species is repeatedly selected in a predetermined order is controlled, as a result, the pulse width adjustments speak exhaustively performed cormorants Runode, eliminates the output pulse The occurrence of the state is suppressed as much as possible. Therefore, reduction of distortion at the time of inputting a minute signal can be realized.

More specifically, the N types of delay times have different lengths n (1), n (2),..., N (N) (n (1) <n (2) <... <n ( N)), and the delay time control means sets the delay times having n (1), n (2),..., N (N) to n (1), n (2), ..., n (N), n (N-1), n (N-2), ..., n (2) are selected in this order, and the delay time of the delay means is repeated by repeating this selection of the order. Is preferably controlled.

In this case, the selection of the delay time is performed in an ordered order, from the shortest one to the longest one, followed by the shortest one, so that the specific configuration of the delay time control means can be simplified. can do.
In addition, since the comprehensive adjustment of the pulse width is more suitably performed, the distortion reduction effect at the time of inputting a minute signal can be more effectively enjoyed.

Further, the N types of delay times have different lengths n (1), n (2),..., N (N) (n (1) <n (2) <... <n (N)). , N (1), n (2),..., N (1), n (2),..., N (1), n (2),. It is preferable to control the delay time of the delay means by selecting the delay time in the order of N) and repeating the selection of this order .

In this case, since the delay time is selected from the shortest one to the longest one, the delay time is changed from the shortest one to the longest one after another. The general configuration can be simplified.
In addition, since comprehensive adjustment of the pulse width is performed more suitably, the distortion reduction effect at the time of inputting a minute signal can be more effectively enjoyed.

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a class D amplifier circuit 100 according to the present embodiment. The same components as those in FIG. 5 are denoted by the same reference numerals.
As shown in the figure, the class D amplifier circuit 100 includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. An input signal Vin + is supplied to the positive input terminal, and an input signal Vin− is supplied to the negative input terminal. Further, the pulse width modulation signal OutP is output from the positive output terminal, and the pulse width modulation signal OutM is output from the negative output terminal. That is, the input signal Vin is given in the form of a differential input. The pulse width modulation signals OutP and OutM are connected to a load such as a speaker (not shown). As a result, a load such as a speaker operates by a differential signal between OutP and OutM. In this embodiment, a filterless class D amplifier circuit that connects a load without using a low-pass filter is used. However, a general configuration in which a load is connected via a low-pass filter may be used.

  The class D amplifier circuit 100 includes resistors R1 to R6, capacitors C1 to C4, an operational amplifier 11, comparators 12a and 12b, and a PWM signal generation unit X1 composed of a triangular wave generation circuit 20, inverters 13a and 13b, and NAND circuits 14a and 14b. And an adjustment unit X3 including an output stage circuit 40, a delay amount variable circuit 50, and an up / down counter 70.

  In the PWM signal generation unit X1, the input signal Vin + is supplied to the positive input terminal of the operational amplifier 11 via the resistor R1 and the feedback signal is supplied via the resistor R3. On the other hand, an input signal Vin− is supplied to the negative input terminal of the operational amplifier 11 via the resistor R2 and a feedback signal is supplied via the resistor R4. Between the positive output terminal and the negative input terminal of the operational amplifier 11 and between the negative output terminal and the positive input terminal, a T-type secondary differentiation circuit is provided. The differentiation circuit between the negative output terminal and the positive input terminal of the operational amplifier 11 is constituted by capacitors C1 and C3 and a resistor R5 provided between the connection point thereof and the ground. The differentiation circuit between the positive output terminal and the negative input terminal of the operational amplifier 11 includes capacitors C2 and C4 and a resistor R6 provided between the connection point thereof and the ground. Since each differentiation circuit is provided in the feedback loop of the operational amplifier 11, the operational amplifier unit synthesizes the input signal Vin and the feedback signal, functions as an integration circuit that performs second order integration on the input signal Vin, and outputs an integration signal. .

The triangular wave generation circuit 20 generates a triangular wave signal having a constant amplitude. The frequency of the triangular wave signal is set higher than the frequency of the input signal Vin. In this example, the maximum frequency of the input signal Vin is 20 KHz, and the frequency of the triangular wave signal is 200 KHz. Note that the spectrum of the triangular wave signal may be spread from the viewpoint of reducing unnecessary electromagnetic radiation.
The PWM signal generation unit X1 generates the pulse A modulated signal A and the signal B based on the triangular wave signal and the integration signal. Here, the comparators 12a and 12b output a high level when the level of the integration signal exceeds the level of the triangular wave signal, and output a low level when the level of the integration signal falls below the level of the triangular wave signal.

The delay amount variable circuit 50 delays the output B to generate the output Bd. The delay amount variable circuit 50 can change the delay amount by the control signal CTL from the up / down counter 70.
FIG. 2 is a block diagram showing an example of the configuration of the delay amount variable circuit 50 and the up / down counter 70. The up / down counter 70 is a counter that counts a clock signal (not shown) and increases the count value when the up signal becomes active, and decreases the count value when the down signal becomes active. Further, the up / down counter 70 outputs a control signal CTL of n (n is a natural number of 2 or more) bits indicating the count value to the delay amount variable circuit 50.

Each of the up signal and the down signal mentioned above becomes complementary and non-active according to a predetermined standard. Here, the predetermined reference is, for example, as follows. That is, initially, during the period of K (K is a natural number of 2 or more) period of the carrier signal, the up signal is active and the down signal is non-active, but during the subsequent K-1 period of the carrier signal. The up signal becomes non-active and the down signal becomes active. Thereafter, these two states are repeated.
How the class D amplifier circuit 100 according to this embodiment operates by such switching will be described later.

  The delay amount variable circuit 50 includes an inverter Inv10, a capacitor C11, an inverter Inv11, a constant current circuit 51, and a selection circuit 52 that are configured by TrP1 to TrP4 and TrN1 to TrN3. The inverter Inv10 charges and discharges the capacitor C11, and the magnitude of the drive current is determined by the current flowing through the transistor TrP1. When the drive current is increased, the charge / discharge time of the capacitor C11 is shortened, so that the delay time of the delay amount variable circuit 50 is shortened. On the other hand, when the drive current becomes small, the charge / discharge time of the capacitor C11 becomes long, so that the delay time of the delay amount variable circuit 50 becomes long.

The constant current circuit 51 and the selection circuit 52 have a function of adjusting the amount of current flowing through the transistor TrP1. The constant current circuit 51 includes n constant current sources 51-1, 51-2,... 51-n, and the selection circuit 52 includes n switches SW1, SW2,. On / off of the n switches SW1 to SWn is controlled by the n-bit control signal CTL. In this example, the current amounts of the constant current sources 51-1, 51-2,... 51-n are set to increase as the subscript number increases. As the count value of the up / down counter 70 is larger, the constant current source 51-1 to 51-n is selected with a smaller current amount, and as the count value of the up / down counter 70 is smaller, the constant current source 51 is selected. The control signal CTL controls the switches SW1 to SWn so as to select one having a large current amount from -1 to 51-n.
The configuration of the variable delay amount circuit 50 is an example, and the present invention can use variable delay amount circuits having various configurations that can switch the delay amount according to the count value of the up / down counter 70.

  Returning to FIG. The logic circuit unit X2 receives the output A and the output Bd obtained by delaying the output B by the delay amount variable circuit 50, the NAND output signal of the inverted signal of the output A and the output Bd, the output A and the output Bd And an NAND output signal with the inverted signal of. An external load such as a speaker is driven by the difference between the output signals. The output stage circuit 40 is configured by connecting inverter buffers in multiple stages.

  With the above configuration, the following operation is performed in the present embodiment. In the following, in order to simplify and clarify the explanation, when n in FIG. 2 is 3, that is, the delay amount takes three values of “small”, “medium”, and “large”. The explanation is based on the premise that the information is obtained. In this case, K described above is “3”.

First, the up / down counter 70 receives an input of an active up signal for a period of three periods of the carrier signal (during this period, the down signal is non-active). Therefore, during this period, the count value continues to increase stepwise in accordance with the number of clock signals input to the up / down counter 70. The up / down counter 70 outputs a signal that increases the delay amount in the delay amount variable circuit 50.
As a result, the delay amount continues to increase stepwise, and the pulse width also continues to increase stepwise.
In this case, the output pulses OutP and OutM are as shown in the first half of FIG. 3, for example. That is, the delay amount gradually increases from small, medium, and large, and the pulse width also gradually increases.

Subsequently, the up / down counter 70 receives an input of an active down signal during a period of two cycles of the next carrier signal (the up signal is non-active during this period). Therefore, during this period, the count value continues to decrease stepwise. Further, the up / down counter 70 outputs a signal such that the delay amount in the delay amount variable circuit 50 becomes small.
As a result, the delay amount continues to decrease stepwise, and the pulse width also continues to decrease stepwise.
In this case, the output pulses OutP and OutM are as shown in the latter half of FIG. 3, for example. That is, the delay amount gradually decreases from medium to small from the above-mentioned “large” state, and the pulse width also gradually decreases.

  Thereafter, the above two operations are repeated. That is, the up / down counter 70 receives an active up signal or down signal at each time interval T, whereby the delay amount is small, medium, large, medium, small, medium, as shown in FIG. , Large,..., Transitions between the three types of values are sequentially repeated. As a result, the pulse width eventually increases or decreases stepwise as shown in FIG.

In the class D amplifier circuit 100 according to the present embodiment, by performing the operation as described above, the time when the output pulses OutP and OutM are eliminated can be shortened as much as possible, and the occurrence of distortion at the time of a minute input signal is suppressed. Can do.
This becomes clearer by comparing this embodiment with the case where the delay amount is unchanged. FIG. 4 shows an example of output pulses OutP and OutM in such a case. In this case, the delay amount continues to take a certain value over the entire period. However, since there is a dead zone near the predetermined level by the output stage circuit 40, when the input signal is in the dead zone, the output pulse disappears. It will end up. In FIG. 4, theoretically, a pulse with a width of W1 should be output. However, because of the influence of the dead zone or the like, it is impossible to output a pulse having a width equal to or smaller than the width Wmin. An example where the pulse disappears is shown.
In such a case, the occurrence of distortion cannot be suppressed near a predetermined level.

On the other hand, in this embodiment, as described above, the risk of suffering such a problem is extremely reduced. For example, if the widths of the pulses P1 and P2 shown at both ends in FIG. 3 are smaller than the Wmin, the pulses P1 and P2 are not output, but in FIG. 3, the pulses P1 and P2 are sandwiched between these pulses P1 and P2. Since the three pulses having a larger delay amount, that is, a wider width are output, the output pulse does not disappear at all during the period.
Further, when the five pulses having different widths shown in FIG. 3 are considered as a group, pulses having an average width of these five pulse widths (hereinafter referred to as “average width”) are obtained during this period. It can be seen as being output. The average width can be generally smaller than the minimum value Wmin. In other words, from this point of view, in the present embodiment, it is possible to obtain an output pulse exceeding the limit of the minimum value Wmin.
Thus, in this embodiment, the time when the output pulses OutP and OutM are eliminated can be shortened as much as possible.

The above embodiment is merely an example of a class D amplifier circuit according to the present invention, and various modifications can be made. For example, in the above-described embodiment, the delay amount is sequentially repeated as small, medium, large, medium, small, medium, large,... By the action of the up / down counter 70 (see FIG. 3). In the present invention, instead of this, operations such as small, medium, large, small, medium, large, small,... Are repeated sequentially until the delay amount reaches the maximum value and then returns to the minimum value again. A form may be adopted. In this case, a “reset signal” (not shown) for resetting the count value of the up / down counter 70 may be used instead of the “down signal” in the above embodiment. According to this, for example, the count value of the up / down counter 70 increases stepwise by the input of the up signal for a fixed time, and then returns to the initial value by the input of the reset signal.
In any case, when the increase / decrease of the delay amount is repeatedly arranged in a certain order, the specific configuration of the delay amount variable circuit 50, the up / down counter 70, etc. is compared to the case where it is not so. It is possible to obtain an advantage that can be configured more simply.
However, depending on the case, a form in which the delay amount changes more randomly (for example, a form in which small, large, medium, small, large, medium,... Are repeated, or a form in which the delay amount is correctly and randomly changed, etc. is included. ) Is also possible. The present invention includes such a form within the scope.

  In the above embodiment, n in FIG. 2 is “3”, but the present invention is not limited to this point as a matter of course. In addition, the said n should just be 2 or more, but when it is 3 or more, the increase or decrease in the delay amount increases in order from the smallest as described above (or vice versa). Is preferably carried out. According to this, the adjustment of the pulse width is performed comprehensively, so that the effect of shortening the time when the output pulses OutP and OutM are eliminated as much as possible can be more effectively obtained. Moreover, according to this form, control is also comparatively easy.

It is a block diagram which shows the structure of the class D amplifier circuit 100 which concerns on this embodiment. It is a block diagram which shows an example of a structure of a delay amount variable circuit and an up / down counter. It is a figure which shows the example of the output pulse by the class D amplifier circuit 100 which concerns on this embodiment. It is a figure which shows the example of an output pulse in case the up / down counter 70 of FIG. 1 does not exist and a delay amount is unchanged. It is a block diagram which shows the structure of the conventional class D amplifier circuit using a delay circuit. It is a figure which shows the output pulse in the time of a no-signal input and a minute signal input.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Operational amplifier, 12a, 12b ... Comparator, 20 ... Triangular wave generation circuit, 40 ... Output stage circuit, 50 ... Delay amount variable circuit, 70 ... Up / down counter, 100 ... Class D amplifier circuit, X1 ... PWM signal generation part, X2: logic circuit unit, X3: adjustment unit.

Claims (3)

Pulse width modulation means for generating a first signal and a second signal by performing pulse width modulation on an input signal;
Delay means capable of delaying the second signal to generate a delayed second signal and controlling a delay time;
Output pulse generating means for generating a first output pulse signal and a second output pulse signal to be output to the outside based on the first signal and the delayed second signal;
Adjusting means for adjusting the pulse width of the first output pulse signal and the second output pulse signal to be a predetermined width;
With
The adjusting means includes
Delay time control means for controlling the delay time of the delay means to be different by repeatedly selecting N kinds of predetermined delay times (N is an integer of 2 or more) in a predetermined order ;
A class D amplifier circuit. The N types of delay times are delays having different lengths n (1), n (2),..., N (N) (n (1) <n (2) <... <n (N)). Including time,
The delay time control means includes
The delay times having n (1), n (2),..., N (N) are expressed as n (1), n (2),..., N (N), n (N-1), n (N The class-D amplification according to claim 1, wherein delay times are selected in the order of -2), ..., n (2), and the delay time of the delay means is controlled by repeating the selection of this order. circuit. The N types of delay times are delays having different lengths n (1), n (2),..., N (N) (n (1) <n (2) <... <n (N)). Including time,
The delay time control means includes
The delay times having n (1), n (2),..., N (N) are selected in the order of n (1), n (2),. by repeating the selection, D-class amplifier circuit according to claim 1, characterized by controlling the delay time of the delay means.

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