TWI665866B - Modulation selecting circuit of audio amplifier - Google Patents

Abstract

A modulation selection circuit for an audio amplifier includes a signal generation circuit, a detection circuit, and a selection circuit. The signal generating circuit is used for generating a three-ary modulation signal and a four-dimensional modulation signal. The detection circuit is used to generate a mode selection signal according to at least the ternary modulation signal. The selection circuit is used to select and output one of the quaternary modulation signal and the ternary modulation signal to an output stage of the audio amplifier according to the mode selection signal.

Description

Modulation selection circuit of audio amplifier

The invention relates to a modulation selection circuit for an audio amplifier, and more particularly to a signal selection circuit for an audio amplifier operating in a ternary modulation mode and a quaternary modulation mode.

In audio applications, analog amplifiers are one of the important components in audio systems. Due to the advantages of high efficiency and low power consumption, Class D amplifiers have been widely used in audio systems in recent years. Since the output waveform of a Class D amplifier is at one of a high logic level (i.e., power supply voltage) and a low logic level (i.e., ground voltage), rather than a common analog voltage level, ideally the output stage If the power transistor is not turned on, no current will flow.

At present, the modulation method commonly used in Class D amplifiers is the pulse width modulation (PWM) method, which is divided into two types: quaternary modulation mode and ternary modulation mode. In the quaternary modulation mode, the output stage of the Class D amplifier will have four operating modes. For the switching mode of the output stage of the Class D amplifier in this mode, please refer to the description of the US patent US6262632. Class D amplifiers use four types of input signals according to the input signal of the audio source. Out-of-grade operating mode to drive loads such as speakers. The quaternary modulation operation of the class D amplifier has better total harmonic distortion (THD, Total Harmonic Distortion) and lower noise at a relatively large output power.

Compared with the quaternary modulation mode, the output stage of the Class D amplifier has three operating modes in the ternary modulation mode (in this mode, the two ends of the load will not be connected to the power supply voltage at the same time). The ternary modulation operation of the class D amplifier has a lower idle current at a relatively small output power. Therefore, how to properly switch the operation mode of the class D amplifier according to different output power to obtain better results is one of the topics of the current class D amplifier.

According to an embodiment of the present invention, a modulation selection circuit of an audio amplifier includes a signal generation circuit, a detection circuit, and a selection circuit. The signal generating circuit is used for generating a three-ary modulation signal and a four-dimensional modulation signal. The detection circuit is used to generate a mode selection signal according to at least the ternary modulation signal. The selection circuit is used to select and output one of the quaternary modulation signal and the ternary modulation signal to an output stage of the audio amplifier according to the mode selection signal.

200‧‧‧Audio Amplifier

201‧‧‧Modulation selection circuit

210‧‧‧gain stage

220‧‧‧ Integrator

230‧‧‧output stage

261,262‧‧‧Filter

310‧‧‧Signal generating circuit

311‧‧‧ Comparator

312‧‧‧ Comparator

313‧‧‧ Comparator

314‧‧‧Ternary modulation signal generating circuit

3141‧‧‧XOR gate

3142‧‧‧AND Gate

3143‧‧‧Inverter

3144‧‧‧NOR gate

320‧‧‧detection circuit

321‧‧‧Counting circuit

3211‧‧‧ Counter

3212‧‧‧ Latching Circuit

3213‧‧‧ Inverter

322‧‧‧Counting circuit

3221‧‧‧Counter

3222‧‧‧ Latching Circuit

3223‧‧‧Inverter

323‧‧‧pulse loss detection circuit

3231‧‧‧pulse missing logic circuit

3232‧‧‧Latching circuit

3233‧‧‧Zero level detection circuit

324‧‧‧Reset circuit

3241‧‧‧NOR Gate

3242‧‧‧ Counter

325‧‧‧output circuit

3251‧‧‧ Latching Circuit

326‧‧‧zero level detection circuit

3261‧‧‧NOR Gate

330‧‧‧Selection circuit

331‧‧‧Multiplexer

332‧‧‧Multiplexer

R1, R2‧‧‧Resistance

The first figure shows the total harmonic distortion and noise distributions obtained when the Class D amplifier operates in quaternary modulation mode and ternary modulation mode at different output powers.

The second figure shows a block diagram of an audio amplifier with a modulation selection circuit combined with an embodiment of the present invention.

The third figure shows a schematic circuit diagram of the modulation selection circuit combined with an embodiment of the present invention.

The fourth figure shows a circuit diagram of the detection circuit combined with an embodiment of the present invention.

The fifth graph shows one possible waveform of the signal shown in the fourth graph.

Certain terms are used in the description and the scope of subsequent patent applications to refer to specific elements. Those of ordinary skill in the art will understand that manufacturers may use different terms to refer to the same components. The scope of this specification and subsequent patent applications does not take the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a criterion for distinguishing components. "Inclusion" mentioned throughout the specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." In addition, the term "coupled" includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be electrically connected directly to the second device or indirectly electrically connected to the second device through other devices or connection means.

The first figure shows the total harmonic distortion and noise (THD + N) distributions obtained when the Class D amplifier operates in the quaternary modulation mode and the ternary modulation mode at different output powers (Pout). As shown in the first figure, at a relatively small output power, the Class D amplifier operates in the quaternary modulation mode and the ternary modulation mode. The total harmonic distortion and noise are very close. However, at relatively large output powers, the total harmonic distortion and noise obtained by a Class D amplifier operating in the quaternary modulation mode will be less than when it operates in the ternary modulation mode. In addition, at a relatively small output power, the Class D amplifier will have a lower idle current when operating in the ternary modulation mode. In consideration of total harmonic distortion, noise and idle current, the audio amplifier in the present invention will operate in a ternary modulation mode at a relatively small output power, and will operate in a quaternary mode at a relatively large output power. Modulation mode.

The second figure shows a block diagram of an audio amplifier 200 with a modulation selection circuit 201 according to an embodiment of the present invention. In this embodiment, the audio amplifier 200 is a Class D amplifier, and the audio amplifier 200 includes a gain stage 210, an integrator 220, the modulation selection circuit 201, an output stage 230, two feedback resistors R1 and R2 and two filters 261 and 262. The modulation selection circuit 201 is used to generate a quaternary modulation signal and a ternary modulation signal, and output one of the quaternary modulation signal and the ternary modulation signal to the modulation mode after the modulation mode is determined. Output stage 230. The output stage 230 generates output signals OUTp and OUTn to the filters 261 and 262.

The third figure shows a schematic circuit diagram of the modulation selection circuit 201 according to an embodiment of the present invention. The modulation selection circuit 201 includes a signal generation circuit 310, a detection circuit 320, and a selection circuit 330. The signal generating circuit 310 includes a plurality of comparators 311, 312, and 313, and a ternary modulation signal generating circuit 314. The comparators 311 and 312 are used to compare the output signal of the integrator 220 and a triangle wave signal to generate the quaternary modulation signal, wherein the four The meta-modulation signal includes a positive quaternary modulation signal QP and a negative quaternary modulation signal QN. The comparator 313 compares one of the output signals of the integrator 220 with a common voltage VCM. In one embodiment, the common voltage VCM is set to half of the power supply voltage (0.5 × VDD), but the invention is not limited thereto. An output terminal of the comparator 313 is coupled to a node N1.

The ternary modulation signal generating circuit 314 is configured to generate the ternary modulation signal according to the positive quaternary modulation signal QP and the negative quaternary modulation signal QN. The ternary modulation signal includes a positive ternary modulation signal. TP and a negative ternary modulation signal TN. In an embodiment of the present invention, the ternary modulation signal generating circuit 314 includes an XOR gate 3141, an AND gate 3142, an inverter 3143, and a NOR gate 3144. The input terminal of the XOR gate 3141 receives the positive quaternary modulation signal QP and the negative quaternary modulation signal QN, and its output terminal is coupled to a node N2. The AND gate 3142 receives signals from the nodes N1 and N2 to generate the positive ternary modulation signal TP. An input terminal of the inverter 3143 is coupled to the node N2. The NOR gate 3144 receives a signal from the node N1 and an output signal of the inverter 3143 to generate the negative ternary modulation signal TN.

The detection circuit 320 is configured to receive the positive ternary modulation signal TP and the negative ternary modulation signal TN, thereby generating a mode selection signal SEL. The selection circuit 330 includes two multiplexers (MUX) 331 and 332. An input terminal S of the multiplexer 331 receives the positive quaternary modulation signal QP, an inverting input terminal S / receives the positive ternary modulation signal TP, and a selection terminal Sel receives the mode selection signal SEL. An input terminal S of the multiplexer 332 receives the negative quaternary modulation signal QN and an inverting phase. The input terminal S / receives the negative ternary modulation signal TN and a selection terminal Sel receives the mode selection signal SEL. In addition, the outputs of the multiplexers 4901 and 4902 are coupled to the output stage 230 of the audio amplifier 200 in the second figure.

The fourth figure shows a circuit diagram of the detection circuit 320 combined with an embodiment of the present invention. As shown in the fourth figure, the detection circuit 320 includes a plurality of counting circuits 321 and 322, a pulse wave loss detection circuit 323, a reset circuit 324, an output circuit 325, and a zero level detection circuit 326. The counting circuit 321 includes a counter 3211, a latch circuit 3212, and an inverter 3213. In this embodiment, the counter 3211 and the latch circuit 3212 are composed of D flip-flops, but the present invention should not be limited thereto.

An input terminal of the inverter 3213 receives the negative ternary modulation signal TN. The input terminal of the counter 3211 receives the positive ternary modulation signal TP, and the reset terminal thereof receives the output signal of the inverter 3213. During operation, when the output signal of the amplifier 200 is a high-power signal (the voltage swing of the input signal is large at this time), one of the positive ternary modulation signal TP and the negative ternary modulation signal TN will have a high density. Number of pulse waves, while the other has no pulse waves. In this embodiment, when the pulse wave number of the positive ternary modulation signal TP is counted up to a specific number of times (for example, twice) by the counter 3211 and when the negative ternary modulation signal TN is counted by the counter 3211, there is no When the pulse wave is generated, it indicates that the output signal of the amplifier 200 is a high-power signal, so the output terminal of the counter 3211 outputs a high level signal, that is, the count signal TP2 outputs a logic 1 level. An input terminal of the latch circuit 3212 is connected to the power voltage, and a clock input terminal thereof receives the counting signal. TP2. When a rising edge of the counting signal TP2 is detected by the latch circuit 3212, a signal TNL having a logic 1 level is generated by the latch circuit 3212, which indicates that there is no pulse of the negative ternary modulation signal TN Wave was detected. In other words, the negative ternary modulation signal TN has a missing pulse wave.

The counting circuit 322 includes a counter 3221, a latch circuit 3222, and an inverter 3223. In this embodiment, the counter 3221 and the latch circuit 3222 are composed of D-type flip-flops, but the present invention should not be limited thereto.

An input terminal of the inverter 3223 receives the positive ternary modulation signal TP. An input terminal of the counter 3221 receives the negative ternary modulation signal TN, and a reset terminal R / thereof receives an output signal of the inverter 3223. When the output signal of the amplifier 200 is a high-power signal during operation, one of the positive ternary modulation signal TP and the negative ternary modulation signal TN will have a high density pulse wave number, while the other will not Pulse wave is generated. In this embodiment, when the pulse wave number of the negative ternary modulation signal TN is counted up to a specific number of times (for example, twice) by the counter 3221 and when the positive ternary modulation signal TP is counted by the counter 3221, there is no When the pulse wave is generated, it indicates that the output signal of the amplifier 200 is a high-power signal, so the output terminal of the counter 3221 outputs a high level signal, that is, the count signal TN2 outputs a logic 1 level. An input terminal of the latch circuit 3222 is connected to the power voltage, and a clock input terminal thereof receives the counting signal TN2. When a rising edge of the counting signal TN2 is detected by the latch circuit 3222, a signal TPL having a logic 1 level is generated by the output terminal of the latch circuit 3222, which indicates that there is no positive ternary modulation signal TP The pulse wave was detected. In other words, the positive ternary modulation signal TP has a pulse Wave is missing.

The pulse wave loss detection circuit 323 includes a pulse wave loss logic circuit 3231, a latch circuit 3232, and a zero level detection circuit 3233. In this embodiment, the latch circuit 3232 is composed of a D-type flip-flop, and the pulse loss logic circuit 3231 is composed of an AND gate, but the present invention should not be limited to this. The pulse wave loss logic circuit 3231 is configured to generate a pulse wave loss signal P_Loss according to the signals TPL and TNL. The zero-level detection circuit 3233 is configured to detect that a zero-crossing signal ZC is generated when the voltage levels of the input signals INp and INn of the amplifier 200 are zero.

An input terminal of the latch circuit 3232 receives the pulse wave loss signal P_Loss, and a clock input terminal thereof is connected to an output terminal of the zero level detection circuit 3233. When a rising edge of the zero-crossing signal ZC is detected by the latch circuit 3232, it indicates that the voltage levels of the input signals INp and INn of the amplifier 200 reach the zero level, and the pulse loss signal P_Loss will be regarded as a The determination signal DET is output at the output terminal of the latch circuit 3232. Specifically, when the signals TPL and TNL are both logic 1 signals, that is, each of the counting signals TP2 and TN2 has a logic 1 level at least once, the pulse wave loss detection circuit 323 detects the Both the positive ternary modulation signal TP and the negative ternary modulation signal TN have a pulse wave loss phenomenon at least once, and the pulse wave loss signal P_Loss will output a logic 1 level as a judgment signal DET.

The zero level detection circuit 326 includes a NOR gate 3261. The NOR gate 3261 receives the positive quaternary modulation signal QP and the negative quaternary modulation signal. QN, the positive ternary modulation signal TP and the negative ternary modulation signal TN, thereby generating a zero-level crossing signal ZC2. The zero level crossing signal ZC2 indicates that the positive quaternary modulation signal QP, the negative quaternary modulation signal QN, the positive ternary modulation signal TP, and the negative ternary modulation signal TN are all at logic 0 level.

The output circuit 325 includes a latch circuit 3251. In this embodiment, the latch circuit 3251 is composed of a D-type flip-flop, but the invention should not be limited thereto. An input terminal of the latch circuit 3251 receives the determination signal DET, and a clock input terminal thereof receives the zero-level crossing signal ZC2. When a rising edge of the zero level crossing signal ZC2 is detected by the latch circuit 3251, it indicates that the positive quaternary modulation signal QP, the negative quaternary modulation signal QN, the positive ternary modulation signal TP, and the The negative ternary modulation signal TN is all at a logic 0 level, and the determination signal DET is output as the mode selection signal SEL. Specifically, when the pulse wave loss detection circuit 323 detects that the positive ternary modulation signal TP and the negative ternary modulation signal TN both have a pulse wave loss phenomenon at least once, that is, the input signal of the amplifier 200 When the voltage swing is large, the determination signal DET has a logic 1 level and is output as the mode selection signal SEL. Accordingly, the selection circuit 330 selects and outputs the quaternary modulation signal (ie, the positive quaternary modulation signal QP and the negative ternary modulation signal QN) to the output stage 230 in the second figure.

The reset circuit 324 includes a NOR gate 3241 and a counter 3242. In this embodiment, the counter 3242 is composed of a D-type flip-flop, but the present invention should not be limited to this. The NOR gate 3241 receives the counting signals TP2 and TN2 to generate a signal SIG. An input of the counter 3242 receives The signal is SIG. When the output signal of the amplifier 200 is a low-power signal, the positive ternary modulation signal TP and the negative ternary modulation signal TN have interleaved pulse waves. At this time, the count signals TP2 and TN2 output a logic 0 level and have no pulse wave loss phenomenon. When the counter 3242 receives the signal SIG of the logic 1 level because of the logic 0 levels of the counting signals TP2 and TN2, after a period of time (for example, after 1 second), the counter 3242 generates a reset signal RESET1 and outputs To these latch circuits 3212,3222, and 3232. In this way, the determination signal DET is output as the mode selection signal SEL. Accordingly, the selection circuit 330 selects and outputs the ternary modulation signal (ie, the positive ternary modulation signal TP and the negative ternary modulation signal TN) to the output stage 230.

The audio amplifier in the present invention can enter the ternary modulation mode from the ternary modulation mode, and then enter the ternary modulation mode from the quaternary modulation mode; it can also enter the ternary modulation mode from the quaternary modulation mode, and then From ternary modulation mode to quaternary modulation mode. For example, when the pulse loss detection circuit 323 detects that the positive ternary modulation signal TP and the negative ternary modulation signal TN both have a pulse loss phenomenon at least once, it indicates that the output signal of the amplifier 200 is large. Power signal. The determination signal DET has a logic 1 level and is output as the mode selection signal SEL. Accordingly, the selection circuit 330 selects and outputs the quaternary modulation signal (ie, the positive quaternary modulation signal QP and the negative quaternary modulation signal QN) to the output stage 230.

The fifth graph shows one possible waveform of the signal shown in the fourth graph. Referring to the fifth figure, the input signal of the amplifier 200 (presented in a differential manner) The signals INn and INp) have large voltage swings from time t1 to t5. At time t2, two pulses of the positive ternary modulation signal TP have been counted by the counter 3211, and the counter 3211 has not counted any pulses of the negative ternary modulation signal TN, so the count signal TP2 is output Logic 1 level. The count signal TP2 triggers the latch circuit 3212, and outputs the signal TNL having a logic 1 level.

At time t3, two pulses of the negative ternary modulation signal TN have been counted by the counter 3221, and the counter 3221 has not counted any pulses of the positive ternary modulation signal TP, so the count signal TN2 Output logic 1 level. The count signal TN2 triggers the latch circuit 3222, and outputs the signal TPL with a logic 1 level. With the pulse wave loss logic circuit 3231 implemented by an AND gate, the pulse wave loss signal P_Loss outputs a logic 1 level.

At time t4, the zero-level detection circuit 3233 detects that the voltage level of the input signal of the amplifier 200 is the zero level, and outputs the zero-crossing signal ZC having a logic 1 level. The pulse wave loss signal P_Loss will be output as a logic 1 level as the judgment signal DET. The judgment signal DET is then output for the mode selection signal SEL. The mode selection signal SEL instructs the selection circuit 330 to select and output the quaternary modulation signal at the zero level crossing signal ZC2 to indicate the positive quaternary modulation signal QP, The negative quaternary modulation signal QN, the positive ternary modulation signal TP, and the negative ternary modulation signal TN are all logic 0 bits on time.

At time t5, the output signal of the amplifier 200 is a low-power signal, and the count signals TP2 and TN2 output a logic 0 level. With the operation of the NOR gate 3241, the signal SIG outputs a logic 1 level. At the counter 3242 After counting for a period of time (for example, 1Sec), at time t6, the reset signal RESET1 is output to reset the latch circuits 3212, 3222, and 3232 so that the signals TNL, TPL, and the pulse wave are lost. P_Loss and the judgment signal DET output a logic 0 level. The judgment signal DET is connected to output the logic 0 level for the mode selection signal SEL. The mode selection signal SEL instructs the selection circuit 330 to select and output the ternary modulation signal. The zero crossing signal ZC2 indicates the positive quaternary modulation The change signal QP, the negative quaternary modulation signal QN, the positive ternary modulation signal TP, and the negative ternary modulation signal TN are all logic 0 bits on time.

In summary, the class D amplifier of the present invention will operate in a quaternary modulation mode at a relatively large output power, and will operate in a ternary modulation mode at a relatively small output power. According to this operation mode, when the output power is small, the class D amplifier of the present invention will have a lower idle current; and when the output power is large, the class D amplifier of the present invention will have better total harmonic distortion and Noise

The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and should be covered by the scope of subsequent patent applications.

Claims (9)

A modulation selection circuit for an audio amplifier includes: a signal generating circuit for generating a ternary modulation signal and a quaternary modulation signal; a detection circuit coupled to the signal generation circuit and the detection circuit Used to generate a mode selection signal according to at least the ternary modulation signal; and a selection circuit coupled to the signal generation circuit and the detection circuit, the selection circuit is used to select and output the quaternary according to the mode selection signal One of the modulation signal and the ternary modulation signal goes to an output stage of the audio amplifier. According to the modulation selection circuit of the first patent application range, wherein the ternary modulation signal includes a positive ternary modulation signal and a negative ternary modulation signal, the detection circuit includes: a first counting circuit for: Generating a first counting signal according to the positive ternary modulation signal and the negative ternary modulation signal, wherein the first counting signal accumulates a specific number of times in the pulse wave of the positive ternary modulation signal and when the negative ternary modulation signal is The modulation signal always outputs a first logic level when no pulse wave is generated. A second counting circuit is configured to generate a second counting signal according to the positive ternary modulation signal and the negative ternary modulation signal. The second count signal accumulates a specific number of pulses in the negative ternary modulation signal and outputs a second logic level when the positive ternary modulation signal has been generated without a pulse wave; a pulse wave loss detection circuit, Coupled to the first counting circuit and the second counting circuit, the pulse wave loss detecting circuit is configured to generate a judgment signal based on at least the first counting signal and the second counting signal; and an output circuit is coupled Lost in the pulse A detection circuit, the output circuit is configured to generate the mode selection signal according to at least the judgment signal; wherein, when the judgment signal instructs the first counting signal to output the first logic level at least once and the second counting signal to output the When the second logic level is at least once, the mode selection signal instructs the selection circuit to select and output the quaternary modulation signal to the output stage of the audio amplifier. The modulation selection circuit according to item 2 of the scope of patent application, wherein the pulse wave loss detection circuit includes a pulse wave loss logic circuit coupled to the first counting circuit and the second counting circuit, and the pulse wave loss logic A circuit for generating a missing pulse signal according to the first counting signal and the second counting signal; a zero level detecting circuit for detecting a voltage level of an input signal of the audio amplifier to be zero A zero-crossing signal is generated on time; and a latch circuit is coupled to the pulse-loss logic circuit and the zero-level detection circuit, and the latch circuit is used to receive the pulse-loss signal and the zero-cross signal. When the zero-crossing signal is generated, the missing pulse wave signal is output as the determination signal to the output circuit. According to the modulation selection circuit of the second patent application range, wherein the quaternary modulation signal includes a positive quaternary modulation signal and a negative quaternary modulation signal, the detection circuit includes: a zero level detection circuit, Used to generate a zero level crossing signal according to the positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal and the negative ternary modulation signal; wherein when the zero level crossing signal When the positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal and the negative ternary modulation signal are all at logic 0 level, the output circuit outputs the judgment signal as the mode selection signal . The modulation selection circuit according to item 4 of the scope of patent application, wherein the output circuit includes: a latch circuit for receiving the judgment signal, the mode selection signal, and a reset signal; wherein when the reset signal has a At the third logic level, the latch circuit is reset, and the mode selection signal is output to instruct the selection circuit to select and output the ternary modulation signal to the output stage of the audio amplifier. When the zero level crossing signal indicates the The positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal, and the negative ternary modulation signal are all logic 0 bits on time. According to the modulation selection circuit of the first patent application range, wherein the ternary modulation signal includes a positive ternary modulation signal and a negative ternary modulation signal, the detection circuit includes: a first counting circuit for: Generating a first counting signal according to the positive ternary modulation signal and the negative ternary modulation signal, wherein the first counting signal accumulates a specific number of times in the pulse wave of the positive ternary modulation signal and when the negative ternary modulation signal The modulation signal always outputs a first logic level when no pulse wave is generated. A second counting circuit is configured to generate a second counting signal according to the positive ternary modulation signal and the negative ternary modulation signal. The second count signal accumulates a specific number of pulses in the negative ternary modulation signal and outputs a second logic level when the positive ternary modulation signal has been generated without a pulse wave; a pulse wave loss detection circuit, Coupled to the first counting circuit and the second counting circuit, the pulse wave loss detecting circuit is used to generate a judgment signal based on at least the first counting signal and the second counting signal; an output circuit is coupled to The Pulse Lost Detection Circuit, the output circuit is used to generate the mode selection signal according to at least the judgment signal; and a reset circuit is coupled to the pulse wave loss detection circuit, and the reset circuit is used to adjust the ternary modulation signal and The negative ternary modulation signal generates a reset signal to the pulse wave loss detection circuit; wherein, when the reset signal has a third logic level, the pulse wave loss detection circuit is reset, and the judgment A signal indicating that the first counting signal does not have a first logic level and the second counting signal does not have the second logic level and is output to the output stage; and when the judgment signal indicates that the first counting signal does not have a first logic level When the level and the second count signal do not have the second logic level, the mode selection signal instructs the selection circuit to select and output the ternary modulation signal to the output stage of the audio amplifier. The modulation selection circuit according to item 6 of the patent application, wherein when a time interval indicating that the first counting signal does not have the first logic level and the second counting signal does not have the second logic level reaches a predetermined interval , The reset signal generated by the reset circuit has the third logic level. The modulation selection circuit according to item 6 of the scope of patent application, wherein the quaternary modulation signal includes a positive quaternary modulation signal and a negative quaternary modulation signal. The detection circuit includes: a zero level detection circuit, Used to generate a zero level crossing signal according to the positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal and the negative ternary modulation signal; wherein when the zero level crossing signal When the positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal and the negative ternary modulation signal are all at logic 0 level, the output circuit outputs the judgment signal as the mode selection signal . The modulation selection circuit according to item 8 of the patent application scope, wherein the output circuit includes: a latch circuit for receiving the judgment signal, the mode selection signal and a reset signal; wherein when the reset signal has a At the third logic level, the latch circuit is reset, and the mode selection signal is output to instruct the selection circuit to select and output the ternary modulation signal to the output stage of the audio amplifier. When the zero level crossing signal indicates the The positive quaternary modulation signal, the negative quaternary modulation signal, the positive ternary modulation signal, and the negative ternary modulation signal are all logic 0 bits on time.