CN113691223A

CN113691223A - Audio amplifier with idle mode

Info

Publication number: CN113691223A
Application number: CN202110537943.8A
Authority: CN
Inventors: R·穆克霍帕德亚伊; E·墨菲; M·费尔德; S·奎因
Original assignee: Maxim Integrated Products Inc
Current assignee: Maxim Integrated Products Inc
Priority date: 2020-05-19
Filing date: 2021-05-18
Publication date: 2021-11-23

Abstract

An audio amplifier employs an idle mode to reduce power consumption and improve the efficiency of the amplifier. The audio amplifier includes a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal into differential first and second quantized signals, each having a common-mode duty cycle. When the level of the analog input signal is below a threshold level, the modulator shifts a common-mode duty cycle of each of the first and second quantized signals such that the common-mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switch between a supply voltage and a second voltage based on the respective first and second quantized signals.

Description

Audio amplifier with idle mode

Background

The audio amplifier amplifies the low power electronic audio signal and produces an output signal that is amplified to a power level sufficient to drive a speaker to produce sound. Several types or classes of audio amplifiers have been developed that are categorized by a class indicator of one or two letters (e.g., class a, class B, class a/B, class D, etc.). Class D amplifiers are often used in applications where low power consumption is important. Class D amplifiers operate with amplifying devices such as transistors, usually MOSFETs, as electronic switches, rather than as linear gain devices as in other classes of amplifiers. The MOSFETs switch rapidly back and forth between the two power rail voltages and are fed by a modulator that employs one of several common modulation techniques (e.g., Pulse Width Modulation (PWM), Pulse Density Modulation (PDM), delta-sigma modulation (DSM), etc.) to encode the audio input signal into a pulse sequence. The modulated audio signal may then be passed through a low-pass LC filter to block high frequency pulses, and then used to drive a load such as a speaker. Since the paired output transistors are never turned on at the same time, there is no other path for current to flow except for the low pass filter/speaker, making the class D amplifier very efficient.

Drawings

Specific embodiments are described with reference to the accompanying drawings. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items. Various embodiments or examples ("examples") of the disclosure are disclosed in the following detailed description and the accompanying drawings. The figures are not necessarily to scale. Generally, the operations of the disclosed processes may be performed in any order, unless otherwise provided in the claims.

Fig. 1 is a block diagram illustrating an amplifier configured with an idle mode according to an example embodiment of the present disclosure.

Fig. 2 is a circuit diagram further illustrating an example audio amplifier employing an idle mode in accordance with the present disclosure.

Fig. 3A, 3B and 3C are signal diagrams illustrating an implementation of an idle mode of an audio amplifier (such as the example amplifier shown in fig. 1 and 2) according to the present disclosure.

Fig. 4 is a graph illustrating the relationship between power consumed by a load (e.g., a speaker) driven by an amplifier and the duty cycle of the output signal of the amplifier according to the present disclosure.

Fig. 5 is a circuit diagram illustrating a second example audio amplifier with an idle mode according to the present disclosure.

Fig. 6 is a signal diagram illustrating an implementation of an idle mode with programmable start-up time for an audio amplifier, such as the amplifier shown in fig. 5, in accordance with an embodiment of the present disclosure.

Fig. 7 is a signal diagram illustrating an implementation of an idle mode with programmable start-up time and extended idle periods for an example audio amplifier according to an embodiment of the present disclosure.

Fig. 8 is a flow chart illustrating a method for implementing an idle mode in an audio amplifier, such as the example amplifiers shown in fig. 1, 2, and 5, according to an example embodiment of the present disclosure.

Detailed Description

SUMMARY

Class D audio amplifiers used in smart speakers must drive higher and higher output voltages. However, in audio circuits using such amplifiers, the large voltage differential (dV/dt) is a major contributor to electromagnetic interference (EMI) emissions. It is desirable to reduce conducted EMI emissions, which are typically measured at outputs below 15 MHz. To achieve this reduction, audio circuits often employ low-pass LC filters that attenuate signals at frequencies above the cutoff frequency to filter EMI radiation from the output signal provided to the speaker.

Although a variety of modulator topologies may be used in modern class D amplifiers, one common topology (BD modulation) utilizes Pulse Width Modulation (PWM) with a triangular (or saw tooth) waveform generator or oscillator to encode the audio input signal. BD modulation modulates the duty cycle of the difference between the output signals so that its average content corresponds to the input analog signal. BD modulation provides superior audio performance (e.g., reduced plosives and clicks). However, BD modulation without (or with a low level of) audio signals consumes much more power than other common modulation techniques (such as AD modulation) when using a low-pass LC filter. BD modulation has significant common mode content in its output. Therefore, there is a correlation between the common mode duty cycle, the inductor current ripple, and the power consumption. Power consumption is highest when the common mode duty cycle is at or near fifty percent (50%), because the ripple current is greatest at these duty cycles.

Accordingly, an audio amplifier is disclosed that employs an idle mode when there is no audio signal or the audio signal is low to reduce power consumption and improve the efficiency of the amplifier. The amplifier includes a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal into differential first and second quantized signals, each having a common-mode duty cycle. When the level of the analog input signal is below a threshold level, the modulator shifts a common-mode duty cycle of each of the first and second quantized signals such that the common-mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switch between a supply voltage and a second voltage based on the respective first and second quantized signals. In an embodiment, the power stage continues to switch the first output signal and the second output signal between the supply voltage and the second voltage when the common-mode duty cycle of each of the first quantized signal and the second quantized signal is shifted.

A modulator suitable for use in an audio amplifier having an idle mode is also disclosed. The modulator includes an amplifier component configured to receive an analog audio input signal having a first voltage and to provide a differential first modulated signal and a second modulated signal, wherein the first modulated signal has a second voltage and the second modulated signal has a third voltage. The waveform generator generates a waveform signal having a fourth voltage centered on the common mode voltage. A comparator component is configured for receiving the waveform signal and the first and second modulated signals and for providing respective differential first and second quantized signals, wherein each of the first and second quantized signals has a common-mode duty cycle. During idle mode, when the first voltage is below a threshold voltage, the fourth voltage or at least one of the second voltage and the third voltage is increased or decreased to shift a common mode duty cycle of the first quantized signal and the second quantized signal such that the common mode duty cycles are one of greater than or less than fifty percent (50%). In an embodiment, the power stage continues to switch the first output signal and the second output signal between the supply voltage and the second voltage when the common-mode duty cycle of each of the first quantized signal and the second quantized signal is shifted.

In an embodiment, the amplifier disclosed herein may comprise a class D audio amplifier employing BD modulation. In such embodiments, the audio amplifier includes a BD modulator configured to receive an analog audio signal having a first voltage and an idle mode offset having an offset voltage. The BD modulator includes an amplifier component operable to provide a differential first modulated signal and a second modulated signal derived from the first voltage, wherein the first modulated signal has a second voltage and the second modulated signal has a third voltage. The triangular wave generator generates a triangular wave signal having a fourth voltage centered on the common mode voltage. A comparator assembly receives the triangular wave signal from the triangular wave generator and the first and second modulation signals from the amplifier assembly and provides respective differential first and second quantized signals, wherein each of the first and second quantized signals has a common-mode duty cycle. During idle mode, when the first voltage is below a threshold voltage, the BD modulator is configured to increase or decrease at least one of the second and third voltages or the fourth voltage to shift the common mode duty cycles of the first and second quantized signals such that the common mode duty cycles are one of greater than or less than fifty percent (50%). A power stage receives the first and second quantized signals and generates respective first and second output signals, wherein the first and second output signals switch between a supply voltage and a fifth voltage based on the first and second quantized signals. In an embodiment, the power stage continues to switch the first output signal and the second output signal between the supply voltage and the second voltage when the common-mode duty cycle of each of the first quantized signal and the second quantized signal is shifted. A low pass LC filter receives the first output signal and the second output signal from the power stage and filters out electromagnetic interference. The first output signal and the second output signal are configured to drive a speaker.

In an embodiment, the digital output signals are shifted according to the amplitude of the analog audio signal. For example, when the level (voltage) of the analog input signal is lower than the threshold level (voltage), the common mode duty cycle of each of the first and second quantized signals and the corresponding output signal is shifted until the level of the analog input signal is higher than a second threshold level (voltage), which is higher than the first threshold level (voltage).

Example embodiments

Fig. 1 illustrates an amplifier 100 configured with an idle mode in accordance with an example embodiment of the present disclosure. As shown, amplifier 100 includes a modulator 102 configured to receive an analog input signal (IN). The modulator 102 is operable to convert or modulate an analog input signal (IN) to provide a differential first (P) quantized signal (BR _ OUTP) and a second (N) quantized signal (BR _ OUTN). IN an embodiment, the modulator 102 employs Pulse Width Modulation (PWM) to encode the audio input signal (IN) into a pulse sequence to generate quantized signals (BR _ OUTP, BR _ OUTN). However, it is contemplated that modulator 102 may employ other modulation techniques, such as Pulse Density Modulation (PDM), Delta Sigma Modulation (DSM), and the like.

Amplifier 100 further includes an output stage 104 that receives the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) from modulator 102 and generates corresponding first (P) and second (N) output signals (OUTP) and (OUTN) configured to drive a resistive load 106, such as a speaker or the like. As shown, the output stage 104 may include a driver stage 108 and a power stage 110. In an embodiment, the power stage 110 includes two or more switching devices, such as power transistors (e.g., Field Effect Transistors (FETs), and particularly Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) in a half-bridge or full-bridge arrangement. The half-bridges switch the first output signal (OUTP) and the second output signal (OUTN) between a supply voltage and a second voltage based on the respective first quantized signal (BR _ OUTP) and second quantized signal (BR _ OUTN). The driver stage 108 receives the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) from the modulator 102, level shifts them as necessary, and drives the power transistors in the power stage 110.

The amplifier 100 may further comprise a low pass filter 108 between the output stage 104 and the load (loudspeaker) 106. The filter 108 receives the output signals (OUTP, OUTN) from the output stage 104 and filters electromagnetic interference from these signals (OUTP, OUTN). The filtered output signals (OUTP _ FLT, OUTN _ FLT) are then used to drive a load (speaker) 106. In an embodiment, the filter 108 comprises a low-pass LC filter that prevents high frequency switching energy from dissipating in the resistive load (speaker) 106.

The quantized signals (BR _ OUTP, BR _ OUTN) each comprise a common mode component having a common mode duty cycle. As the level (i.e., the voltage (V)) of the input signal (IN) decreases, the duty ratios of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) approach the common mode duty ratio. Therefore, when the input signal (IN) is not present, the level (voltage (V)) of the input signal (IN) is zero (0), making the duty ratio of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) equal to the common mode duty ratio, fifty percent (50%), resulting IN increased power usage and reduced efficiency of the amplifier 100.

According to the present disclosure, when there is no input signal (IN) or the input signal is very low, an idle mode of operation is set for amplifier 100 to reduce power consumption and improve the efficiency of amplifier 100. During the idle mode, when the level of the analog input signal (IN) falls below a threshold level, the modulator 102 is configured to shift the common-mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) such that the common-mode duty cycle is greater than or less than fifty percent (50%). For example, as shown IN fig. 1, when the level of the analog input signal (IN) falls below a threshold level, the modulator 102 is configured to receive an IDLE MODE OFFSET signal (IDLE MODE OFFSET) that causes the modulator 102 to shift the duty cycles of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN). IN an embodiment, the threshold level comprises a threshold voltage, and the modulator 102 compares the voltage level of the analog input signal (IN) to the threshold voltage. When the voltage level of the analog input signal (IN) falls below a threshold voltage, the modulator implements an idle mode to shift the common mode duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN). In an embodiment, the switching devices (e.g., MOSFETs arranged in a half-bridge) of the power stage 110 continue to switch the first output signal (OUTP) and the second output signal (OUTN) between the supply voltage and the second voltage when the common-mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) is shifted by fifty percent (50%). In an embodiment, the threshold voltage is substantially zero volts (0V). The threshold voltage may also be programmable so that it can be set, for example, using the input of the modulator 102. In an embodiment, the idle mode of amplifier 100 may be disabled. For example, the modulator 102 may be configured such that shifting of the common MODE duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) may be selectively disabled by an IDLE MODE OFFSET signal (IDLE MODE OFFSET).

In an embodiment, the amplifier 100 may be an audio amplifier, and may in particular be a class D audio amplifier. In such an embodiment, the load 106 may include a speaker and the analog input signal may include an analog audio signal. The audio amplifier may employ BD modulation such that the modulator 102 comprises a BD modulator. However, it is contemplated that other modulation schemes (e.g., AD modulation) may be utilized.

Fig. 2 illustrates an amplifier 200 configured with an idle mode in accordance with an example embodiment of the present disclosure. As with amplifier 100 of fig. 1, amplifier 200 is configured to receive an analog input signal having a common-mode component and drive a load 202 (e.g., a speaker, etc.) based on the input signal.

The amplifier 200 includes a modulator 204 having an amplifier component 206, which may include one or more amplifiers or other components. When there is no analog input signal, the amplifier component 206 receives a common-mode signal (VCM _ MOD) having a voltage equal to one-half of the common-mode voltage (VREFC/2). The amplifier component 206 generates a differential first (P) modulated signal (MODP) and a second (N) modulated signal (MODN), wherein the first modulated signal (MODP) has a second voltage and the second modulated signal (MODN) has a third voltage.

The modulator 204 further includes a waveform generator 208 for generating a waveform signal having a fourth voltage centered on a common mode Voltage (VREFC). In the illustrated embodiment, the waveform generator 208 includes a triangle wave generator configured to receive a waveform input signal (VCM _ TRI) that causes the waveform generator 208 to generate a triangle wave signal (V _ TRI) having a fourth voltage centered on the common mode voltage (VREFC/2). In other embodiments, a waveform generator 206 that generates other waveforms (e.g., a sawtooth wave) may be used. However, it is contemplated that such other waveforms will have a voltage that is also centered on the common mode Voltage (VREFC) when the idle mode is not enabled.

The comparator component 210 is coupled to the amplifier component 206 and the waveform generator 208 and receives the first modulated signal (MODP) and the second modulated signal (MODN) and the waveform (triangle wave) signal (V _ TRI). As shown in fig. 2, the comparator assembly 210 includes a first (P) comparator 212 having a positive analog input terminal receiving the first modulated signal (MODP) and a negative analog input terminal receiving the waveform (triangle wave) signal (V _ TRI). The first comparator 212 outputs a first (P) quantized signal (BR _ OUTP). As further shown, the comparator assembly 210 also includes a second (N) comparator 214 having a negative analog input terminal that receives the second modulated signal (MODN) and a positive analog input terminal that receives the waveform (triangle wave) signal (V _ TRI). The second comparator 214 outputs a second (N) quantized signal (BR _ OUTN).

In an embodiment, the comparator component employs Pulse Width Modulation (PWM) to encode the first modulated signal (MODP) and the second modulated signal (MODN) as a pulse sequence to generate the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN). However, it is contemplated that other modulation techniques may be utilized, such as Pulse Density Modulation (PDM), Delta Sigma Modulation (DSM), and the like.

The output stage of the amplifier 200 illustrated in fig. 2 employs a full bridge power stage 216 comprising two

half bridges

218, 220 that differentially drive a load (speaker) 202 in a bridge load (BTL) configuration. Each

half bridge

218, 220 includes two output switching devices, such as transistors (metal oxide semiconductor field effect transistors (MOSFETs) 222, 224 and 226, 228, respectively, are shown). The first half bridge 218 includes: a first P-channel MOSFET 222 having its gate coupled to the first (P) quantized signal generated by the comparator 212, its source coupled to a supply voltage rail (VSUPPLY)230, and its drain coupled to the load (speaker) 202; and a second n-channel MOSFET 224 having a gate coupled to the first (P) quantized signal generated by the comparator 212, a source coupled to a second voltage, such as a ground rail (VGND)232, and a drain coupled to the load (speaker) 202. The second half bridge 220 includes: a first p-channel MOSFET 226 having its gate coupled to the second (N) quantized signal generated by the comparator 214, its source coupled to a supply voltage rail (VSUPPLY)230, and its drain coupled to the load (speaker) 202; and a second N-channel MOSFET 224 having a gate coupled to the second (N) quantized signal generated by the comparator 214, a source coupled to a second voltage, such as ground rail (VGND)232, and a drain coupled to the load (speaker) 202. As shown, p-

channel MOSFETs

222, 226 and n-

channel MOSFETs

224, 228 operate as current-steering switches by alternately connecting their outputs (OUTP, OUTN) to a supply Voltage (VSUPPLY) and a second voltage (e.g., ground (VGND)), respectively, such that the resulting outputs (OUTP, OUTN) are high-frequency square waves.

A low

pass LC filter

234, 236 is provided between each

half bridge

216, 218 and the load (speaker) 202, respectively, to recover the amplified audio signal. The low-pass LC filters 234, 236 filter out electromagnetic interference from the output signals (OUTP, OUTN) thereby preventing high frequency switching energy from dissipating in the resistive load (speaker) 202.

Because the output signals (OUTP, OUTN) comprise square waves that are pulse-width modulated by the input audio signal, the duty cycle of the resulting output signals (OUTP, OUTN) is proportional to the level of the input signal. When no input signal is present, the duty cycle of the output signal (OUTP, OUTN) waveform is equal to fifty percent (50%).

In accordance with the present disclosure, the audio amplifier 200 illustrated in fig. 2 includes an idle mode of operation when there is no input signal or the input signal is very low to reduce power consumption and improve the efficiency of the amplifier 200. During idle mode, when the voltage of the analog input signal drops below a threshold level, the common mode component of the input signal (VCM _ MOD)204, whose voltage is equal to half the common mode voltage (VREFC/2), is input to the amplifier component 206. The modulator 202 is configured to shift a common mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) such that the common mode duty cycle is greater than or less than fifty percent (50%). In an embodiment, when the common mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) is shifted by fifty percent (50%), the p-

channel MOSFETs

222, 226 and the n-

channel MOSFETs

224, 228 continue to switch the first output signal (OUTP) and the second output signal (OUTN), respectively, between the supply Voltage (VSUPPLY) and the second voltage (e.g., ground (VGND)). In an embodiment, the threshold voltage is substantially zero volts (0V). The threshold voltage may also be programmable so that it can be set, for example, using the input of the modulator 202.

As shown in fig. 2, an IDLE MODE OFFSET signal (IDLE MODE OFFSET) is provided as an input to the waveform generator 206. The IDLE MODE OFFSET signal (IDLE MODE OFFSET) causes the waveform generator 206 to add (or subtract) a voltage OFFSET to (or from) the voltage of the waveform (triangle wave) input signal (VCM _ TRI) such that the voltage of the triangle wave signal (V _ TRI) increases (or decreases) and is therefore no longer centered on the common MODE voltage (VREFC/2). In other embodiments, the IDLE MODE OFFSET signal (IDLE MODE OFFSET) may cause the amplifier component 204 to add (or subtract) a voltage OFFSET to the voltage of the common MODE component of the input signal (VCM _ MOD) to cause the voltage of the differential first (P) and second (N) modulation signals (MODP, MODN) to increase (or decrease). An increase (or decrease) in either or both of the voltages of the waveform (triangle wave) signal (V _ TRI) and the first (P) and second (N) modulation signals (MODP, MODN) shifts the common mode duty cycle of the first and second quantized signals (BR _ OUTP, BR _ OUTN) output by the respective first and

second comparators

204, 206 in the comparator component 208 such that the common mode duty cycle of these quantized signals (BR _ OUTP, BR _ OUTN) is one of greater than or less than fifty percent (50%). In this way, the power consumed by the load (speaker) 202 is greatly reduced, thereby improving the efficiency of the amplifier 200.

In an embodiment, the idle mode of amplifier 200 may be disabled. For example, in an embodiment, the modulator 202 may be configured such that shifting of the common MODE duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) may be selectively disabled by disabling the IDLE MODE OFFSET signal (IDLE MODE OFFSET).

Fig. 3A, 3B and 3C illustrate idle mode implementations of the

example amplifiers

100, 200 illustrated in fig. 1 and 2, respectively. As shown in fig. 3A, when there is no analog input signal, the voltage of the common mode component (VCM _ MOD) is equal to half the common mode voltage (VREFC/2). Therefore, the voltage of the common mode component (VCM _ MOD) is equal to the average voltage of the waveform (triangular wave) input signal (VCM _ TRI) having a voltage (VCM _ MOD ═ VCM _ TRI) centered around half of the common mode voltage (VREFC/2). Thus, the voltage of the differential first (P) and second (N) modulation signals (MODP, MODN) is also equal to half the common mode voltage (VREFC/2) and thus also equal to the average voltage of the waveform (triangular wave) signal (V _ TRI). The quantized signals (BR _ OUTP, BR _ OUTN) and the resulting output signals (OUTP, OUTN) comprise square waves generated using pulse width modulation according to their respective modulation signals (MODP, MODN) and waveform (triangle wave) signals (V _ TRI). Thus, when there is no input signal, the duty cycle of the resulting quantized signal (BR _ OUTP, BR _ OUTN) and output signal (OUTP, OUTN) is equal to fifty percent (50%), and the differential output signal (OUTP-OUTN) is equal to zero (0).

Referring now to fig. 4, there is shown the relationship between the duty cycle of the quantized signals (BR _ OUTP, BR _ OUTN) and the output signals (OUTP, OUTN) of the

amplifiers

100, 200 as shown in fig. 1 and 2, and the amount of power required by the load (speaker). As shown, the amount of power required decreases as the duty cycle approaches zero percent (0%) and/or one hundred percent (100%) and increases as the duty cycle approaches fifty percent (50%). Therefore, when there is no analog input signal (IN), the consumed power is maximum, and thus the consumed power can be reduced by shifting the duty ratios of the quantized signals (BR _ OUTP, BR _ OUTN) and the output signals (OUTP, OUTN) by fifty percent (50%).

As shown in fig. 3B and 3C, in the idle mode, one or both of the voltage of the common mode component signal (VCM _ MOD) or the voltage of the waveform (triangle wave) input signal (VCM _ TRI) is added (or subtracted) with a voltage offset.

In fig. 3B, the voltage of the common mode component (VCM _ MOD) is added (or subtracted) with a voltage offset. Therefore, in the idle mode, the voltage of the common mode component (VCM _ MOD) is equal to half the common mode voltage shifted by the offset voltage ((VREFC/2) ± VOFFSET). As shown, the voltage of the common mode component (VCM _ MOD) is therefore no longer equal to the average voltage of the waveform (triangle wave) input signal (VCM _ TRI) having a voltage centered on the common mode voltage (VREFC/2). The voltage of the common mode component (VCM _ MOD) is shifted by the offset Voltage (VOFFSET) to increase (or decrease) the voltage of the modulation signal (MODP, MODN). In the illustrated embodiment, the voltage of the modulation signal (MODP, MODN) is also shifted (increased or decreased) by an offset voltage ((VREFC/2) ± VOFFSET) equal to half the common mode voltage. The voltage of the modulated signal (MODP, MODN) thus shifts (no longer equals) the average voltage of the waveform (triangular wave) signal (V _ TRI) having a voltage centered on the common-mode voltage (VREFC/2). The offset shifts a common mode duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) such that the common mode duty cycle of the quantized signals (BR _ OUTP, BR _ OUTN), and thus the common mode duty cycle of the output signals (OUTP, OUTN), is shifted by fifty percent (50%). However, because the output signals (OUTP, OUTN) are shifted by the same amount, the differential output signal (OUTP-OUTN) remains equal to zero (0).

In fig. 3C, instead, the voltage offset is added (or subtracted) to the waveform (triangle wave) input signal (VCM _ TRI) such that the average voltage of the waveform (triangle wave) input signal (VCM _ TRI) is centered at half the common mode voltage shifted by the offset voltage ((VREFC/2) ± VOFFSET). Therefore, in this embodiment, the average voltage of the waveform (triangle wave) input signal (VCM _ TRI) is no longer equal to the voltage of the common mode component (VCM _ MOD), which is equal to half the common mode voltage (VREFC/2). The average voltage of the waveform (triangle wave) signal (VCM _ TRI)) is shifted by the offset Voltage (VOFFSET) so that the average voltage of the waveform (triangle wave) signal (V _ TRI) is also increased (or decreased). In the illustrated embodiment, the average voltage of the waveform (triangle wave) signal (V _ TRI) is centered around the offset voltage ((VREFC/2) ± VOFFSET) shifted (increased or decreased) by half the common mode voltage. Therefore, the average voltage of the waveform (triangle wave) signal (V _ TRI) is shifted (no longer equal) to the voltage of the modulation signals (MODP, MODN) which are equal to half the common mode voltage (VREFC/2). The offset shifts a common mode duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) such that the common mode duty cycle of the quantized signals (BR _ OUTP, BR _ OUTN), and thus the common mode duty cycle of the output signals (OUTP, OUTN), is shifted by fifty percent (50%). Because the output signals (OUTP, OUTN) are shifted by the same amount, the differential output signal (OUTP-OUTN) remains equal to zero (0).

As can be seen from fig. 4, the common mode duty cycles of the output signals (OUTP, OUTN) are shifted away from fifty percent (50%) as shown in fig. 3B and 3C such that these common mode duty cycles are greater or less than fifty percent (50%) reduce the power consumed by the load, improving the efficiency of the amplifier.

Fig. 5 illustrates an amplifier 500 configured with an idle mode according to an example embodiment of the present disclosure. As with

amplifiers

100, 200 of fig. 1 and 2, amplifier 500 is configured to receive an analog input having a common mode component and drive a load 502 (e.g., a speaker, etc.) based on the input signal.

The amplifier 500 includes a modulator 504 having an amplifier assembly 506, which may include one or more amplifiers or other components. The amplifier component 506 receives the analog input signal (INP, INN), the common mode component (VCM _ MOD), and the output signal (OUTP, OUTN), and generates a differential first (P) modulation signal (MODP) and a second (N) modulation signal (MODN), wherein the first (P) modulation signal has a second voltage and the second (N) modulation signal has a third voltage.

The modulator 504 further comprises a waveform generator 508 for generating a waveform signal. In the illustrated embodiment, the waveform generator 508 includes a triangle wave generator configured to receive a waveform input signal (VCM _ TRI) that causes the waveform generator 508 to generate a triangle wave signal (V _ TRI) having a fourth voltage centered on the common mode voltage (VREFC/2) when the idle mode is not enabled. In other embodiments, a waveform generator 206 that generates other waveforms (e.g., a sawtooth wave) may be used. However, it is contemplated that such other waveforms will have a voltage that is also centered on the common mode Voltage (VREFC) when the idle mode is not enabled.

The comparator component 510 is coupled to the amplifier component 506 and the waveform generator 508, and receives the first modulated signal (MODP) and the second modulated signal (MODN) and the waveform (triangle wave) signal (V _ TRI). As shown in fig. 5, the comparator assembly 510 includes a first (P) comparator 512 having a positive analog input terminal receiving the first modulated signal (MODP) and a negative analog input terminal receiving the waveform (triangle wave) signal (V _ TRI). The first comparator 512 outputs a first (P) quantized signal (BR _ OUTP). As further shown, the comparator component 510 also includes a second (N) comparator 514 having a negative analog input terminal that receives the second modulated signal (MODN) and a positive analog input terminal that receives the waveform (triangle wave) signal (V _ TRI). The second comparator 514 outputs a second (N) quantized signal (BR _ OUTN).

The first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) are then passed to an output stage 515 that drives a load (speaker 502). In the illustrated embodiment, the output stage 515 includes a driver stage 516 and a power stage 518. The output stage 515 employs a full bridge power stage 518 comprising two

half bridges

520, 522 that differentially drive the load (speaker) 502 in a bridge load (BTL) configuration. Each

half bridge

520, 522 includes two output switching devices (e.g., power Field Effect Transistors (FETs)). In the illustrated embodiment, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 524, 526 and 528, 530, respectively, are shown. The first half bridge 520 includes: a first P-channel MOSFET 524 having its gate coupled to the first (P) quantized signal generated by the comparator 512, its source coupled to a supply voltage rail (VSUPPLY)532, and its drain coupled to the load (speaker) 502; and a second n-channel MOSFET 526 having a gate coupled to the first (P) quantized signal generated by the comparator 512, a source coupled to a second voltage, such as a ground rail (VGND)534, and a drain coupled to the load (speaker) 502. The second half bridge 522 includes: a first p-channel MOSFET 528 having its gate coupled to the second (N) quantized signal generated by the comparator 514, its source coupled to a supply voltage rail (VSUPPLY)532, and its drain coupled to the load (speaker) 502; and a second N-channel MOSFET 526 having a gate coupled to the second (N) quantized signal generated by the comparator 514, a source coupled to a second voltage, such as ground rail (VGND)534, and a drain coupled to the load (speaker) 502. As shown, p-

channel MOSFETs

524, 528 and n-

channel MOSFETs

526, 530 operate as current-steering switches by alternately connecting their outputs (OUTP, OUTN) to a supply Voltage (VSUPPLY) and a second voltage (e.g., ground (VGND)), respectively, such that the resulting outputs (OUTP, OUTN) are high-frequency square waves. The driver stage 516 receives the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) from the modulator 504, level shifts them as necessary, and drives the

MOSFETs

524, 526, 528, 530 in the power stage 518.

A low pass LC filter 536, 538 is provided between each

half bridge

518, 520 and the load (speaker) 502, respectively, to recover the amplified audio signal. The low pass LC filters 536, 538, which include an inductor (LFILT) and a Capacitor (CFILT), filter out electromagnetic interference from the output signals (OUTP, OUTN) to prevent high frequency switching energy from dissipating in the resistive load (speaker) 502.

In accordance with the present disclosure, the audio amplifier 500 illustrated in fig. 5 includes an idle mode of operation when there is no input signal or the input signal is very low to reduce power consumption and improve the efficiency of the amplifier 500. During the idle mode, when the voltage of the analog input signal falls below a threshold level such that a common mode component (VCM _ MOD)504 of the input signal, the voltage of which is equal to one-half of the common mode voltage (VREFC/2), is input to the amplifier component, the modulator 502 is configured to shift the common mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) such that the common mode duty cycle is greater than or less than fifty percent (50%). In an embodiment, the threshold voltage is substantially zero volts (0V). The threshold voltage may also be programmable so that it can be set, for example, using the input of the modulator 502.

As shown in fig. 5, an IDLE MODE OFFSET signal (IDLE MODE OFFSET) is provided as an input to the waveform generator 506. The IDLE MODE OFFSET signal (IDLE MODE OFFSET) causes the waveform generator 506 to add (or subtract) a voltage OFFSET to (or from) the voltage of the waveform (triangle wave) input signal (VCM _ TRI) such that the voltage of the triangle wave signal (V _ TRI) increases (or decreases) and is therefore no longer centered on the common MODE voltage (VREFC/2). In other embodiments, the IDLE MODE OFFSET signal (IDLE MODE OFFSET) may cause the amplifier component 504 to add (or subtract) a voltage OFFSET to the voltage of the common MODE component of the input signal (VCM _ MOD) to cause the voltage of the differential first (P) and second (N) modulation signals (MODP, MODN) to increase (or decrease). An increase (or decrease) in either or both of the voltages of the waveform (triangle wave) signal (V _ TRI) and the first (P) and second (N) modulation signals (MODP, MODN) shifts the common mode duty cycle of the first and second quantized signals (BR _ OUTP, BR _ OUTN) output by the respective first and

second comparators

504, 506 in the comparator component 508 such that the common mode duty cycle of these quantized signals (BR _ OUTP, BR _ OUTN) is one of greater than or less than fifty percent (50%). In an embodiment, when the common mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) is shifted by fifty percent (50%), the p-

channel MOSFETs

524, 528 and the n-

channel MOSFETs

526, 530 continue to switch the first output signal (OUTP) and the second output signal (OUTN), respectively, between the supply Voltage (VSUPPLY) and the second voltage (e.g., ground (VGND)). In this way, the power consumed by the load (speaker) 520 is greatly reduced, thereby improving the efficiency of the amplifier 500.

In an embodiment, the idle mode of amplifier 500 may be disabled. For example, in an embodiment, the modulator 502 may be configured such that shifting of the common MODE duty cycle of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) may be selectively disabled by the IDLE MODE OFFSET signal (IDLE MODE OFFSET).

Fig. 6 and 7 illustrate an idle mode implementation of an amplifier, such as amplifier 500 shown in fig. 5, with programmable start-up times in accordance with an embodiment of the present disclosure.

The level of the analog input signal is compared to a threshold level. In the illustrated embodiment, the level of the analog input signal may include a voltage determined as the difference between the voltages of the input signals (INP-INN) of the amplifier 500, which is compared to a threshold voltage. When the level of the analog input signal (INP-INN) is higher than the threshold voltage, the amplifier 500 normally modulates the first modulation signal (MODP) and the second modulation signal (MODN). Therefore, the difference between the first modulation signal (MODP) and the second modulation signal (MODN) causes the output signals (OUTP, OUTN) to have different duty cycles. Therefore, the differential output signal (OUTP-OUTN) includes a pulse wave that varies between the power supply Voltage (VDD) and zero (0). The voltage of the output COMMON MODE (OUT COMMON MODE) is equal to one-half of the supply voltage (VDD/2).

When there is no analog input signal, the modulation signal (MODP, MODN) is equal to the average voltage of the waveform (triangle wave) signal (V _ TRI) in order to cause the level (voltage) of the analog input signal (INP-INN) to fall below the threshold voltage (programmable threshold in fig. 6, programmable threshold LO in fig. 7). The duty cycle of the output signals (OUTP, OUTN) is equal to fifty percent (50%), and the differential output signal (OUTP-OUTN) is equal to zero (0). The voltage of the output COMMON MODE (OUT COMMON MODE) is equal to one-half of the supply voltage (VDD/2). As shown, this state may last for a period of time, referred to herein as a start-up time (programmable start-up time), before entering the idle mode.

After the start-up time (programmable start-up time) has expired, the idle mode is entered, causing the voltage of the modulated signal (MODP, MODN) to increase (or decrease). The voltage of the modulated signal (MODP, MODN) thus shifts (no longer equals) the average voltage of the waveform (triangle wave) signal (V _ TRI). The offset causes the common mode duty cycle of the output signals (OUTP, OUTN) to be shifted away from fifty percent (50%). However, because the output signals (OUTP, OUTN) are shifted by the same amount, the differential output signal (OUTP-OUTN) remains equal to zero (0). The voltage of the output COMMON MODE (OUT COMMON MODE) increases (or decreases) and is no longer equal to half the supply voltage (VDD/2).

In an embodiment, the length of the start-up time (programmable start-up time) may vary depending on the implementation, and may be programmable via an input (not shown) of the amplifier 500.

Fig. 7 further illustrates an implementation of an extended idle period for an amplifier, such as the amplifier shown in fig. 5, in accordance with an embodiment of the present disclosure. As shown, when the level (voltage) of the analog input signal (INP-INN) falls below a first threshold voltage (programmable threshold LO), the modulation signal (MODP, MODN) is equal to the average voltage of the waveform (triangle wave) signal (V _ TRI). The duty cycle of the output signals (OUTP, OUTN) is equal to fifty percent (50%), and the differential output signal (OUTP-OUTN) is equal to zero (0). The voltage of the output COMMON MODE (OUT COMMON MODE) is equal to one-half of the supply voltage (VDD/2). As shown, this state may last for a period of time, referred to herein as a start-up time (programmable start-up time), before entering the idle mode. As described above, after the start-up time (programmable start-up time) has expired, the idle mode is entered, causing the voltage of the modulated signal (MODP, MODN) to increase (or decrease). The voltage of the modulated signal (MODP, MODN) thus shifts (no longer equals) the average voltage of the waveform (triangle wave) signal (V _ TRI). The offset causes the common mode duty cycle of the output signals (OUTP, OUTN) to be shifted away from fifty percent (50%). However, because the output signals (OUTP, OUTN) are shifted by the same amount, the differential output signal (OUTP-OUTN) remains equal to zero (0). The voltage of the output COMMON MODE (OUT COMMON MODE) increases (or decreases) and is no longer equal to half the supply voltage (VDD/2).

In an embodiment, amplifier 500 may continue to operate in the idle mode until the level (voltage) of the analog input signal (INP-INN) increases above a second threshold level (voltage) (programmable threshold HI). Therefore, as shown in fig. 7, even if some analog input signal is present and the differential output signal (OUTP-OUTN) includes a pulse wave varying between the power supply Voltage (VDD) and zero (0), the amplifier can continue to operate in the EXTENDED IDLE MODE (EXTENDED IDLE MODE). However, the voltage of the output COMMON MODE (OUT COMMON MODE) remains increased (or decreased) and is no longer equal to half the supply voltage (VDD/2). When the level (voltage) of the analog input signal (INP-INN) increases above a second threshold level (voltage) (programmable threshold HI), amplifier 500 exits idle mode and returns to normal modulation. This return may be done continuously or in discrete steps so that the shifting of the duty cycle does not cause signal distortion as the amplitude of the audio signal increases. In an embodiment, when the amplifier 500 is in an idle mode (e.g., when the common mode duty cycle of each of the first quantized signal (BR _ OUTP) and the second quantized signal (BR _ OUTN) is shifted by fifty percent (50%), the p-

channel MOSFETs

524, 528 and the n-

channel MOSFETs

526, 530 continue to switch the first output signal (OUTP) and the second output signal (OUTN) between the supply Voltage (VSUPPLY) and the second voltage (e.g., ground (VGND)), respectively.

In an embodiment, the voltage of the output common mode signal may be equal to an average of the common mode duty cycle multiplied by the supply voltage. Thus:

OUT COMMON MODE ═ D1 × VDD + D2 × VDD)/2 where D1 is the duty cycle of the first output signal (OUTP) and D2 is the duty cycle of the second output signal (OUTN). Thus, for example, when the duty cycles are each fifty percent (D1 ═ D2 ═ 0.5), the voltage of the output COMMON MODE signal (OUT COMMON MODE) is equal to one-half of the supply voltage (OUT COMMON MODE ═ 0.5 × VDD), as will occur during the PROGRAMMABLE start-up time (program MODE ATTACK TIME) of fig. 6 and 7. When the duty cycles are all shifted to eighty percent (D1 ═ D2 ═ 0.8), the voltage of the output COMMON MODE signal (OUT COMMON MODE) is equal to eighty percent of the supply voltage (OUT COMMON MODE ═ 0.8 × VDD), as will occur during idle MODE.

When the duty cycle of the first output signal (OUTP) is eighty-two percent (D1 ═ 0.82) and the duty cycle of the second output signal (OUTN) is seventy-eight percent (D1 ═ 0.78), the voltage of the output COMMON MODE signal (OUT COMMON MODE) is equal to eighty percent of the supply voltage (OUT COMMON MODE ═ 0.8 × VDD), even if the differential output signal (OUTP-OUTN) is no longer 0, as would occur during the extended idle MODE (extended idle MODE). It should be understood that the values (0.8, 0.82, 0.78) selected for the duty cycle of the output signals (OUTP, OUTN) are merely examples. Thus, the duty cycle may have other values. Additionally, in the example provided, the duty cycle has undergone a positive shift, i.e., where the COMMON MODE output (OUT COMMON MODE) increases from nominal (VDD/2). However, it should be understood that the duty cycle may also experience a negative shift, i.e., where the output COMMON MODE (OUT COMMON MODE) increases from nominal (VDD/2) and the power usage experiences the same or similar decrease.

In an embodiment, the amount of shift of the duty cycle of the output signals (OUTP, OUTN) may vary depending on the implementation, and the input (not shown) via the amplifier 500 may be programmable. Additionally, in an embodiment, the threshold levels or voltages (programmable threshold in fig. 6, programmable threshold LO and programmable threshold level HI in fig. 7) may be programmable via inputs (not shown) of amplifier 500.

Example method

Fig. 8 illustrates a method 800 for implementing an idle mode in an audio amplifier, such as the

example amplifiers

100, 200, and 500 shown in fig. 1, 2, and 5, respectively, in accordance with the present disclosure. The method 800 allows for a reduction in power consumed by a speaker employing a class D audio amplifier. As shown, method 800 includes receiving an analog audio input signal (block 802). For example, in an embodiment, the analog audio input signal may comprise a first (P) audio input signal (INP) and a second (N) audio input signal (INN). The level of the analog audio input signal may comprise a voltage determined as the difference between the voltages of the input signals (INP-INN). An audio input signal is modulated to provide differential quantized signals (BR _ OUTP, BR _ OUTN) (block 804), each having a common-mode duty cycle. In an embodiment, modulating the analog input signal (INP, INN) to provide the quantized signal (BR _ OUTP, BR _ OUTN) is achieved by providing a differentially modulated signal (MODP, MODN) derived from the analog audio signal (INP, INN). The respective voltages of the modulated signals (MODP, MODN) are proportional to the analog input signal. A waveform signal (e.g., a triangular wave, a sawtooth wave, etc.) having a voltage centered on the common mode voltage is also generated (V _ TRI). The respective modulation signals (MODP, MODN) and waveform signals (V _ TRI) are used to generate quantized signals (BR _ OUTP, BR _ OUTN) using modulation techniques such as Pulse Width Modulation (PWM).

The level of the analog input signal (INP-INN) is compared to a threshold level (block 806). In an embodiment, the threshold voltage is substantially zero volts (0V). The threshold voltage may also be programmable so that it can be set, for example, using the input of the amplifier.

When it is determined that the level of the analog input signal (INP-INN) is above the threshold level (voltage) (no at block 806), modulation of the analog input signal continues to normally generate the output signals (OUTP, OUTN) (block 812). The output signals (OUTP, OUTN) are switched between the power supply voltage and the second voltage based on the differential quantized signal. Therefore, the differential output signal (OUTP-OUTN) includes a pulse wave that varies between the power supply Voltage (VDD) and zero (0).

When the level of the analog audio input signal (INP-INN) is below the threshold level (yes at block 806), a second determination may be made: whether an idle mode of the amplifier is entered (block 810). For example, the amplifier may receive an idle mode offset signal. When the idle mode is not entered, e.g., no idle mode signals are received (e.g., idle mode is disabled), or during the programmable start-up time discussed in the description of fig. 6, output signals (OUTP, OUTN) are generated (block 812) having a duty cycle equal to fifty percent (50%) and a differential output signal (OUTP-OUTN) equal to zero (0). When the idle mode is entered, for example, after expiration of a programmable start-up time, the common-mode duty cycle of each quantized signal is shifted such that the common-mode duty cycle is one of greater than or less than fifty percent (50%) (block 810). Output signals (OUTP, OUTN) are then generated (block 812), the duty cycles of which are shifted by fifty percent (50%) while the differential output signal (OUTP-OUTN) is equal to zero (0). The output signals (OUTP, OUTN) drive the load (speaker) (block 816). In an embodiment, a low-pass filter (e.g., a low-pass LC filter, etc.) may be used to filter out electromagnetic interference from the output signals (OUTP, OUTN).

In an embodiment, when the level (voltage) of the input signal (INP-INN) is lower than the threshold level (voltage), the common mode duty ratio of the quantized signal (BR _ OUTP, BR _ OUTN) and the output signal (OUTP, OUTN) is shifted by increasing or decreasing at least one of the voltage of the modulated signal (MODP, MODN) or the average voltage of the waveform (triangular wave) signal (V _ TRI).

In an embodiment, the digital output signals (OUTP, OUTN) are shifted according to the amplitude of the analog audio signal. For example, when the level (voltage) of the analog input signal (INP-INN) is lower than a threshold level (voltage), the common mode duty cycle of each of the first and second quantized signals (BR _ OUTP) and corresponding output signals (OUTP, OUTN) is shifted until the level of the analog input signal (INP-INN) is higher than a second threshold level (voltage), which is higher than the first threshold level (voltage).

In general, any of the functions described herein can be implemented using hardware (e.g., fixed logic circuitry such as an integrated circuit), software, firmware, manual processing, or a combination thereof. Accordingly, the blocks discussed in the disclosure above generally represent hardware (e.g., fixed logic circuitry such as an integrated circuit), software, firmware, or a combination thereof. In the example of a hardware configuration, the various blocks discussed in the disclosure above may be implemented as an integrated circuit along with other functionality. Such an integrated circuit may include all of the functionality of a given block, system, or circuit, or a portion of the functionality of a block, system, or circuit. Additionally, elements of a block, system, or circuit may be implemented across multiple integrated circuits. Such integrated circuits may include a variety of integrated circuits, including but not necessarily limited to: monolithic integrated circuits, flip-chip integrated circuits, multi-chip module integrated circuits, and/or mixed signal integrated circuits. In the example of a software implementation, the various blocks discussed in the disclosure above represent executable instructions (e.g., program code) that perform specified tasks when executed on a processor. These executable instructions may be stored in one or more tangible computer-readable media. In some such examples, an entire system, block, or circuit may be implemented using its software or firmware equivalents. In other examples, portions of a given system, block, or circuit may be implemented in software or firmware, while other portions are implemented in hardware.

Although the subject matter has been described in language specific to structural features and/or procedural operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An amplifier, comprising:

a modulator configured to receive an analog input signal, the modulator operable to convert the analog input signal into differential first and second quantized signals, each of the first and second quantized signals having a common-mode duty cycle; and

a power stage to receive the first and second quantized signals and generate corresponding first and second output signals configured to drive a load, the first and second output signals being switched between a supply voltage and a second voltage based on the respective first and second quantized signals,

wherein the modulator shifts a common mode duty cycle of each of the first and second quantized signals such that the common mode duty cycle is one of greater than or less than fifty percent (50%) when a level of the analog input signal is below a threshold level, the power stage continuing to switch the first and second output signals between the supply voltage and the second voltage when the common mode duty cycle of each of the first and second quantized signals is shifted.

2. The amplifier of claim 1, wherein the modulator is further configured to receive an idle mode offset, the idle mode offset to cause the modulator to shift duty cycles of the first quantized signal and the second quantized signal.

3. The amplifier of claim 1, wherein the threshold level comprises a threshold voltage.

4. The amplifier of claim 3, wherein the threshold voltage is programmable.

5. The amplifier of claim 1, further comprising a filter for receiving the first output signal and the second output signal from the power stage and filtering out electromagnetic interference.

6. The amplifier of claim 1, wherein the modulator includes a start-up time for shifting the first quantized signal and the second quantized signal, and wherein the start-up time is programmable.

7. The amplifier of claim 1, wherein the modulator is configured such that shifting of the common mode duty cycle of the first and second quantized signals may be selectively disabled.

8. The amplifier of claim 1, wherein the modulator shifts a common mode duty cycle of each of the first quantized signal and the second quantized signal until the analog input signal is above a second threshold level, the second threshold level being higher than the first threshold level.

9. The amplifier of claim 1, wherein the modulator is operable to convert the analog input signal to a quantized signal using Pulse Width Modulation (PWM).

10. A BD modulator for an audio amplifier, the BD modulator comprising:

an amplifier component configured to receive an analog audio signal having a first voltage and to provide a differential first modulated signal and a second modulated signal, the first modulated signal having a second voltage and the second modulated signal having a third voltage;

a waveform generator for generating a waveform signal having a fourth voltage centered on the common mode voltage; and

a comparator component configured for receiving the waveform signal and the first and second modulated signals and for providing respective differential first and second quantized signals, each of the first and second quantized signals having a common-mode duty cycle,

wherein when the first voltage is below a threshold voltage, at least one of the fourth voltage or the second voltage and the third voltage is increased or decreased to shift a common mode duty cycle of the first quantized signal and the second quantized signal such that the common mode duty cycles are one of greater than or less than fifty percent (50%).

11. The BD modulator for an audio amplifier of claim 10, wherein the waveform generator includes a triangle wave generator, and the waveform signal includes a triangle wave.

12. The BD modulator of claim 10, wherein at least one of the amplifier component and the waveform generator is further configured to receive an idle mode offset having an idle mode offset voltage to increase or decrease the second voltage and the third voltage or the fourth voltage.

13. A BD modulator as claimed in claim 10, wherein the threshold voltage is substantially zero volts (0V).

14. A BD modulator as claimed in claim 10, wherein the threshold voltage is programmable.

15. BD modulator of claim 10, wherein the comparator component is operable to generate the first and second quantized signals using Pulse Width Modulation (PWM).

16. A class D audio amplifier comprising:

a BD modulator configured to receive an analog audio signal having a first voltage and an idle-mode offset having an offset voltage, the BD modulator comprising:

an amplifier component operable to provide differential first and second modulated signals derived from the first voltage, the first modulated signal having a second voltage and the second modulated signal having a third voltage;

a triangular wave generator for generating a triangular wave signal having a fourth voltage centered on the common mode voltage;

a comparator component configured for receiving the triangular wave signal and the first and second modulated signals and for providing respective differential first and second quantized signals, each of the first and second quantized signals having a common-mode duty cycle,

wherein when the first voltage is lower than a threshold voltage, the BD modulator increases or decreases the second and third voltages or the fourth voltage to shift common mode duty cycles of the first and second quantized signals such that the common mode duty cycles are one of greater than or less than fifty percent (50%);

a power stage to receive the first and second quantized signals and generate respective first and second output signals that switch between a supply voltage and a fifth voltage based on the first and second quantized signals; and

a low pass LC filter to receive the first and second output signals from the power stage and filter out electromagnetic interference, the first and second output signals configured to drive a speaker.

17. A class D audio amplifier according to claim 16, wherein the threshold voltage comprises a programmable voltage.

18. The class D audio amplifier of claim 16, wherein the BD modulator includes a start-up time for shifting the first quantized signal and the second quantized signal, and wherein the start-up time is programmable.

19. The class D audio amplifier of claim 16, wherein the BD modulator is configured such that shifting of the common mode duty cycle of the first and second quantized signals may be selectively disabled.

20. A class D audio amplifier according to claim 16, wherein the digital output signal is shifted in dependence on the amplitude of the analog audio signal,

wherein when the level of the analog input signal is below the threshold level, the BD modulator shifts the common mode duty cycle of each of the first and second quantized signals until the analog input signal is above a second threshold level, the second threshold level being above the threshold level.