KR100971390B1 - The Circuit for Generating Gamma Reference Voltage - Google Patents

Abstract

The present invention relates to a gamma reference voltage generating circuit in which the number of terminals to which an input voltage is applied is minimized and includes an input terminal for receiving a gamma high voltage and a gamma low voltage from a power supply unit, A positive polarity portion for grouping the plurality of gamma resistors into first and second groups and outputting a voltage divided by the first group of gamma resistors and a positive polarity portion for outputting a voltage divided by the first group of gamma resistors, And a gamma voltage regulating resistor connected between the first group and the second group for regulating a positive voltage and a negative voltage.

Gamma reference voltage, gamma resistance, input voltage

Description

[0001] The present invention relates to a gamma reference voltage generating circuit,

1 is a block diagram showing a general liquid crystal display

Figure 2 is a block diagram illustrating the data driver of Figure 1;

3 is a circuit diagram showing a conventional gamma reference voltage generating circuit

4 is a circuit diagram showing a gamma reference voltage generating circuit according to the first embodiment of the present invention.

5 is a circuit diagram showing a gamma reference voltage generating circuit according to a second embodiment of the present invention

Description of the Related Art [0002]

100: Power supply unit 200: Gamma reference voltage generating circuit

300: decoder

The present invention relates to a liquid crystal display device, and more particularly to a gamma reference voltage generating circuit in which the number of terminals to which an input voltage is applied is minimized.                         

(PDP), Electro Luminescent Display (ELD), Vacuum Fluorescent (VFD), and the like have been developed in recent years in response to the demand for display devices. Display) have been studied, and some of them have already been used as display devices in various devices.

Among them, the LCD is the most widely used in place of a CRT (Cathode Ray Tube) for the purpose of a portable image display device because of its excellent image quality, light weight, thinness and low power consumption, A television monitor for receiving and displaying a broadcast signal, a computer monitor, and the like.

In order to use such a liquid crystal display device as a general screen display device in various parts, it is said that it is important to realize high quality image such as high definition, high brightness, and large area while maintaining characteristics of light weight, thin shape and low power consumption .

A general liquid crystal display device can be broadly divided into a liquid crystal panel for displaying an image and a driving part for applying a driving signal to the liquid crystal panel. The liquid crystal panel includes first and second glass substrates, And a liquid crystal layer injected between the first and second glass substrates.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged at regular intervals and arranged in one direction, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by intersecting gate lines and data lines and a plurality of thin film transistors switched by signals of the gate lines to transmit signals of the data lines to the pixel electrodes .

The second glass substrate (color filter substrate) is provided with a light-shielding layer for shielding light in a portion excluding the pixel region, an R, G, and B color filter layers for expressing color hues, .

The driving principle of the general liquid crystal display device utilizes the optical anisotropy and the polarization property of the liquid crystal. Liquid crystals have a directional arrangement of molecules because the structure is thin and long, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal due to optical anisotropy, so that image information can be expressed.

At present, active matrix liquid crystal displays (LCDs), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, have received the most attention because of their excellent resolution and video realization capability.

Hereinafter, a conventional gamma reference voltage generating circuit will be described with reference to the accompanying drawings.

1 is a block diagram showing a general liquid crystal display device.                         

1, a driving circuit of a general liquid crystal display device includes a liquid crystal panel 21 having a plurality of gate lines G and data lines D arranged in a direction perpendicular to each other and having a pixel region in a matrix form, A driving circuit 22 for supplying a driving signal and a data signal to the panel 21 and a backlight 28 for providing a constant light source to the liquid crystal panel 21.

The driving circuit 22 includes a data driver 21b for inputting a data signal to each data line of the liquid crystal panel 21 and a gate driver for driving each gate line G of the liquid crystal panel 21 The display data R, G, and B, the vertical and horizontal synchronizing signals Vsync and Hsync and the clock signal DCLK input from the driving system 27 of the liquid crystal panel and the control signals DTEN) and formats and outputs each display data, a clock and a control signal at a timing suitable for each of the data driver 21b and the gate driver 21a of the liquid crystal panel 21 to reproduce the screen, A power supply unit 24 for supplying a voltage required for the liquid crystal panel 21 and each unit and a power supply unit 24 for receiving digital data A constant voltage Vdd used in the liquid crystal panel 21 using the voltage output from the power supply unit 24, and a constant voltage Vdd used in the liquid crystal panel 21, A DC / DC converter 26 for outputting a gate high voltage VGH, a gate low voltage VVGL, a reference voltage Vref and a common voltage Vcom; an inverter 29 for driving the backlight 28; Respectively.                         

The operation of the driving circuit unit 22 of the general liquid crystal display device constructed as described above is as follows.

That is, the timing controller 23 generates control signals DTEN such as display data R, G, and B input from the driving system 27 of the liquid crystal panel, vertical and horizontal synchronizing signals Vsync and Hsync, and a clock signal DCLK, The gate drivers 21a and the gate drivers 21a of the liquid crystal panel 21 provide respective display data and clocks and control signals at appropriate timings to reproduce the screen, Applies a gate driving pulse to each gate line G of the liquid crystal panel 21 and the data driver 21b inputs a data signal to each data line D of the liquid crystal panel 21 And displays the input video signal.

2 is a block diagram illustrating the data driver of FIG.

2, a general data driver includes a source start pulse (SSP), a source shift clock (SSC), a left / right select signal (L / R) A first shift register 30 for receiving a load signal from a microcomputer and receiving and storing a video signal RGB data according to an even mode / A decoder (DAC) 33 for converting the digital signals stored in the first and second latch units 31 and 32 into analog signals and outputting each signal of the decoder 33 for each data line And an output buffer (AMP) 34.

At this time, the decoder 33 applies the gamma reference voltage (+) Vref for the (+) field and the gamma reference voltage (-) Vref for the field to the gamma reference voltage unit 25 Receive.

The operation of the data driver will be described in detail as follows.

That is, the RGB data sequentially coming in through the shift register 30 is latched by the microcomputer through the first and second latch units 31 and 32 in accordance with the dot clock, (Line at a Time Scanning).

Then, the data stored in the first latch unit 31 is transferred to the second latch unit 32 in accordance with a transfer enable signal for every horizontal line period.

The data stored in the second latch unit 32 is applied to the gamma reference voltage as an operation power source and is converted into an analog voltage by the decoder 33 in response to a polarity output load (POL) applied from the microcomputer.

And is applied to each data line through an output buffer 34 in accordance with an analog power supply and a control signal applied from the microcomputer.

3 is a circuit diagram showing a conventional gamma reference voltage generating circuit.

As shown in FIG. 3, the conventional gamma reference voltage generating circuit (gamma reference voltage section) is divided into a positive section 25a and a negative section 25b, Each of the reference voltage generating circuits receives the two power supply voltage values from the reference voltage generating circuit 24 and outputs the positive reference voltages and the negative reference voltages to the decoder 33 on the output side thereof.

Here, the first and second power supply voltages (the gamma high voltages VGH63 (V1) and VGH0 (V2)) are applied to the positive electrode portion 25a from the power supply portion 24, (+) Vref1, ((+) Vref1, and (Vref2)) constituting an output terminal between the power supply voltage application terminal and each of the gamma resistors RT1, RT2, +) Vref2, (+) Vref3, (+) Vref4, (+) Vref5.

When the third and fourth power supply voltages (the gamma low voltages VGL0 (V3) and VGL63 (V4)) are supplied from the power supply section 24 to the negative polarity section 25b, (-) Vref1, (-) Vref1 to the decoder 33 by constituting an output stage between the voltage applying stage and each gamma resistor, and the gamma resistors RT5, RT6, RT7, ) Vref2, (-) Vref3, (-) Vref4, (-) Vref5.

The gamma reference voltage generating circuit 25 is applied with four power source voltages V1, V2, V3 and V4 for driving the positive electrode portion 25a and the negative electrode portion 25b, Four pins are required.

The lowest voltage V2 applied to the positive electrode 25a and the third voltage V3 applied to the negative electrode 25b are not connected to each other without being connected to each other.

In the drawing, the power supply voltage is applied with the highest and lowest values of the polarity reference voltages to generate the respective polarity reference voltages. In order to generate the reference voltage therebetween at a desired value, A separate power supply voltage application pin may be further provided to apply the power supply voltage between the gamma resistors. In this case, no gamma resistance is formed in the gamma reference voltage generating circuit 25 corresponding to between the application potentials of the adjacent power source voltages V2 and V3.

The reference voltages outputted through the gamma reference voltage generating circuit 25 are respectively applied to a decoder 33 and used as a reference voltage for converting digital data into analog signals according to the gradation.

However, the conventional gamma reference voltage generating circuit has the following problems.

The gamma reference voltage generating circuit requires at least two power supply voltages to output a reference voltage for each polarity portion on the input side thereof in order to output the reference voltages for the positive and negative polarity portions. At least four pins were required. This causes problems of power consumption increase and cost increase.

It is an object of the present invention to provide a gamma reference voltage generating circuit that minimizes the number of terminals to which an input voltage is applied.

According to an aspect of the present invention, there is provided a gamma reference voltage generating circuit including an input terminal for receiving a gamma high voltage and a gamma low voltage from a power supply unit, a plurality of gamma resistors connected in series between the input terminal and dividing an input voltage, A positive polarity portion for grouping the plurality of gamma resistors into first and second groups and outputting a voltage divided by the first group of gamma resistors and a voltage divider for outputting a voltage divided by the second group of gamma resistors to an output And a gamma voltage regulating resistor connected between the first group and the second group for regulating a positive voltage and a negative voltage.

The first group is adjacent to an input to which the gamma high voltage is applied and the second group is adjacent to the input end to which the gamma low voltage is applied.

The positive polarity portion further includes an output terminal connected to the input terminal of the gamma high voltage, between the first group of gamma resistors, and to the connection portion of the first group and the gamma voltage regulating resistor.

The output stage outputs positive reference voltages.

The output terminal is connected to the decoder of the data driver.

The negative polarity portion further includes an output terminal at an input terminal of the gamma voltage, an output terminal between the second group of gamma resistors, and a connection portion between the second group and the gamma voltage regulating resistor.

The output stage outputs negative reference voltages.

The output terminal is connected to the decoder of the data driver.

In order to achieve the same object, the gamma reference voltage generating circuit of the present invention includes an input terminal and a ground terminal for receiving a gamma high voltage from a power supply unit, and a plurality of gamma -controllers connected in series between the input terminal and the ground terminal, And a plurality of gamma resistors are grouped into a first group and a second group to output a voltage divided by the first group of gamma resistors and a voltage divider unit for outputting a voltage divided by the second group of gamma resistors to an output A first gamma voltage regulating resistor connected between the first group and the second group for regulating a positive voltage and a negative voltage, and a second gamma voltage regulating resistor connected between the ground and the second group, And a second gamma voltage regulating resistor for regulating the negative voltage.

The first group is adjacent to an input to which the gamma high voltage is applied, and the second group is adjacent to the ground terminal.

The positive polarity portion further includes an output terminal at the input terminal, an output terminal between the first group of gamma resistors, and a connection portion between the first group and the gamma voltage regulating resistor.

The output stage outputs positive reference voltages.

The output terminal is connected to the decoder of the data driver.

The negative polarity portion has an output terminal at each of the ground terminal, the second group of gamma resistors, and the connection between the second group and the gamma voltage regulating resistor.

The output stage outputs negative reference voltages.

The output terminal is connected to the decoder of the data driver.

Hereinafter, the gamma reference voltage generating circuit of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram showing a gamma reference voltage generating circuit according to the first embodiment of the present invention.

4, the gamma reference voltage generating circuit 200 according to the first embodiment of the present invention includes an input terminal VGH63 for receiving the gamma high voltage V1 and the gamma low voltage V4 from the power supply unit 100, A plurality of gamma resistors R1, R2, R3, R4, R5, R6, R7, and R8 connected in series between the input terminals VGH63 and VGL63 for dividing an input voltage, (R1, R2) of the input terminal (VGH63) to which the gamma high voltage (V1) is inputted by grouping the first gamma resistance (R1, R2, R3, R4, R5, R6, R7, R8) A positive polarity portion 200a for outputting a voltage divided by the first group gamma resistor R3, R4 to the decoder 300 and a second group gamma resistor R5, R6 for the input terminal VGL63 to which the gamma low voltage V4 is inputted, R6, R7 and R8 to the decoder 300 and a negative polarity part 200b connected in series between the gamma resistors R4 and F5 between the first group and the second group Further included is a gamma voltage controlled resistance (R9) for controlling the polarity voltage and negative polarity voltage.

Therefore, the reference voltages (+) Vref1, (+) Vref2, (+) Vref3, (+) Vref4, and Vref4 are output from the output terminals of the positive polarity portion 200a and the negative polarity portion 200b to the decoder 300 of the data driver. (+) Vref5, (-) Vref1, (-) Vref2, (-) Vref3, (-) Vref4, (-) Vref5.

The output terminal of the positive polarity portion outputs positive reference voltages (+ Vref), and the output terminal of the negative polarity portion outputs negative reference voltages (- (-) Vref).

(+) Vref1, (+) Vref2, (+) Vref3, (+) Vref4, (+) Vref5, (-) Vref1, (-) Vref2, (-) Vref3, (-) Vref4, (-) Vref5) are calculated as follows.

Here, the total resistance value of all the resistors (R1 to R9) connected in series between the input terminals (VGH63 and VGL63) is denoted by R _T.

The reference voltage values output from the output terminals are divided into a positive electrode portion 200a and a negative electrode portion 200b, respectively.

First, the positive electrode part (200a) is in turn to each of the output terminals V1, {(V1-V4) × (R T -R1) / R T} + V4, {(V1-V4) × (R T - (R1 + _{R2)) / R T} +} V4, {(V1-V4) × (R T - (R1 + R2 + R3)) / R T} + V4, {(V1-V4) × (R T - (R1 + (+) Vref1, (+) Vref2, (+) Vref3, (+) Vref4, (+) Vref5 having a value of R2 + R3 + R4) / R _T } + V4.

The negative polarity portion 200b is connected to each output terminal in order of {(V1 - V4) (R5 + R6 + R7 + R8) / R _T } + V4, {(V1 - V4) _{R T} + V4, {(} V1-V4) × (R7 + R8) / R T} + V4, {(V1-V4) × R8 / R T} + V4, the reference voltage ((having the value of V4 - (-) Vref1, (-) Vref2, (-) Vref3, (-) Vref4, (-) Vref5.

The gamma reference voltage generating circuit of the present invention includes an output terminal for outputting the lowest reference voltage (+) Vref5 of the positive polarity portion 200a and an output terminal for outputting the highest reference voltage (- (-) Vref1) of the negative polarity portion 200b And the positive electrode unit 200a and the negative electrode unit 200b are connected in series through the resistor R9 so that the positive electrode unit 200a and the negative electrode unit 200b are connected in series, It is not necessary to separately apply power to each of the positive and negative electrodes 200a and 200b and the power source voltages V1 and V4 are simultaneously applied to the positive and negative electrodes 200a and 200b. Therefore, the input terminal can be reduced as compared with the conventional case, and the power consumption can be reduced and the circuit can be simplified.

(+) Vref1, (+) Vref2, (+) Vref3, (+) Vref4, (+) Vref5, (-) Vref1, (-) output from the gamma reference voltage generating circuit (200) Vref2, (-) Vref3, (-) Vref4, (-) Vref5 are applied to the decoder 33 for each polarity to convert the digital data into analog signals according to the gradation.

(+) Vref1, (+) Vref2, (+) Vref3, (+) Vref4, (+) Vref5 from the top to the bottom (-) Vref1, (-) Vref2, (-) Vref3, (-) Vref4, (-) Vref5 which output the reference voltage of the corresponding level of black to white or white to black, ) Outputs a reference voltage of a corresponding level from white to black and from black to white symmetrically with the positive polarity reference voltage at the polarity.

5 is a circuit diagram showing a gamma reference voltage generating circuit according to a second embodiment of the present invention.

5, in the gamma reference voltage generating circuit of the first embodiment of the present invention, the input stage is reduced to one, and a gamma high voltage (VGH63 (V1)) is applied to the input stage, The gamma resistors R1 to R9 are connected in series between the input terminal VGH63 and the ground terminal as in the first embodiment of the present invention, And another gamma resistor (R10) is further provided on the ground side.

5, the gamma reference voltage generating circuit according to the second embodiment of the present invention includes an input terminal VGH63 for receiving the gamma high voltage V1 from the power supply unit 100, A plurality of gamma resistors R1, R2, R3, R4, R5, R6, R7, R8 connected in series between the input terminal VGH63 and the ground terminal to divide the input voltage, (R1, R2, R3, R4) at the input terminal (VGH63) to which the gamma high voltage (V1) is inputted by grouping the first gamma resistor (R3, R4, R5, R6, R7, R8) A positive polarity portion 200a for outputting a voltage divided by the first group gamma resistor R5, R6, R7 and R8 to the decoder 300; A negative polarity part 200b for outputting the positive voltage and the negative voltage in series between the first group and the second group and the gamma resistances R4 and F5 between the first group and the second group, Further included is a first gamma voltage regulation resistor (R9) and a second gamma voltage regulation for regulating the negative voltage are series-connected between the second group and the ground terminal resistor (R10) to group.

The output terminal of the positive polarity portion 200a outputs a positive polarity reference voltage, and the output terminal of the negative polarity portion 200b outputs a negative polarity reference voltage. The reference voltages of the corresponding polarities are applied to the decoder 300 of the data driver.

In the gamma reference voltage generating circuit according to the second embodiment of the present invention, only one power supply voltage is applied from the power supply unit 100, so that the input terminal can be further reduced in comparison with the first embodiment, .

The gamma reference voltage of the present invention as in the first and second embodiments described above can be connected in series with more gamma resistance to each group in order to increase the number of reference voltage values outputted from the positive portion and the negative portion.

The plurality of gamma resistors may be formed identically or differently to output a predetermined level to a desired reference voltage value.

The first and second gamma reference voltage regulating resistors R9 and R10 may be either a resistor having a fixed resistance value or a variable resistor having a variable resistance value.

The gamma reference voltage generating circuit may output a stable reference voltage without noise by connecting a buffer to each of the gamma resistors and each output terminal in addition to a plurality of the gamma resistors connected in series as shown in the figure.

The reference voltages output through the gamma reference voltage generating circuit are applied to the decoders of the data drivers, and the decoders generate R, G, and B signals using the polarity gamma reference voltages (+ Vref, (-) Vref) Converts the digital video signal into an analog video signal and outputs a driving voltage, and the output driving voltage is applied to the data line of the liquid crystal panel every scanning.

The gamma reference voltage generating circuit of the present invention as described above has the following effects.

First, by further connecting a resistor in series between the positive electrode portion and the negative electrode portion, the power voltage input terminal can be reduced, thereby reducing power consumption and simplifying the circuit.                     

Second, a reference voltage can be generated even if only one predetermined power supply voltage is applied by taking a structure in which the power supply voltage applied to the lowest point of the gamma resistance is grounded rather than a separate power supply unit.

Claims (16)

delete delete delete delete delete delete delete delete An input terminal and a ground terminal for receiving a gamma high voltage from the power supply unit; A positive polarity portion which is in contact with the input terminal and has a plurality of first group gamma resistors connected in series and outputs a plurality of positive polarity voltages divided; A negative pole portion adjacent to the ground terminal and having a plurality of series connected second group gamma resistors to output a plurality of divided negative voltages; A first gamma voltage regulating resistor connected between the positive electrode and the negative electrode to control a difference between a positive minimum voltage and a negative maximum voltage; And And a second gamma voltage regulating resistor connected between the ground and the negative electrode to regulate the negative voltage of the negative polarity. delete 10. The method of claim 9, The positive polarity portion is connected between the first group of gamma resistors and the connecting portion between the upper end of the first group of gamma resistors and the input end and the lowest end of the first group of gamma resistors and the connecting portion of the first gamma voltage regulating resistor Further comprising a positive polarity reference output terminal, The negative polarity portion has a negative polarity reference voltage output terminal at the connection between the second group of gamma resistors, a top end of the second group gamma resistor, a bottom end of the second group gamma resistor, The gamma reference voltage generating circuit further comprising: delete 12. The method of claim 11, Wherein the positive polarity reference voltage output terminal and the negative polarity reference voltage output terminal are connected to a decoder of a data driver. delete delete delete

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