KR100967200B1 - Trench DMOS Transistor and Method for the Same - Google Patents

Abstract

The present invention provides a method of forming a well having a predetermined depth in a semiconductor substrate, forming a field oxide film in the semiconductor substrate, and performing a first trench etching process on a semiconductor substrate in a region where a gate is to be formed. Forming a trench, performing a second trench etching process on the semiconductor substrate on which the trench is formed, so that an upper end of the trench has an inclination of 82 to 87 °, and forming a gate oxide film on an inner wall of the trench And filling the trench with a conductive material to form a gate electrode, and implanting impurity ions into both sides of the trench to form a source, thereby increasing the channel length by the top slope of the trench. A trench DMOS transistor capable of forming a gate oxide film having a uniform thickness and a method of manufacturing the same are provided.

Trench, Tilt, Channel, Gate Oxide

Description

Trench DMOS transistor and its manufacturing method {Trench DMOS Transistor and Method for the Same}             

1A to 1D are flowcharts illustrating a method of manufacturing a trench DMOS transistor according to the prior art.

FIG. 2 is a SEM photograph of a trench DMOS transistor having a vertical structure formed by the prior art. FIG.

3A to 3D are flowcharts illustrating a method of manufacturing a trench DMOS transistor according to the present invention.

4 is an SEM photograph of a trench DMOS transistor formed by the present invention.

   -Explanation of symbols for the main parts of the drawings-

200: semiconductor substrate 201: N-type epitaxial layer

202 p-well 203 nitride film

204 HLD oxide film 205 Gate oxide film

206: gate electrode 207: source

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage device and a method of manufacturing the same, and more particularly, to form a trench having a predetermined slope on the upper side thereof, to increase the channel length and to form a gate oxide film having a uniform thickness. A transistor and a method of manufacturing the same.

In general, when an external system using a high voltage is controlled by an integrated circuit, an integrated circuit needs an element for high voltage control therein, and such a device needs a structure having a high breakdown voltage.

That is, in a drain or source of a transistor to which a high voltage is integrated, a punch-through voltage between the drain and the source and the semiconductor substrate, and a breakdown voltage between the drain and the source and the well or the substrate It must be greater than this high voltage.

In general, as a high voltage semiconductor device, a DMOS including a PN diode is used. This increases the punch-through voltage and breakdown voltage of the transistor by forming the drain region as a double impurity diffusion region, and forms a PN diode between the source and drain regions to turn off the transistor. It is possible to prevent the device from being destroyed by excessive voltage.

However, in the case of the high voltage device having a vertical structure among the conventional DMOS transistors, the channel length of the linear structure is formed by the trench, so that only the junction operates with the breakdown voltage.

The problem of the trench type DMOS transistor according to the prior art will be described in detail with reference to the drawings exemplified below.

1A to 1D are flowcharts illustrating a method of manufacturing a trench type DMOS transistor according to the prior art.

Referring to FIG. 1A, after the n-type epitaxial layer 101 is formed on a n-type semiconductor substrate 100 on which a common drain (not shown) is formed using a conventional epitaxial growth method, the semiconductor substrate 101 is formed. P-type impurity ion implantation is performed on the entire surface to form a p-well 102 having a predetermined depth. A sacrificial oxidation process is performed after forming a field oxide film (not shown) for isolation between devices.

Thereafter, after implanting channel ions for controlling the threshold voltage V _th , an annealing process is performed to form a channel region (not shown).

Referring to FIG. 1B, a trench A is formed by sequentially depositing a nitride film 103 and an HLD oxide film 104, forming a predetermined photoresist pattern, and then performing a conventional trench etching process using the same. . At this time, since the trench forms a vertical structure, the channel is also formed in a vertical structure, so that only the junction operates as a breakdown voltage.

Referring to FIG. 1C, a gate oxide layer 105 is formed on an inner wall of the trench, a doped polysilicon layer is deposited, an etch back process is performed, and a photo and etching process is performed to form the gate electrode 106. At this time, since the trench has a vertical structure, when the gate oxide film 105 is formed, the supply of O 2 is not smooth and the thickness of the gate oxide film becomes uneven, which causes a low breakdown voltage.

Referring to FIG. 1D, a source 107 is formed by ion implantation of a high concentration of N-type impurities, and the subsequent interlayer insulating film and metal wiring process proceed in the same manner as in the conventional process.

2 is an SEM image of a trench DMOS transistor having a vertical structure according to the prior art, and it can be seen that the channel length is short because the trench does not have a slope.

As described above, according to the method of manufacturing a trench DMOS transistor according to the related art, the channel length of the linear structure is formed by the vertical trench, so that only the junction operates as a breakdown voltage, and a gate oxide film is formed on the inner wall of the trench. When forming, the O2 supply is not made smoothly, resulting in a problem that the breakdown voltage is lowered because the thickness of the gate oxide film is not uniformly formed.

In addition, due to the vertical structure, nodules are generated in the gate oxide layer inside the trench, and there is a problem that only the thickness of the polysilicon needs to be dependent.

The present invention for solving the above problems is to provide a trench DMOS transistor and a method of manufacturing the same to increase the channel length as well as to form a gate oxide film of a uniform thickness.

The present invention for achieving the above object is a trench formed in a P-well region formed in the active region of the semiconductor substrate, a predetermined depth in the P-well region, the top of which has a slope of 82 ~ 87 °, Provided is a trench DMOS transistor comprising a gate insulating film formed on an inner wall, a gate electrode formed to fill a trench, and a source formed inside the P-well region and formed on both sides of the trench on which the gate oxide film is formed. .

The present invention for achieving the above object is to form a well having a predetermined depth in the semiconductor substrate, to form a field oxide film on the semiconductor substrate, the first trench etching for the semiconductor substrate of the region where the gate is to be formed Forming a trench having a predetermined depth by performing a process; and performing a second trench etching process on the semiconductor substrate on which the trench is formed, so that the upper end of the trench has an inclination of 82 to 87 °; Forming a gate oxide film on the inner wall, embedding the trench with a conductive material to form a gate electrode, and implanting impurity ions into both sides of the upper side of the trench to form a source; A method of manufacturing a transistor is provided.

It is preferable to form the slope of the second trench only on the upper side.

The first trench etching process may be performed using CF ₄ gas for 10 seconds using a gas amount of 30 sccm under a pressure of 40 mT and an energy of 200 W. FIG.

The second trench etching process is performed using a plasma composed of CF ₄ , HBr, and HeO ₂ , but preferably, the secondary trench etching process is performed at a ratio of CF ₄ : HBr: HeO ₂ = 10: 23: 19 for 180 seconds.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same symbols and names.

3A to 3D are flowcharts illustrating a method of manufacturing a trench DMOS transistor according to the present invention.

Referring to FIG. 3A, an N-type epitaxial layer 201 is formed on an n-type semiconductor substrate 200 using a conventional epitaxial growth method. P-type impurity ion implantation is performed on the entire surface of the semiconductor substrate 200 to form a P-well 202 having a predetermined depth. A sacrificial oxidation process is performed after forming a field oxide film (not shown) for isolation between devices.

Thereafter, after implanting channel ions for controlling the threshold voltage V _th , an annealing process is performed to form a channel region (not shown).

Referring to FIG. 3B, a nitride film 203 and an HLD oxide film 204 are sequentially deposited to define a region where a trench is to be formed, and then a predetermined photoresist pattern (not shown) is formed. The first trench A is formed by performing a first trench etching process using the photoresist pattern as a mask. The first trench etching process is preferably performed for 10 seconds by supplying 30 sccm of CF ₄ gas under a pressure of 40mT and an energy of 200W.

Referring to FIG. 3C, a second trench is etched on the resultant in which the first trench is formed to form a second trench to have an inclination of 82 to 87 °. In this case, the second trench etching process is carried out under a pressure of 100mT and an energy of 450W, it is preferably carried out for 180 seconds using a plasma consisting of a combination of CF ₄ gas, HBr and HeO ₂ gas. In this case, the gas is preferably combined with CF ₄ : HBr: HeO ₂ = 10: 23: 19 sccm.

Since the upper portion of the trench has an inclination of 82 to 87 °, the channel has an inclination of 13 to 18 °, thereby increasing the channel length, thereby increasing the threshold voltage and the breakdown voltage. In addition, since the upper portion of the trench is enlarged, O ₂ is smoothly supplied when forming the gate oxide layer, and thus a gate oxide layer having a uniform thickness may be formed in the lower portion of the trench.

Referring to FIG. 3D, after the gate oxide layer 205 is formed on the inner wall of the second trench, the doped polysilicon is deposited, an etch back process is performed, and a photo and etching process is performed to perform the gate electrode (in the second trench). 206).

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After the gate electrode is formed, a high concentration of N-type impurity ions are implanted to form a source 207, and subsequent interlayer insulating film and metal wiring processes are performed in the same manner as in the conventional process.

FIG. 4 is a SEM photograph of a trench DMOS transistor formed by the present invention. As shown here, the trench is formed such that its upper side has a predetermined slope.

As described above, according to the present invention, when the trench is formed in the well, the trench may be formed to have a predetermined slope by performing an additional etching process after the trench etching process having a predetermined depth is performed as the main etching process. As a result, the channel length can be expanded and a gate oxide film having a uniform thickness can be obtained.

As described above, the present invention has an advantage of improving device driving capability by increasing breakdown voltage and threshold voltage by increasing the channel length by the slope of the vertical trench.

In addition, by forming a wide upper portion of the trench so that O ₂ is smoothly supplied to the lower portion of the trench when forming the gate oxide layer, a gate oxide layer having a uniform thickness is formed to improve the characteristics of the device to improve the yield.

Claims (10)

A P-well region formed in the active region of the semiconductor substrate; A trench formed to a predetermined depth in the P-well region, the trench having a slope of 82 ° to 87 °; A gate insulating film formed on an inner wall of the trench; A gate electrode formed to fill the trench; And And a source formed in the P-well region and formed on both sides of the upper side of the trench where the gate oxide layer is formed. The trench DMOS transistor of claim 1, wherein the trench has a slope only on an upper side thereof. delete Forming a well having a predetermined depth in the semiconductor substrate; Forming a field oxide film on the semiconductor substrate; Forming a trench having a predetermined depth in the semiconductor substrate in a region where a gate is to be formed; Performing an etching process on the trench-formed semiconductor substrate so that the top of the trench has an inclination of 82 ° to 87 °; Forming a gate oxide film on an inner wall of the trench; Filling the trench with a conductive material to form a gate electrode; And And forming a source by implanting impurity ions into both sides of the upper side of the trench. The method of claim 4, wherein the slope of the trench is generated only at an upper side thereof. delete The method of claim 4, wherein the forming of the trench comprises: A method of manufacturing a trench DMOS transistor, which is performed using CF ₄ gas. The method of claim 7, wherein forming the trench, A method for manufacturing a trench DMOS transistor, characterized in that it is carried out for 10 seconds under a pressure of 40 mT and an energy of 200 W using a gas amount of 30 sccm. The method of claim 4, wherein the upper end of the trench has a slope of 82 ° to 87 °. A method of manufacturing a trench DMOS transistor, characterized in that it is carried out using a plasma composed of CF ₄ , HBr, and HeO ₂ . The method of claim 9, wherein the step of making the upper end of the trench have an inclination of 82 to 87 °, characterized in that the gas combination is performed for 180 seconds at a ratio of CF ₄ : HBr: HeO ₂ = 10: 23: 19. Method of manufacturing a trench DMOS transistor.

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