KR100192596B1 - Buried type transistor and manufacturing method thereof - Google Patents
Buried type transistor and manufacturing method thereof Download PDFInfo
- Publication number
- KR100192596B1 KR100192596B1 KR1019960053514A KR19960053514A KR100192596B1 KR 100192596 B1 KR100192596 B1 KR 100192596B1 KR 1019960053514 A KR1019960053514 A KR 1019960053514A KR 19960053514 A KR19960053514 A KR 19960053514A KR 100192596 B1 KR100192596 B1 KR 100192596B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating layer
- buried
- layer
- transistor
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000003989 dielectric material Substances 0.000 claims abstract description 5
- 239000007943 implant Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract 5
- 230000000873 masking effect Effects 0.000 claims abstract 4
- 238000009792 diffusion process Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 24
- 150000004767 nitrides Chemical class 0.000 description 17
- 108091006146 Channels Proteins 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229940090044 injection Drugs 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 고집적화를 위한 매몰형 트랜지스터 및 그 제조방법에 관한 것으로, 매몰형 트랜지스터의 제조방법은 제1도전형의 반도체 기판상에 제1절연층을 얇게 성장시키는 단계와; 상기 제1절연층상에 제2절연층을 적층하는 단계와; 상기 사진 및 식각공정에 의해 상기 제2절연층을 패터닝하는 단계와; 상기 열산화에 의해 상기 제1절연층과 동일 물질의 제3절연층을 형성하는 단계와; 상기 제2절연층을 마스크화하여 제1절연층 및 제3절연층을 이방성 식각하는 단계와; 결과물 전면에 제4절연층을 형성하는 단계와; 상기 제2절연층과 제4절연층을 순차적으로 식각하여, 상기 마스크화한 제2절연층에 의해 식각되지 않은 제3절연층의 프로파일을 형성하는 단계와; 상기 제3절연층의 프로파일을 마스크화하여 소오스와 드레인 형성을 위한 고농도 엔형 불순물을 이온주입하는 단계와; 결과물 전면에 걸쳐 게이트 유전물질층을 형성하는 단계와; 상기 게이트 유전물질층상에 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a buried transistor for high integration and a method of manufacturing the buried transistor, the method of manufacturing a buried transistor comprising the steps of growing a thin first insulating layer on a semiconductor substrate of the first conductive type; Stacking a second insulating layer on the first insulating layer; Patterning the second insulating layer by the photo and etching process; Forming a third insulating layer of the same material as the first insulating layer by the thermal oxidation; Anisotropically etching the first insulating layer and the third insulating layer by masking the second insulating layer; Forming a fourth insulating layer on the entire surface of the resultant material; Sequentially etching the second insulating layer and the fourth insulating layer to form a profile of the third insulating layer not etched by the masked second insulating layer; Masking the profile of the third insulating layer to ion implant a high concentration of en-type impurities to form a source and a drain; Forming a gate dielectric layer over the entire surface of the resultant; And forming a gate electrode on the gate dielectric material layer.
Description
본 발명은 반도체 메모리 장치에 관한 것으로, 특히 고집적화를 위한 매몰형 트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a buried transistor for high integration and a method of manufacturing the same.
일반적으로, 매몰형 트랜지스터란 통상의 트랜지스터가 게이트 패터닝후 상기 게이트에 셀프 얼라인(Self alignment) 이온주입에 의해 소오스/드레인을 형성하는 것에 반해 게이트 패터닝전에 소오스/드레인을 형성하며, 이후 게이트 형성에 의해 게이트는 소오스/드레인 생성영역의 상부에 일정부분 덮히게 되는데, 여기서 매몰형(Buried)란 이를 뜻한다.Generally, a buried transistor forms a source / drain before gate patterning, whereas a conventional transistor forms a source / drain by self alignment ion implantation into the gate after gate patterning. As a result, the gate is partially covered with an upper portion of the source / drain generation region, which means buried.
도 1a 내지 도 1d는 종래기술의 실시예에 따라 구현되는 매몰형 트랜지스터의 제조방법을 보여주는 공정단면도들로서, 여러가지 종래기술들중 폴리 버퍼드 국부산화공정(Poly Buffered LOCOS)을 예로 들어 설명할 것이다.1A to 1D are process cross-sectional views illustrating a method of manufacturing a buried transistor implemented according to an exemplary embodiment of the prior art, and will be described using poly buffered LOCOS as an example.
도 1a를 참조하면, 소자활성영역과 소자분리영역을 정의하는 국부산화공정을 하기 위한 것으로, 피형 불순물이 도핑된 반도체 기판(101)상에 100500의 박막의 패드 산화막(102A)과 5002000의 비정질 폴리실리콘층(102)과 100010000의 질화막(103)을 침적한후, 포토 레지스트(104)를 통해 식각된 상기 질화막(103)이 도시되어 있다.Referring to FIG. 1A, a local oxidation process for defining an element active region and an isolation region is performed on a semiconductor substrate 101 doped with an impurity. 500 Thin film pad oxide film 102A and 500 2000 Of amorphous polysilicon layer 102 and 1000 10000 After depositing the nitride film 103, the nitride film 103 etched through the photoresist 104 is shown.
도 1b를 참조하면, 필드 산화공정에 의해 상기 질화막(103)이 덮힌 곳에서는 옥사이드의 성장이 억제되고, 상기 질화막(103)이 없는 곳에서는 옥사이드(105)가 성장됨으로써 상기 활성공정은 완료하게 된다. 이러한 결과물 전면에 소자 분리막인 옥사이드(105)의 특성을 강화하기 위하여 기판의 불순물과 같은 도전형의 불순물을 이온주입하여 채널스톱층(106)을 형성한다. 이러한 이온주입은 고에너지로 이온주입하게 되며, 이를 통상적으로 엔형 채널 필드 이온주입이라 칭한다. 필드 옥사이드(105)의 두께에 따라 필드 옥사이드(105) 하부의 근접부위에 최대 피크(Peak)를 형성하며, 활성영역에서는 도시되지 않았지만 Rp만큼 깊게 투과되어 채널형성영역인 0"0.25㎛ 깊이에서는 상기 채널스톱층(106)에 의한 소자특성이 크게 영향 받지 않게 된다. 이렇게 필드 옥사이드(105)와 활성영역을 동시에 실시하는 엔형 채널 필드 이온주입을 LIF(Local Ion implantation after Field oxidation)공정이라 칭하며 일반적으로 통용되는 공정이다.Referring to FIG. 1B, the growth of oxide is suppressed where the nitride film 103 is covered by the field oxidation process, and the oxide 105 is grown where the nitride film 103 is absent, thereby completing the active process. . The channel stop layer 106 is formed by ion implanting a conductive type impurity such as an impurity of a substrate in order to enhance the characteristics of the oxide 105 as a device isolation layer on the entire surface of the resultant. Such ion implantation is ion implanted at high energy, which is commonly referred to as en-channel channel field ion implantation. According to the thickness of the field oxide 105, a maximum peak is formed in the vicinity of the lower portion of the field oxide 105, and although not shown in the active region, it is transmitted as deep as Rp, so that the depth of the channel oxide region is 0 " 0.25 mu m. The device characteristics by the channel stop layer 106 are not significantly affected. The N-type channel field ion implantation which simultaneously performs the field oxide 105 and the active region is called a LIF (Local Ion implantation after Field oxidation) process. It is a commonly used process.
도 1c를 참조하면, 사진공정(Photolithography)에 의해 매몰형 트랜지스터가 형성되는 영역만을 오픈(Open)하고 나머지 영역에는 포토레지스트(107)가 형성된 상태에서 상기 매몰형 트랜지스터의 소오스/드레인 형성을 위한 고농도 도우즈 주입(High dose implant)을 상기 소자분리공정에서 형성된 필드 옥사이드(105)에 의해 셀프얼라인(Self-align) 이온주입한 도면이다.Referring to FIG. 1C, only a region in which a buried transistor is formed by photolithography is opened and a photoresist 107 is formed in the remaining region, and a high concentration for source / drain formation of the buried transistor is formed. Dose implantation (High dose implant) is a self-aligned (Self-align) ion implantation by the field oxide 105 formed in the device isolation process.
도 1d를 참조하면, 상기 매몰형 트랜지스터의 소자분리공정시 형성되었던 상기 필드 옥사이드(105)를 전면 식각하여 상기 필드 옥사이드(105)가 제거된 영역의 표면 하단을 매몰형 트랜지스터의 채널로 이용하기 위한 문턱전압 Vth 조정 주입(Implant)와 게이트 유전물질층(109)을 형성하며, 이어 게이트 전극층(110)을 형성한다. 이후 층간절연막, 콘택형성, 금속화(Metalization) 및 보호막형성등의 일반적인 후속공정을 통하여 완료되게 된다. 이러한 종래기술은 디자인 루울이 타이트한 필드산화막형성시 매몰형 트랜지스터의 소오스/드레인을 함께 결정함으로써 마스크단계는 감소하지 않지만 2개의 주요한(Critical) 단계인 활성영역정의 단계와 BN+ 이온주입단계를 1개의 주요단계와 1개의 비주요단계로 변경함에 따라 생산성 및 공정 마진이 증대되고, 필드 산화막 하부의 경사면을 따라 채널을 형성함으로 동일한 포토 레지스트 마스크공정 대비 펀치쓰루(Punch-Through)에 대한 마진(Margin)이 증가한다. 통상 포토 레지스트 마스크시 BN+ 이온주입될 영역의 포토 레지스트가 오픈됨에 따라 사진공정의 한계에 따른 패턴능력을 확보하기 위해 오픈영역을 포토 레지스트가 덮힌 영역보다 크게할 수 밖에 없음에 따라 펀치 마진을 확보할 수 없게 된다.Referring to FIG. 1D, the front surface of the field oxide 105 formed during the device isolation process of the buried transistor is etched to use the lower surface of the region where the field oxide 105 is removed as a channel of the buried transistor. The threshold voltage Vth adjustment implant (Implant) and the gate dielectric material layer 109 are formed, followed by the gate electrode layer 110. After that, it is completed through a general subsequent process such as interlayer insulating film, contact formation, metallization, and protective film formation. In the prior art, the design phase determines the source / drain of the buried transistor in the formation of a tight field oxide film, so that the mask step is not reduced, but the two critical steps, the active region definition step and the BN + ion implantation step, are used as one main factor. Productivity and process margins increase with each step and one non-major step, forming channels along the slopes below the field oxide and margins for punch-through compared to the same photoresist mask process. Increases. In general, when photoresist masks open the photoresist in the area to be implanted with BN + ion, punch margins can be secured as the open area must be larger than the area covered with the photoresist in order to secure pattern capability according to the limitation of the photo process. It becomes impossible.
본 발명의 목적은 고집적화할 수 있는 매몰형 트랜지스터 및 그 제조방법을 제공함에 있다.An object of the present invention is to provide a buried transistor that can be highly integrated and a method of manufacturing the same.
본 발명의 다른 목적은 공정조절이 용이한 적층두께나 산화조건에 의해 채널의 길이를 조절할 수 있는 매몰형 트랜지스터 및 그 제조방법을 제공함에 있다.Another object of the present invention is to provide a buried transistor and a method for manufacturing the same, which can control the length of a channel by stacking thickness or oxidation conditions, which are easy to control.
본 발명의 또 다른 목적은 펀치쓰루에 대한 공정마진을 확보하면서도 고집적화할 수 있는 매몰형 트랜지스터 및 그 제조방법을 제공함에 있다.Still another object of the present invention is to provide a buried transistor and a method of manufacturing the same, which can be highly integrated while securing a process margin for punch-through.
도 1a 내지 도 1d는 종래기술의 실시예에 따라 구현되는 매몰형 트랜지스터의 제조방법을 보여주는 순차적인 단면도들.1A to 1D are sequential cross-sectional views showing a method of manufacturing a buried transistor implemented according to an embodiment of the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따라 구현되는 매몰형 트랜지스터의 제조방법을 보여주는 순차적인 단면도들.2A through 2D are sequential cross-sectional views illustrating a method of manufacturing a buried transistor implemented in accordance with an embodiment of the present invention.
이하 본 발명에 따른 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명할 것이다. 또한, 도면들중 동일한 구성요소 및 부분들은 가능한한 어느곳에서든지 동일한 부호들을 나타내고 있음을 유의하여야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, it should be noted that like elements and parts in the drawings represent the same numerals wherever possible.
도 2a 내지 도 2d는 본 발명의 실시예에 따라 구현되는 매몰형 트랜지스터를 제조하기 위한 순차적인 공정단면도들이다.2A through 2D are sequential process cross-sectional views for manufacturing a buried transistor implemented according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(201)에 박막의 패드산화막과 질화막(203)을 적층한후 소자분리영역과 소자활성영역을 정의하는 단계를 보이며, 보다 구체적으로 설명하면 상기 적층구조에 있어 사진공정과 식각(Etch)공정에 의해 소자분리영역의 질화막(203)을 선택적으로 식각하고 소자활성영역에는 질화막(203)을 남기는 단계와, 열산화에 의해 상기 질화막(203)이 덮히지 않은 영역에 필드 옥사이드(202)를 성장시키는 단계로 이루어 진다. 상기 공정은 일반적인 국부산화공정(LOCOS)의 일부이며, 본 발명에서는 상기 필드옥사이드(202)이 소자분리를 위하여 사용되는 것이 아니며, 또한 상기 국부산화공정에 의한 필드옥사이드(202)뿐만 아니라 폴리 버퍼트 국부산화공정(Poly Buffered LOCOS), 폴리 스페이서 국부산화공정(Poly Spacer LOCOS)등의 많은 변형된 공정에 의한 필드옥사이드도 가능하다. 상기 공정에 의하면 질화막(203) 패턴의 에지(Edge)에서 산소의 선택적 공급에 따라 필드옥사이드(202)의 에지는 경사진 모양을 가지며, 질화막 하부에 일정부분 침투하게 된다. 상기 질화막(203) 패턴 대비 침투되어진 옥사이드를 통상 버즈믹(Bird's beak)이라 칭하며, 상기 버즈빅의 크기, 즉 침투되어지는 양은 상기 질화막(203)의 두께, 질화막(203) 하부에 형성된 패드산화막의 두께, 성장시킨 필드옥사이드(202)의 두께에 의해 크게 좌우된다. 미시적으로는 산화조건, 상기 질화막(203)의 폭과 에지 프로파일(Edge profile)등에 의해 영향을 받는다.Referring to FIG. 2A, a step of defining a device isolation region and a device active region after stacking a thin film of a pad oxide film and a nitride film 203 on a semiconductor substrate 201 is described. Selectively etching the nitride film 203 in the device isolation region by a process and an etching process and leaving the nitride film 203 in the device active region, and in a region where the nitride film 203 is not covered by thermal oxidation. Growing field oxide 202. The process is part of a general local oxidation process (LOCOS), and in the present invention, the field oxide 202 is not used for device isolation, and also the field oxide 202 by the local oxidation process as well as the poly buffer. Field oxides are also possible by many modified processes, such as poly-buffered LOCOS and poly-spacer LOCOS. According to the above process, the edge of the field oxide 202 has an inclined shape according to the selective supply of oxygen at the edge of the nitride film 203 pattern, and penetrates to a lower portion of the nitride film. Oxides permeated relative to the pattern of the nitride film 203 are commonly referred to as Bird's beak, and the size of the bird's beak, ie, the amount penetrated, is the thickness of the nitride film 203 and the pad oxide film formed under the nitride film 203. It depends largely on the thickness and the thickness of the grown field oxide 202. Microscopically, it is influenced by the oxidation conditions, the width and edge profile of the nitride film 203, and the like.
도 2b를 참조하면, 상기 질화막(203)을 마스크로 하여 성장된 필드옥사이드(203)를 이방성식각(204)한 도면이다. 이후 도 2c에서와 같이 질화막(203)의 전면식각시 반도체 기판(201)의 피팅(Pitting)을 억제하기 위한 옥사이드를 얇게 성장시킨후 질화막(203)의 습식식각, 잔류 필드 옥사이드(202)의 습식식각을 통하여 안정된 형태의 버즈빅(Bird's beak) 옥사이드로 구성된 프로파일을 형성하며, 이 옥사이드(202) 프로파일을 마스크로 하여 매몰형 트랜지스터의 소오스/드래인을 위한 이온주입을 하게 되며, 이온주입시 데미지(Damage)를 방지하기 위한 버퍼 옥사이드의 존재 유무는 본 발명의 기술적 사상을 벗어나므로 언급하지 않을 것이다. 이때, 마스크인 버즈빅을 가지는 옥사이드(202)의 폭은 상기 매몰형 트랜지스터의 채널길이를 결정한다.Referring to FIG. 2B, anisotropic etching of the field oxide 203 grown using the nitride film 203 as a mask is performed. Thereafter, as shown in FIG. 2C, when the entire surface of the nitride film 203 is etched, an oxide for suppressing the fitting of the semiconductor substrate 201 is grown thinly, and the wet etching of the nitride film 203 and the wet of the residual field oxide 202 are performed. Etching forms a stable profile of Bird's beak oxide, and the ion 202 is used as a mask to inject ion / drain for the source / drain of the buried transistor, and damage during ion implantation. The presence or absence of a buffer oxide to prevent damage will not be mentioned since it departs from the technical idea of the present invention. In this case, the width of the oxide 202 having the mask of buzz big determines the channel length of the buried transistor.
도 2d는 상기 옥사이드(202)를 제거하고 게이트 산화막(205)과 게이트 전극(206)을 구비한 도면이며, 상기 사진공정시 라인 및 스페이스(오픈영역)이 반복적인 형태로 구성되어진 매몰형 확산층(204)의 피치를 1/2로 감소시키며, 집적도는 2배 증가하게 된다.FIG. 2D is a view showing a gate oxide film 205 and a gate electrode 206 having the oxide 202 removed therein, and a buried diffusion layer having lines and spaces (open regions) formed in a repetitive form during the photolithography process. The pitch of 204 is reduced to one half, and the degree of integration is doubled.
전술한 바와 같이, 본 발명은 공정조절이 용이한 적층두께 및 산화조건등에 의해 단일화된 채널길이를 확보할 수 있는 이점을 가진다. 또한, 본 발명은 매몰형 트랜지스터를 고집적화할 수 있는 이점을 가진다.As described above, the present invention has an advantage of ensuring a unified channel length due to easy stacking and oxidation conditions. In addition, the present invention has the advantage of high integration of the buried transistor.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960053514A KR100192596B1 (en) | 1996-11-12 | 1996-11-12 | Buried type transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960053514A KR100192596B1 (en) | 1996-11-12 | 1996-11-12 | Buried type transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980035236A KR19980035236A (en) | 1998-08-05 |
| KR100192596B1 true KR100192596B1 (en) | 1999-07-01 |
Family
ID=19481593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960053514A KR100192596B1 (en) | 1996-11-12 | 1996-11-12 | Buried type transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100192596B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200482362Y1 (en) | 2015-10-22 | 2017-01-13 | 윤지용 | Vegicle outside side-view mirror having light portion for daylight |
-
1996
- 1996-11-12 KR KR1019960053514A patent/KR100192596B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980035236A (en) | 1998-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4459325A (en) | Semiconductor device and method for manufacturing the same | |
| US5175119A (en) | Method of producing insulated-gate field effect transistor | |
| US5714393A (en) | Diode-connected semiconductor device and method of manufacture | |
| US4674173A (en) | Method for fabricating bipolar transistor | |
| KR100248506B1 (en) | A method of fabricating semiconductor device for improving characteristics of transistor | |
| US5547903A (en) | Method of elimination of junction punchthrough leakage via buried sidewall isolation | |
| KR930011500B1 (en) | Isolation method of semiconductor | |
| US6800528B2 (en) | Method of fabricating LDMOS semiconductor devices | |
| KR0138234B1 (en) | Structure of high voltage mos transistor | |
| KR100192596B1 (en) | Buried type transistor and manufacturing method thereof | |
| KR100273296B1 (en) | Method for fabricating mos transistor | |
| KR100642420B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| JP3061157B2 (en) | Method for forming semiconductor device | |
| KR100250098B1 (en) | Isolation area and method | |
| KR940010543B1 (en) | Fabricating method of mos transistor | |
| KR100579849B1 (en) | Semiconductor device and method for fabricating thereof | |
| KR100305205B1 (en) | Method for manufacturing semiconductor device | |
| US6136633A (en) | Trench-free buried contact for locos isolation | |
| KR100967200B1 (en) | Trench DMOS Transistor and Method for the Same | |
| KR950000151B1 (en) | Manufacturing method of semiconductor device of it ldd structre | |
| KR100497221B1 (en) | Method For Manufacturing Semiconductor Devices | |
| KR100243024B1 (en) | Method of manufacturing mos transistor | |
| KR100280535B1 (en) | MOS transistor manufacturing method | |
| KR20010064328A (en) | Method for fabricating MOS transistor with ITLDD structure | |
| KR100235980B1 (en) | Manufacturing method of mosfet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20061221 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |