KR100664871B1 - Method for Improving Profile of Source-Drain Junction in the Vicinity of Shallow Trench Isolation - Google Patents

Abstract

A method of improving the profile of a source-drain junction in an STI boundary region is disclosed. The method includes forming a photoresist pattern exposing a plurality of regions including a boundary between a region where a shallow trench isolation (STI) is to be formed and a transistor active region on a pad oxide film formed on a semiconductor substrate in advance; And forming a plurality of auxiliary diffusion regions by ion implanting impurities into the substrate using the photoresist pattern as a barrier. As such, an auxiliary diffusion region may be formed in advance prior to STI formation to improve the source / drain junction profile near the STI.

Description

Method for Improving Profile of Source-Drain Junction in the Vicinity of Shallow Trench Isolation}

1 is a cross-sectional view of a MOS transistor for explaining a problem in which current leakage occurs due to penetration of a salicide layer in the vicinity of a conventional shallow trench isolation (STI).

2A and 2B illustrate a process of forming an auxiliary diffusion region to improve a source / drain junction profile in an STI boundary region according to an embodiment of the present invention.

3A to 3C illustrate a process of forming a PMOS side auxiliary diffusion region and an NMOS side auxiliary diffusion region and forming an STI between the PMOS and NMOS transistors according to another embodiment of the present invention.

4 is a cross-sectional view of a MOS transistor with improved source / drain junction profiles in the STI boundary region in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication technology of semiconductor devices, and more particularly, to a method for improving a source / drain junction profile in an STI boundary region.

Referring to Figure 1 briefly described a conventional MOSFET manufacturing process as follows. That is, first, a shallow trench isolation (STI) 30 is formed in the silicon substrate 10 to separate the active regions of the NMOS and PMOS transistors. The gate oxide film 22 and the polycrystalline silicon gate electrode 20 are formed in the active region where the transistor is formed. Thereafter, the LDD (Lightly Doped Drain) region 12a and the source / drain diffusion region 12 are formed by an ion implantation process and a heat treatment process. Salicide is then formed on the silicon surface in the source / drain diffusion region 12 and on the polycrystalline silicon surface of the gate electrode 20.

Here, the STI 30 forms (1) a pad nitride film and a pad oxide film on the substrate 10, (2) forms a moat pattern by a photolithography process, and (3) a substrate ( 10) forming a trench to a predetermined depth in (4) and (4) depositing the STI oxide into the trench by O3-TEOS Chemical Vapor Deposition (HDP) or HDP CVD (High Density Plasma Chemical Vapor Deposition). It is formed by embedding. STI may be formed by a variety of methods and more detailed description is omitted.

In addition, the LDD region 12a and the source / drain diffusion region 12 (1) immediately after the gate electrode 20 is formed, impurity of low concentration is penetrated into the silicon substrate by ion implantation of low energy so that the LDD region 12a is formed. (2) Next, a buffer oxide film 20b and a nitride film spacer 20a are formed on the sidewalls of the gate electrode 20, and (3) the gate electrode 20 and the nitride film spacer 20a are used as a barrier. The source / drain diffusion region 12 is formed by ion implanting a high concentration of impurities into the silicon substrate 10.

As described above, after the source / drain diffusion region 12 is formed, a silicon substrate is formed by depositing a metal such as cobalt (Co) or titanium (Ti) on the entire surface of the gate electrode 20 and the substrate 10 and then performing heat treatment. The salicide layers 14 and 24 are formed on the surface and the polycrystalline silicon surface, respectively.

On the other hand, when impurities are implanted into the silicon substrate 10 to form the source / drain diffusion region 12, ion implantation may not be sufficiently performed in the region adjacent to the STI due to the inclination of the STI. In other words, the boundary between the silicon and the STI oxide embedded in the trench is inclined to one side, and this inclination serves as a barrier to ion implantation so that impurities are not sufficiently injected near the STI. In addition, although some diffusion is achieved by heat treatment after ion implantation, a junction of sufficient depth is not formed in comparison with other regions.

For this reason, a phenomenon in which the depth of the junction becomes low occurs in the region adjacent to the STI. The salicide layer 14 formed on the silicon substrate is formed by the reaction between silicon and metal. If the junction depth is low in the adjacent region of the STI, the salicide layer is formed inside the substrate 10 (ie, the region where impurities do not penetrate). The layer 14a penetrates, causing failure of the breakdown voltage BV of the transistor.

SUMMARY OF THE INVENTION An object of the present invention is to improve the source / drain junction profile by forming the auxiliary diffusion region in the substrate before forming the STI, thereby preventing the junction depth from lowering near the STI boundary due to the slope of the STI sidewall. To provide.

The method for improving the source-drain junction profile in the STI boundary region according to the present invention includes a plurality of regions including a boundary between a region where a shallow trench isolation (STI) is to be formed and a transistor active region on a pad oxide layer formed on a semiconductor substrate. Forming a photosensitive film pattern to be exposed; And forming a plurality of auxiliary diffusion regions by ion implanting impurities into the substrate using the photoresist pattern as a barrier. Thus, auxiliary diffusion regions can be preformed prior to STI formation to improve the source / drain junction profile near the STI.

Here, the photosensitive film pattern for forming the auxiliary diffusion region is preferably formed on the pad oxide film formed in advance on the substrate. In other words, when the pad oxide film is used as a barrier against ion implantation performed when forming the auxiliary diffusion region, damage to the substrate can be prevented.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

First, in order to form the STI according to the exemplary embodiment of the present invention, the pad oxide layer 32 is formed on the surface of the substrate 10. In the conventional STI forming process, a pad nitride film is formed directly on the pad oxide film 32. In an embodiment of the present invention, a preliminary ion implantation process is performed to form a source-drain junction before forming the pad nitride film. That is, as shown in FIG. 2A, a photosensitive film is coated on the pad oxide film 32. Thereafter, the photoresist film is formed of a photoresist pattern 40 that exposes the boundary region of the field region F and the transistor active region A in which the STI is to be formed through a photolithography process.

The photoresist pattern 40 exposes a region B including a portion of the region where the STI is to be formed and a portion of the source / drain diffusion region, and implants impurities such as a p-type dopant or an n-type dopant in the exposed region. To form the auxiliary diffusion region 13 (see FIG. 2B).

After that, the STI is formed in the region F according to the general STI formation method. In this process, impurities implanted into the auxiliary diffusion region 13 may be diffused into the substrate 10 by heat treatment performed during the STI forming process, but the range of the auxiliary diffusion region 13 may be adjusted so that the diffusion range thereof is not large. If set, does not affect other processes. That is, the auxiliary diffusion region 13 undergoes more thermal processes than the conventional source / drain diffusion region 12 but is far from the channel, and thus does not significantly affect the threshold voltage Vt and the drain current Id. However, in consideration of the current leakage at the junction, it is preferable to form as narrow as possible to the STI side.

When the auxiliary diffusion region 13 is formed as described above, a transistor structure having a shape as shown in FIG. 4 is obtained. 4 is similar to the transistor structure shown in FIG. 1, but the profile of the source / drain junction in the vicinity of STI is improved. That is, even if the salicide layer 14 penetrates deeply, the junction diffusion region 13 is deeply formed due to the auxiliary diffusion region 13 so that the auxiliary diffusion region 13 is specifically a source / drain diffusion region ( Since it is formed up to a depth of 12), it is not in direct contact with silicon without impurities. Thus, current leakage in the vicinity of STI is prevented.

In the case where the PMOS transistor and the NMOS transistor are formed adjacent to each other according to another embodiment of the present invention, the above-described process of forming the auxiliary diffusion region may be repeated. That is, first, a photoresist pattern is formed to expose the transistor active region on the PMOS side and the auxiliary diffusion region on the PMOS side overlapping the STI formation region to ion implant impurities of the p-type dopant. At this time, ion implantation is blocked on the NMOS side by the photosensitive film pattern. Next, the photoresist pattern is removed and a new photoresist pattern is formed which exposes the NMOS side transistor active region and the NMOS side auxiliary diffusion region overlapping the STI formation region. Thereafter, impurities of an n-type dopant are ion implanted into the NMOS side auxiliary diffusion region.

The PMOS side auxiliary diffusion region 13a and the NMOS side auxiliary diffusion region 13b thus formed are shown in FIG. 3A. After the auxiliary diffusion regions 13a and 13b are formed in this manner, the pad nitride film 34 is formed on the pad oxide film 32. Thereafter, a moat pattern is formed using the photosensitive film, the pad nitride film 34 and the pad oxide film 32 are etched through an etching process, and a trench 30a is formed in the substrate 10 (FIG. 3B). At this time, a portion of the auxiliary diffusion regions 13a and 13b are removed together so that only a portion remains on both sides of the trench.

Next, an O3-TEOS CVD oxide film or an HDP CVD oxide film is embedded in the trench 30a as an STI filling material (see FIG. 3C). The gate oxide film 22 and the polycrystalline silicon gate 20 are then processed according to a general MOS transistor manufacturing process. ), The buffer oxide film 20b, the nitride film spacer 20a, the LDD region 12a, the source / drain diffusion region 12, and the salicide layers 14 and 24 are formed, respectively. The MOS transistor thus formed is shown in FIG. 4. As described above, even if the salicide layer 14 penetrates deep due to the auxiliary diffusion region 13a or 13b, it is not directly in contact with the silicon without impurities. Thus, current leakage in the vicinity of STI is prevented.

According to the present invention, the slope of the STI sidewalls can prevent the source / drain junction from decreasing in depth near the STI boundary. Therefore, the salicide layer can be prevented from penetrating into the silicon substrate free of impurities and preventing current leakage, and improving the isolation characteristics of the STI.

Although a preferred embodiment of the present invention has been described so far, those skilled in the art will be able to implement in a modified form without departing from the essential characteristics of the present invention. Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation. Should be interpreted as being included in.

Claims (3)

Forming a photoresist pattern on the pad oxide layer formed on the semiconductor substrate to expose a plurality of regions including a boundary between a region where a shallow trench isolation (STI) is to be formed and a transistor active region; And Forming a plurality of auxiliary diffusion regions by ion implanting impurities into the substrate using the photoresist pattern as a barrier; The auxiliary diffusion region is formed to the depth of the source / drain diffusion region, characterized in that the source-drain junction profile improvement in the STI boundary region. delete The method of claim 1, Forming a salicide layer over said auxiliary diffusion region, Preventing the salicide layer from penetrating the semiconductor substrate by the auxiliary diffusion region to improve the profile of the source-drain junction at the STI boundary region. .

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