KR100961962B1 - Driving apparatus and method for liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and method for a liquid crystal display device, comprising: a storage unit including a memory, one end of which is connected to the storage unit, and a switch which is turned on / off in accordance with a first signal from the outside; And a signal controller connected to the other end of the switch and communicating with the storage unit when the switch is turned on, and correcting data in the memory according to a second signal from the outside when the switch is turned off. In this way, a switch is provided between the signal control section and the storage section to cut off the communication lines of the signal control section and the storage section, if necessary, so that the data of the EEPROM can be modified while the storage section made up of the IC chip is mounted without being removed from the substrate. In addition, the signal controller is not affected by the write operation from the external device.

Liquid Crystal Display, EEPROM, Switch, I2C, Data Line, Clock Line

Description

DRIVING APPARATUS AND METHOD FOR LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a driving device for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a circuit diagram of a memory unit and a switch according to an exemplary embodiment of the present invention.

5 shows a symbol of a switch according to an embodiment of the present invention.

The present invention relates to a drive device for a liquid crystal display device, and more particularly to a device for correcting data stored in an EEPROM used in a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent deterioration caused by the application of an electric field in one direction for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or dot.

The control board for controlling the liquid crystal display device includes a signal controller. The signal controller includes a maskable ROM, which stores data for lookup tables used to correct video signals displayed on the liquid crystal display. However, many users of the liquid crystal display device require data for a lookup table suitable for user characteristics. Therefore, in order to meet these demands, a separate EEPROM is mounted outside the signal controller so that the lookup table data can be selectively used by the ROM inside the signal controller and the EEPROM outside the signal controller according to the user's request.

However, if the data for the lookup table needs to be corrected, the EEPROM, which is soldered to the control board, should be removed from the control board, the data must be corrected, and then soldered to the control board again. In this process, errors of ROM data may be generated, and the process itself is quite complicated.

Accordingly, an object of the present invention is to provide a drive device for a liquid crystal display device capable of modifying lookup table data without removing the EEPROM from the control board.

In accordance with an aspect of the present invention, there is provided a driving apparatus for a liquid crystal display device, the memory including a memory and one end of which is connected to the memory and on / off according to a first signal from the outside. And a signal controller connected to the other end of the switch and communicating with the storage unit when the switch is turned on, and when the switch is turned off, the data of the memory according to a second signal from the outside. Correct it.

Preferably, the signal control unit and the storage unit communicate through an inter integrated circuit control (I2C) interface.

The I2C interface includes a clock line SCL and a data line SDA, and the switch may short or open the clock line and the data line.

Preferably, the storage unit and the switch are connected through the clock line and the data line, and the second signal is applied to the clock line and the data line between the storage unit and the switch.

According to another exemplary embodiment of the present invention, a driving method of a liquid crystal display device including a storage unit including a driving memory, a signal controller communicating with the storage unit, and a switch connected between the storage unit and the signal controller may include: Turning on / off the switch in response to a signal from, reading data in the memory when the switch is on, and writing new data to the memory when the switch is off.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display to which a driving device according to an exemplary embodiment of the present invention is applied will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.                     

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminals are connected to the liquid crystal capacitor (C _LC ) and the holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. Is made of.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

Next, the driving apparatus for the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a block diagram of a driving device for a liquid crystal display according to an exemplary embodiment of the present invention.                     

As shown in FIG. 3, the driving apparatus for the liquid crystal display according to the present invention includes a signal controller 600, a switch 40 connected to the signal controller 600, and a storage unit 50 connected to the switch 40. do.

The signal controller 600 and the memory unit 50 are connected via an inter integrated circuit control (I2C) interface, which is a communication method proposed by Philips, with the switch 40 interposed therebetween. I2C is a bus interface that allows devices connected via two bidirectional communication lines, that is, clock line SCL and data line SDA, to communicate with each other. Accordingly, the clock line SCL of the signal controller 600 is connected to the clock line SCL of the storage unit 50 through the switch 40, and the data line SDA of the signal controller 600 is also switched by the switch 40. ) Is connected to the data line SDA of the storage unit 50. In this embodiment, the signal control unit 600 becomes a master and the storage unit 50 becomes a slave.

The switch 40 is turned on / off according to a write protection (WP) signal from an external device (not shown), and the clock line SCL and data to which the signal controller 600 and the storage unit 50 are connected. Short or open line SDA.

When the switch 40 is turned on, the signal controller 600 and the memory 50 perform serial communication through the clock line SCL and the data line SDA. The storage unit 50 includes an EEPROM (not shown), and the signal control unit 600 reads data from the EEPROM (not shown).

Meanwhile, the clock line SCL and the data line SDA from an external device (not shown) may be applied to the clock line SCL and the data line SDA to which the switch 40 and the storage unit 50 are connected. Can be.

When the switch 40 is turned off, the signal controller 600 and the memory 50 are disconnected and are in a state in which communication cannot be performed. In the state where the switch 40 is turned off, the external device becomes a master and the storage unit 50 becomes a slave. In this state, the external device can write new data to the EEPROM of the memory 50.

4 and 5, the operation of the driving apparatus for the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail.

4 is a circuit diagram of a memory unit and a switch according to an embodiment of the present invention, and FIG. 5 shows a symbol of a switch according to an embodiment of the present invention.

As shown in Fig. 4, the switch 40 is composed of one IC chip, and there are two switches inside the IC chip. One of the two switches consists of terminals 1A, 1B and OE1 and the other consists of terminals 2A, 2B and OE2. In the present embodiment, the switch 40 uses a 2-bit bus switch FSA266 manufactured by "FAIRCHILD".

As shown in FIG. 5, the symbols of the two switches can be shown. Here, 1A and 1B are connected when the signal input to the control input terminals OE1 and OE2 is high level, and 2A and 2B are connected, and when the signal is low level, they are not connected.

In this embodiment, the data line SDA from the signal control unit 600 is connected to the terminal 1B, and the data line SDA from the storage unit 50 is connected to the terminal 1A. The clock line SCL from the signal controller 600 is connected to the terminal 2A, and the clock line SCL from the storage unit is connected to the terminal 2B. The control input terminals OE1 and OE2 are commonly connected to a write protection (WP) signal from an external device.

On the other hand, the memory unit 50 also includes one IC chip. The data line SDA and the clock line SCL terminals connected to the switch 40 are pulled up with resistors R2 and R3 at the power supply voltage VCC. The write inhibit terminal VCLK is also pulled up to the power supply voltage VCC with a resistor R1 and connected to a write protection signal WP from an external device. It can be seen that the address terminals NC1, NC2, NC3 of the I2C bus are grounded so that the external address for the storage unit 50 is "000".

The data line SDA and the clock line SCL between the storage unit 50 and the switch 40 have a data line port SDA_P and a clock line port so that an external device can communicate with the storage unit 50. (SCL_P) is provided.

The operation of the driving apparatus of this embodiment according to the write protection (WP) signal from the external device will now be described.

When the write protection signal WP is not input, the write prohibition terminal VCLK of the storage unit 50 and the control input terminals OE1 and OE2 of the switch 40 are at a high level, so that the storage unit 50 has a high level. It is not possible to write data to the EEPROM, and each of the terminals 1A, 1B (2A, 2B) of the switch 40 is connected. Therefore, the signal controller 600 and the memory 50 may communicate.

When the low level write protection signal WP is input from the external device, the write prohibit terminal VCLK of the storage unit 50 and the control input terminals OE1 and OE2 of the switch 40 are set to the low level so that the storage unit ( Data can be written to the EEPROM of 50, and the terminals 1A, 1B (2A, 2B) of the switch 40 are not connected. Therefore, the external device can communicate by accessing the data line SDA and the clock line SCL of the storage unit 50 and write data to the EEPROM of the storage unit 50. That is, the external device can modify the data of the EEPROM of the storage unit 50 without affecting the signal controller 600.

Thus, by providing the switch 40 between the signal control part 600 and the memory | storage part 50, and disconnecting the communication lines SDA and SCL of the signal control part 600 and the memory | storage part 50 as needed, It is possible to modify the data of the EEPROM in the memory unit 50 in a state in which the memory unit 50 made of the chip is mounted without being removed from the substrate, and the signal controller 600 is affected by a write operation from an external device. Do not receive.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

In this way, a switch is provided between the signal control section and the storage section to cut off the communication lines of the signal control section and the storage section, if necessary, so that the data of the EEPROM can be modified while the storage section made up of the IC chip is mounted without being removed from the substrate. In addition, the signal controller is not affected by the write operation from the external device.

Claims (5)

A memory containing memory, A switch connected at one end to the storage unit and switched on / off according to a first signal from the outside; and A signal controller connected to the other end of the switch and communicating with the storage unit when the switch is turned on Including, When the switch is off, modify the data of the memory in accordance with a second signal from the outside, And the storage unit and the switch are connected through a clock line (SCL) and a data line (SDA), and the switch and the signal control unit are connected through the clock line and the data line. delete In claim 1, And the switch short-circuits or opens the clock line and the data line. 4. The method of claim 3, And the second signal is applied to the clock line and the data line between the storage unit and the switch. A storage unit including a memory, a signal control unit communicating with the storage unit, and a switch connected between the storage unit and the signal control unit, wherein the storage unit and the switch include a clock line SCL and a data line SDA. A method of driving a liquid crystal display device connected through a switch, wherein the switch and the signal controller are connected through the clock line and the data line. Turning on / off the switch according to a signal from an external device, Reading the data in the memory when the switch is on, and Writing new data to the memory when the switch is turned off Method of driving a liquid crystal display comprising a.

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