KR100973808B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of reducing the usage of frame memory. The liquid crystal display according to the present invention includes a plurality of pixels, a signal controller which receives image data from the outside and a control signal for controlling the display thereof, a frame memory that receives image data through a data bus from the signal controller, and a signal controller. A data driver which selects a gray voltage corresponding to the image data and supplies the same to the pixel, wherein the frame memory includes a plurality of memories having first and second spaces, respectively, each of the first and second spaces includes a write mode, Repeating the holding mode and the reading mode sequentially, the signal controller receives the image data for a predetermined time and allocates the image data to the data bus of the frame memory. The data bus has a predetermined bit, and the signal controller controls the number of memory and the predetermined bit of the data bus. After receiving the multiplied image data, each predetermined data bus It allocates by bit. In this way, by receiving the predetermined time data and allocating the data to the entire data bus of the frame memory, the number of memories can be reduced and the cost can be saved.

Frame, memory, clock, signal controller, liquid crystal display, frequency, data bus, digital signal processing, DCC, EMI

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can reduce the number of frame memories by optimizing use of the frame memory.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

On the other hand, the LCD includes a signal control unit for receiving and processing image data from the outside and control signals for controlling the display thereof. This process basically processes a digital signal. In order to process the digital signal in one frame unit, an image signal from the outside is stored in a memory and output. Dynamic capacitance compensation (DCC) is currently used as such digital processing.

This is one of the typical digital signal processing methods as a method of increasing the charging speed of the liquid crystal by comparing the current frame with the previous frame stored in the memory and outputting a compensated frame.

At this time, the data buses of the memory produced these days are in units of 8, 16 and 32 bits.

However, for example, when the image data R, G, and B are 8 bits each and 24 bits each, the memory uses a memory having a 32-bit data bus (hereinafter referred to as '32 -bit memory '). Typically, only 24 bits are allocated on the data bus, leaving the remaining 8 bits unused, which wastes memory. In particular, when data is transmitted through a dual interface to process a large amount of data, 48 bits are input, and when the data is written to two memories again, 16 bits are wasted.

Accordingly, an object of the present invention is to provide a driving device of a liquid crystal display device capable of optimizing the use of a memory.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of pixels, a signal controller, a frame memory, and a data driver. The signal controller receives the image data from the outside and a control signal for controlling the display thereof, the frame memory receives the image data from the signal controller through a data bus, and the data driver receives the image data from the signal controller. The gray voltage corresponding to the voltage is selected and supplied to the pixel. The frame memory includes a plurality of memories having first and second spaces, respectively, wherein each of the first and second spaces sequentially repeats a write mode, a sustain mode, and a read mode, and the signal controller controls the signal for a predetermined time. The image data is received and allocated to the data bus of the frame memory. In this case, the data bus has a predetermined bit, and the signal controller receives image data multiplied by the number of the memory and a predetermined bit of the data bus, and then allocates the predetermined number of bits to the data bus of the memory. desirable.

A liquid crystal display according to another exemplary embodiment of the present invention includes a plurality of pixels, a signal controller, a frame memory, and a data driver. The signal controller receives the image data from the outside and a control signal for controlling the display thereof, the frame memory receives the image data from the signal controller through a data bus, and the data driver receives the image data from the signal controller. The gray voltage corresponding to the gray voltage is selected and supplied to the pixel, and the signal controller receives the image data during the first clock and allocates the image data to the data bus of the frame memory during the second clock. In this case, the data bus has a predetermined bit, and the signal controller receives image data multiplied by the number of the memory and a predetermined bit of the data bus, and then allocates the predetermined number of bits to the data bus of the memory. desirable. In addition, the frequency of the second clock is preferably higher than the frequency of the first clock.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected thereto, a data driver 500, and a data driver. The gray voltage generator 800 connected to the signal generator 500 includes a signal controller 600 and a frame memory 700 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal, and applies the image signals R, G, and B to operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500. . In addition, a read or write signal is provided to the frame memory 700 to store current frame data and output previous frame data.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.                     

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode 190 and the common electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Meanwhile, as described above, the signal controller 600 controls the operation of the frame memory 700, which will be described in detail with reference to FIGS. 3 and 4.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 3, the liquid crystal display according to the exemplary embodiment of the present invention includes a signal controller 600 and a frame memory 700.

The signal controller 600 receives image data R, G, and B from the outside and stores the image data R, G, and B in the frame memory 700.

The frame memory 700 includes three frame memories 701, 702, and 703. The data bus of each frame memory 701, 702, and 703 is 32 bits, and each frame memory 701, 702, and 703 is It has two separate spaces (A, B), each space sequentially repeats the read mode, hold mode and write mode based on the control signal of the signal controller 600 do.

The signal controller 600 receives the image data of the current frame, that is, the current frame data, stores them in the frame memories 701, 702, and 703, and then reads out previous frame data stored in the frame memories 701, 702, and 703. . Subsequently, after comparing the current frame data with the previous frame data, the frame data compensated for the result is exported to the data driver 500.

On the other hand, when the signal control unit 600 stores the current frame data in the frame memories 701, 702, and 703, the data is divided and stored. For example, in a dual interface where 48 bits per clock are input simultaneously, 96 bits of data are received for two clocks, divided into three 32-bit data, and allocated to each frame memory 701, 702, and 703. That is, after receiving image data corresponding to the capacity of the data bus and the number of memories, the data is allocated according to the number of bits of the data bus. At this time, each data bus is allocated as many as the number of bits of each data bus so that there is no shortage.

In this way, when the input data is collected for two clocks and divided into three 32-bit data, the number of frame memories can be reduced by one. Conventionally, four 32-bit memories were required to read and write 96 bits of data. That is, 48 bits are divided into 24 bits, the current frame data is written to two memories, and the previous frame is read from two memories. Therefore, according to one embodiment of the present invention, it is possible to reduce the cost by using all of them without wasting data buses and at the same time reducing the number of memories.

4 illustrates a liquid crystal display according to another exemplary embodiment of the present invention. Unlike the embodiment shown in FIG. 3, the frame memory 700 includes two frame memories 704 and 705.

4 shows a case where data is processed using two frame memories 704 and 705. FIG. At this time, in order to read and write 96-bit data using the two frame memories 704 and 705, the clock frequency DCLK of the frame memories 704 and 705 must be changed. Since one frame memory has to play two roles, the clock DCLK of the memories 704 and 705 is typically twice the main clock MCLK to store the same data within the same time. That is, since two memory clocks DCLK are included in one main clock MCLK, 48 bits of data may be transmitted during one main clock MCLK.

The embodiment according to the present invention requires a clock DCLK that is 1.5 times the main clock MCLK. As described above, it receives 96 bits of data for 2 clocks, but transfers data by allocating data to the entire 32-bit data bus. Thus, 64 bits of data are transmitted per clock based on the main clock MCLK. All require only 1.5 clocks to carry 96 bits of data. This has the effect of reducing the clock frequency to reduce EMI.

In addition, in the embodiment shown in Fig. 4, unlike the embodiment shown in Fig. 3, the memories 704 and 705 do not need to be spatially divided. This is because each of the two memories repeats the write, hold, and read modes sequentially. For example, the memory 704 writes and maintains current frame data and reads previous frame data. The same applies to the memory 705.

Although the 32-bit data bus has been described above as an example, it is obvious that the present invention can be applied to data buses having 8-bit and 16-bit or other capacities.

In this way, when a certain amount of data is collected and allocated across the data bus, the number of frame memories can be reduced, resulting in cost savings, as well as reducing the clock frequency of the memory to reduce EMI.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

A liquid crystal display device comprising a plurality of pixels, A signal controller receiving a control signal for controlling image data and display thereof from the outside; A frame memory for receiving the image data from the signal controller through a data bus, and A data driver which selects a gray voltage corresponding to the image data from the signal controller and supplies it to the pixel Including, The frame memory includes a plurality of small memories having first and second spaces, respectively, Each of the first and second spaces sequentially repeats a write mode, a sustain mode, and a read mode, And when the bits of the image data and the bits of the small memory are different, the signal controller receives the image data for a plurality of clock times, divides the image data into bits of the small memory, and allocates the image data to a data bus of the frame memory. In claim 1, And the image data received during the plurality of clock times is an integer multiple of the small memory bit. A liquid crystal display device comprising a plurality of pixels, A signal controller receiving a control signal for controlling image data and display thereof from the outside; A frame memory for receiving the image data from the signal controller through a data bus, and A data driver which selects a gray voltage corresponding to the image data from the signal controller and supplies it to the pixel Including, The signal controller receives the image data during a first clock and allocates the image data to a data bus of the frame memory during a second clock. The frequency of the second clock is higher than the frequency of the first clock Liquid crystal display. 4. The method of claim 3, The data bus has a predetermined bit, The signal controller receives image data multiplied by the number of the memory and predetermined bits of the data bus, and then allocates the predetermined number of bits to the data bus of the memory. Liquid crystal display. delete

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