CN110428767B - Driving circuit of display panel and display device - Google Patents
Driving circuit of display panel and display device Download PDFInfo
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- CN110428767B CN110428767B CN201910573180.5A CN201910573180A CN110428767B CN 110428767 B CN110428767 B CN 110428767B CN 201910573180 A CN201910573180 A CN 201910573180A CN 110428767 B CN110428767 B CN 110428767B
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- 230000015654 memory Effects 0.000 claims abstract description 272
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 238000004891 communication Methods 0.000 claims description 32
- 230000003287 optical effect Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 description 21
- 239000010409 thin film Substances 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 6
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- 239000010408 film Substances 0.000 description 4
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- 238000004806 packaging method and process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
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- 239000003990 capacitor Substances 0.000 description 2
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- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
- G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
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Abstract
The invention discloses a drive circuit of a display panel and a display device, wherein the drive circuit of the display panel comprises a time schedule controller, a first memory and a second memory, and data transmission ends of the first memory and the second memory are connected with the data transmission end of the time schedule controller; the first memory is configured to work when receiving the first chip selection signal, and the stored software data is read by the time schedule controller; the controlled end of the memory switch control circuit is connected with the chip selection signal output end of the time schedule controller, and the control signal output end is connected with the chip selection pin of the second memory; the memory switch control circuit receives the second chip selection signal to be conducted and outputs the chip selection signal for controlling the second memory to work to the second memory so as to enable the time schedule controller to read the stored software data. The invention solves the problems that the whole driving framework of the display panel can not be packaged in a small way, and has large volume and higher cost.
Description
Technical Field
The present invention relates to the field of display driving technologies, and in particular, to a driving circuit of a display panel and a display device.
Background
In a display device, data in a static read only memory SROM inside a timing controller TCON IC cannot be stored after power failure, but data stored in an EEPROM (Erasable Programmable read only memory) or a Flash memory Flash can be stored even after power failure, so that a control program of the timing controller is stored in the external memory EEPROM or Flash. In the display device, the number of the memories is more than one, and each memory needs to be respectively connected with the time schedule controller in a communication mode through a group of communication lines.
This results in the whole driving structure of the display panel not being small, bulky and costly.
Disclosure of Invention
The invention provides a driving circuit of a display panel and a display device, and aims to solve the problems that the whole driving structure of the display panel cannot be subjected to small packaging, and is large in size and high in cost.
In order to achieve the above object, the present invention provides a driving circuit of a display panel, including:
a timing controller configured to output a first chip select signal and a second chip select signal;
the data transmission ends of the first memory and the second memory are connected with the data transmission end of the time schedule controller; the first memory is configured to work when receiving a first chip selection signal, and the stored software data is read by the time schedule controller;
the memory switch control circuit comprises a controlled end and a control signal output end, the controlled end is connected with a chip selection signal output end of the time sequence controller, and the control signal output end is connected with a chip selection pin of the second memory; and the memory switch control circuit is configured to be turned on after receiving the second chip selection signal and output a chip selection signal for controlling the second memory to work to the second memory so that the timing controller can read the stored software data.
Optionally, the timing controller is further configured to output a third chip select signal to control the first memory to stop operating, and control the memory control switch circuit to turn off and output a chip select signal to control the second memory to operate to control the second memory to stop operating.
Optionally, the software data stored in the first memory is initialization software data of the display panel;
the software data stored in the second memory is optical compensation software data.
Optionally, the driving circuit of the display panel further includes a serial communication bus, and the timing controller is connected to the first memory and the second memory through the serial communication bus.
Optionally, the memory switch control circuit includes a first switch tube and a pull-up resistor, the controlled end of the first switch tube is the controlled end of the memory switch circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is the chip selection signal output end of the memory switch control circuit and is connected to the first dc power supply through the pull-up resistor.
Optionally, the driving circuit of the display panel further includes a gate driving circuit and a source driving circuit, and controlled ends of the gate driving circuit and the source driving circuit are respectively connected to an output end of the timing controller.
The present invention further provides a driving circuit of a display panel, the driving circuit of the display panel comprising:
a timing controller configured to output a first chip selection signal, a second chip selection signal, and a third chip selection signal;
a first memory configured to store initialization software data of the display panel;
a second memory configured to store optically compensated software data;
the data transmission ends of the first memory and the second memory are both connected with the data transmission end of the time sequence controller; the first memory is also configured to work when receiving a first chip selection signal, and the stored initialization software data of the display panel is read by the time schedule controller;
the memory switch control circuit comprises a controlled end and a control signal output end, wherein the controlled end is connected with a chip selection signal output end of the time schedule controller, and the control signal output end is connected with a chip selection pin of the second memory; the memory switch control circuit is configured to be switched on when receiving the second chip selection signal so as to control the second memory to work, and the stored optical compensation software data is read by the time schedule controller;
the time schedule controller is also configured to output a third chip selection signal to control the first memory to stop working and control the memory control switch circuit to be switched off to control the second memory to stop working.
Optionally, the specific working process of the timing controller is as follows:
outputting the first chip selection signal, controlling the first memory to work, and reading the initialization software data of the display panel stored in the first memory;
outputting the second chip selection signal to control the on-off of the memory switch control circuit so as to control the second memory to work, and reading the optical compensation software data stored in the second memory by the time schedule controller after the second memory works;
and outputting the third chip selection signal to control the first memory to stop working, and controlling the memory switch control circuit to be switched off so as to control the second memory to stop working.
The invention also provides a display device, which comprises a display panel and the driving circuit of the display panel, wherein the gate driving circuit and the source driving circuit of the display panel are respectively electrically connected with the display panel.
Optionally, the display device further comprises a timing control board and a source driving printed circuit board;
the time sequence controller and the first memory of the driving circuit of the display panel are arranged on the time sequence control board;
and the second memory of the driving circuit of the display panel is arranged on the source electrode driving printed circuit board.
The invention realizes the communication connection with the first memory and the second memory through the same serial communication bus by arranging the memory switch control circuit, the time schedule controller, the first memory and the second memory. The memory switch control circuit is arranged between the chip selection pin of the first memory and the time schedule controller in series, the memory switch control circuit is controlled based on the chip selection signal of the time schedule control circuit, and when the time schedule controller controls the memory switch control circuit to be closed, the communication connection between the time schedule controller and the first memory is realized, so that the time schedule controller reads the software data of the first memory, and the initial setting of the time schedule controller is further completed. When the time schedule controller controls the on-off control circuit of the memory to be started, the communication connection between the time schedule controller and the second memory is realized, so that the time schedule controller reads the software data of the second memory. The invention solves the problems that the whole driving framework of the display panel can not be subjected to small packaging, and the size is large and the cost is higher because the time schedule controller needs to realize communication connection with different memories by arranging a plurality of groups of serial communication buses.
Meanwhile, the invention also solves the problems that when the time schedule controller reads the data of the first memory, the data of the second memory possibly enters the time schedule controller, so that the data reading of the first memory by the time schedule controller fails, or when the data of the second memory is read, the data of the first memory is serially connected to the time schedule controller, and the data reading of the second memory by the time schedule controller fails. The invention also effectively solves the problem of wrong software reading of the time sequence controller when the same serial communication bus is adopted to connect the memories, and improves the reliability of the display device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of a driving circuit of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a driving circuit of a display panel according to an embodiment of the present invention;
FIG. 3 is a functional block diagram of another embodiment of a driving circuit of a display panel according to the present invention;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the invention.
The reference numbers indicate:
the implementation, functional features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, back, 8230; etc.) are involved in the embodiment of the present invention, the directional indications are only used for explaining the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the figure), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a driving circuit of a display panel.
Referring to fig. 1 to 3, in an embodiment of the present invention, a driving circuit of a display panel includes:
a timing controller 10 configured to output a first chip select signal and a second chip select signal;
a first memory 20 and a second memory 30, wherein the data transmission terminals of the first memory 20 and the second memory 30 are connected to the data transmission terminal of the timing controller 10; the first memory 20 is configured to operate when receiving a first chip select signal, and is used for the timing controller 10 to read stored software data;
the memory switch control circuit 40 comprises a controlled end and a control signal output end, the controlled end is connected with the chip selection signal output end of the time schedule controller 10, and the control signal output end is connected with the chip selection pin of the second memory 30; the memory switch control circuit 40 is configured to be turned on when receiving the second chip select signal to control the second memory 30 to operate, and the timing controller 10 is provided to read the stored software data.
Referring to fig. 3, in this embodiment, the driving circuit of the display panel further includes a gate driving circuit 50 and a source driving circuit 60, and controlled terminals of the gate driving circuit 50 and the source driving circuit 60 are respectively connected to an output terminal of the timing controller 10. The timing controller 10 generates timing control signals for driving the gate driving circuit 50 and the source driving circuit 60 to operate according to the received display data, so that the gate driving circuit 50 drives active switches connected to corresponding scan lines in the display panel to be turned on, and the source driving circuit 60 outputs the received data signals to the display panel to drive the display panel to operate.
The first memory 20 and the second memory 30 may be implemented by an EEPROM (Erasable Programmable read only memory) or a Flash memory Flash. The first memory 20 and the Timing Controller 10 may be disposed on a Timing Controller (TCON) PCB, the first memory 20 may store control signals for driving a gate driver ic and a source driver ic to operate, and is in communication connection with the Timing Controller 10 through a serial communication bus, when the display device is powered on to operate, the Timing Controller 10 reads the control signals in the first memory 20 and performs initial setting on other set data to generate corresponding Timing control signals, so as to drive the source driver ic and the gate driver ic of the display panel in the display device to operate, that is, the software data stored in the first memory 20 is initialized software data of the display panel; the data in the first memory 20 cannot be modified when the display device is operating normally, and once the data is modified to make the setting data wrong, the display device is abnormal. Therefore, the first memory 20 is mostly provided with a write protect pin (WP pin), and when a high level is input, the first memory 20 can be controlled to write data, and when a low level is input, the data cannot be written, and at this time, the first memory 20 is only used for the timing controller 10 to read data. The second memory 30 may be disposed on the printed circuit board X-PCB for connecting the source driving circuit 60, and the second memory 30 may store the brightness compensation demura table data, that is, the software data stored in the second memory 30 is the optical compensation software data. The timing control board is further provided with a driving power supply 70, that is, the output end of the driving power supply 70 is respectively connected with the first memory 20, the second memory 30 and the timing controller 10, and the accessed power supply is converted into the power supply of the circuit module to supply power to the circuit module. After the timing controller 10 is powered on, the initialized parameter data and demura table data are read from the first memory 20 and the second memory 30 for initialization, and then the R/G/B compressed signal and the control signal output by the MCU on the main control board in the display device are received through the serial communication bus, and the power supply on the main control board drives the power supply 70 through the power line. The driving power supply 70 converts the received power supply into a corresponding driving power supply and outputs the driving power supply to the circuit module on the timing control board. After the display device normally operates, the timing controller 10 converts the received R/G/B compression signals and control signals into data signals, control signals, and clock signals suitable for the source driving circuit 60 and the gate driving circuit 50 in the display device, thereby implementing image display of the display panel.
Referring to fig. 1 or fig. 2, the memory may be a high level enable or a low level enable, and the present embodiment may be a low level enable, and correspondingly, the first chip select signal is a low level signal and the second chip select signal is a high level signal. The first memory 20 and the second memory 30 each include a chip select pin CS, a data input pin SI, an output pin SO, and a clock signal pin SCLK, and in some embodiments, the first memory 20 and the second memory 30 also include a Hold pin. The chip select pin of the first memory 20 is connected to the timing controller 10, and the chip select pin of the second memory 30 is connected to the memory switch control circuit 40, that is, the first memory 20 is controlled by the timing controller 10 and is selected when the first chip select signal is received, and is not selected when the second chip select signal is received. The second memory 30 is controlled by a memory switch control circuit 40, and the memory switch control circuit 40 is turned on/off according to a chip select signal of the timing controller 10. Specifically, when the timing controller 10 outputs the first chip select signal, the memory switch control circuit 40 outputs a high-level chip select signal to the second memory 30, and thus the second memory 30 is not selected. And is turned on when receiving the second chip select signal outputted from the timing controller 10, and at this time, the memory switch control circuit 40 outputs a low-level chip select signal to the second memory 30, so that the second memory 30 is selected.
It should be noted that, the timing controller 10 and the first memory 20 and the second memory 30 are respectively connected to each other by two sets of serial communication buses, so that the whole driving structure of the display panel cannot be small, and has a large size and a high cost. For this reason, in the present embodiment, the first memory 20 and the second memory 30 are implemented by using the same set of serial communication buses, and in the process of reading data by the timing controller 10, other chips may be affected, for example, when the timing controller 10 reads data of the first memory 20, data of the second memory 30 may enter the timing controller 10, or when the timing controller 10 reads data of the second memory 30, a data signal of the first memory 20 is output to the timing controller 10 to cause a disorder of operation of the timing controller 10, so that the timing controller 10 fails to read data of the two memories.
In order to solve the above problem, the driving circuit of the display panel of the present embodiment may further be provided with a memory switch control circuit 40 to implement the switching of the memory. Specifically, the memory switch control circuit 40 is turned on/off by receiving a chip select signal output from the timing controller 10, and when the display device is powered on, the timing controller 10 outputs a first chip select signal to control the memory switch control circuit 40 to be turned off and the first memory 20 to be selected. The time schedule controller 10 is connected to the first memory 20 through a serial communication bus for reading the software data of the first memory 20, so as to realize the initial setting of the time schedule controller 10. In this process, the memory switch control circuit 40 is in the off state, so that the data of the second memory 30 is not output to the first memory 20 or the timing controller 10 via the serial communication bus, and the data reading of the first memory 20 by the timing controller 10 is interfered. The timing controller 10 outputs a second chip select signal to control the memory switch control circuit 40 to be turned on, so as to output a low-level chip select signal to the second memory 30, and the second memory 30 is selected, and the timing controller 10 is in communication connection with the second memory 30 through a serial communication bus to read the software data of the second memory 30, thereby realizing the brightness compensation of the display panel. In this process, the first memory 20 receives the second chip select signal and is not selected, so that the data in the first memory 20 is not output to the second memory 30 or the timing controller 10 through the serial communication bus, and the data in the second memory 30 read by the timing controller 10 is not interfered. When the initialization is finished and the display device enters a normal working state, the timing controller 10 is in communication connection with the control chip 20 through the serial communication bus, so as to receive the control signal, the data signal and the clock signal output by the control chip 20, convert the control signal, the data signal and the clock signal into corresponding driving signals and output the driving signals, and finish the image display of the display panel.
The invention realizes the communication connection with the first memory 20 and the second memory 30 through the same serial communication bus by arranging the memory switch control circuit 40, the time schedule controller 10, the first memory 20 and the second memory 30. The memory switch control circuit 40 is arranged between the chip selection pin of the first memory 20 and the time schedule controller 10 in series, the memory switch control circuit 40 is controlled based on the chip selection signal of the time schedule control circuit, and when the time schedule controller 10 controls the memory switch control circuit 40 to be closed, the communication connection between the time schedule controller 10 and the first memory 20 is realized, so that the time schedule controller 10 reads the software data of the first memory 20, and the initial setting of the time schedule controller 10 is further completed. When the timing controller 10 controls the memory switch control circuit 40 to be turned on, the communication connection between the timing controller 10 and the second memory 30 is realized, so that the timing controller 10 can read the software data of the second memory 30. The invention solves the problems that the whole driving framework of the display panel can not be subjected to small packaging, and the size is large and the cost is high because the time schedule controller 10 needs to realize communication connection with different memories by arranging a plurality of groups of serial communication buses.
Meanwhile, the present invention also solves the problem that when the timing controller 10 reads the data of the first memory 20, the data of the second memory 30 may enter the timing controller 10, which results in the failure of the timing controller 10 to read the data of the first memory 20, or when the data of the second memory 30 is read, the data of the first memory 20 enters the timing controller 10 in series, and the data of the second memory 30 is read by the timing controller 10. The invention also effectively solves the problem of error reading of the software of the time schedule controller 10 when the same serial communication bus is adopted to connect the memory, and improves the reliability of the display device.
Referring to fig. 1 to 3, in an embodiment, the timing controller 10 is further configured to output a third chip select signal to control the first memory 20 to stop operating, and control the memory switch control circuit 40 to turn off to control the second memory 30 to stop operating.
In this embodiment, after the timing controller 10 sequentially reads the data of the first memory 20 and the data of the second memory 30, and completes the power-on initialization, the timing controller 10 outputs a third chip select signal, i.e., a high-impedance signal, so that the chip select pin of the first memory 20 is in a high-impedance state, and the memory switch control circuit 40 is not turned on under the high-impedance signal, so that the input of the chip select pin of the second memory 30 is a high level and is not selected.
Referring to fig. 1 and 2, in an alternative embodiment, the memory switch control circuit 40 includes a first switch tube Q1 and a pull-up resistor R1, the controlled terminal of the first switch tube Q1 is the controlled terminal of the memory switch circuit, the first terminal of the first switch tube Q1 is grounded, and the second terminal of the first switch tube Q1 is the chip select signal output terminal of the memory switch control circuit 40 and is connected to a first dc power supply through the pull-up resistor R1.
In this embodiment, the first switch tube Q1 may be implemented by a switch tube such as a triode, an MOS tube, or the like, and this embodiment may be implemented by an N-MOS tube. The first resistor R1 is a pull-up resistor R1, and is used for outputting a low-high level chip selection signal to the second memory 30, so that the second memory 30 is not selected and is in a state of stopping operation. When the display device is powered on, the memory switch control circuit 40 does not operate when the timing controller 10 outputs the first chip select signal of low level, so that the N-MOS transistor is kept in an off state, at this time, the first resistor outputs the high level of the first dc power supply to the second memory 30, so that the second memory 30 is in an off state, and when the second timing controller 10 outputs the second chip select signal of high level, the N-MOS transistor is turned on, and outputs the low level to the second memory 30, so that the second memory 30 is selected. When the initialization is finished and the display device enters a normal working state, the timing controller 10 outputs a third chip selection signal to control the N-MOS transistor to be turned off, so that the first resistor R1 outputs a low-high level chip selection signal to the second memory 30, and the second memory 30 is in a non-selected state but in a state of stopping working.
The invention also provides a driving circuit of the display panel.
Referring to fig. 1 to 3, the driving circuit of the display panel includes:
a timing controller 10 configured to output a first chip select signal, a second chip select signal, and a third chip select signal;
a first memory 20 configured to store initialization software data of the display panel;
a second memory 30 configured to store optically compensated software data;
the data transmission terminals of the first memory 20 and the second memory 30 are both connected with the data transmission terminal of the timing controller 10; the first memory 20 is further configured to be selected when receiving the first chip select signal, and the timing controller 10 is provided to read the stored initialization software data of the display panel;
the memory switch control circuit 40 comprises a controlled end and a control signal output end, wherein the controlled end is connected with a chip selection signal output end of the time schedule controller 10, and the control signal output end is connected with a chip selection pin of the second memory 30; the memory switch control circuit 40 is configured to be turned on when receiving the second chip select signal to control the second memory 30 to be selected, and the timing controller 10 is provided for reading the stored optical compensation software data;
the timing controller 10 is further configured to output a third chip select signal to control the first memory 20 to stop being selected, and control the memory switch control circuit 40 to turn off to control the second memory 30 to stop being selected.
The specific selected process of the first storage 20 and the second storage 30 is as follows:
after the timing controller 10 is powered on to work, the first chip select signal is output to control the first memory 20 to be selected, after the timing controller 10 is set up in the SCLK, the first memory 20 is read by an MOSI (SI) instruction and an address to start reading, and then the timing controller 10 starts to read the initialization code stored in the first memory 20, namely the initialization software data of the display panel;
after the timing sequence controller 10 is powered on and initialized, the second chip selection signal is output, the memory switch control circuit 40 is controlled to be switched on to control the second memory 30 to be selected, the timing sequence controller 10 sends a reading instruction and a reading starting address to the second memory 30 through an MOSI (SI), and then the timing sequence controller 10 starts to read the optical compensation software data stored in the second memory 30 from the second memory 30, namely, reads the demura table until the reading is completed.
And after the initialized parameters and the demura table are read for initialization, outputting the third chip selection signal, controlling the first memory 20 to stop being selected, and controlling the memory switch control circuit 40 to be switched off so as to control the second memory 30 not to be selected.
After the timing controller 10 finishes reading the initialization codes in the first memory 20 and the second memory 30, the timing controller 10 releases the SPI bus, the output chip select signal CS is the high-impedance signal Hi-Z, the first memory 20 is not selected, and at this time, the chip select signal of the second memory 30 is also pulled to the high level H due to the pull-up resistor R1, so the second memory 30 is not selected, and the codes in the memories are prevented from being rewritten.
Referring to fig. 3, in an embodiment, the driving circuit of the display panel further includes a gamma circuit 80 configured to generate a plurality of gamma voltages and output the gamma voltages to the source driver 40, and the source driver 40 controls the pixels corresponding to the tfts to be charged according to the timing control signal and the gamma voltages output by the timing controller 10, so that the source driver 40 outputs the data signals to the corresponding pixels to display the image to be displayed. The gamma circuit 80 may be implemented by a programmable gamma chip or by discrete components such as resistor string, memory, etc., and may generate a set of gamma voltages (V) γ1 ～V γ14 ) Can be used as the pixel gray scale reference voltage. The gate driver 20 outputs scan signals line by line to drive the thin film transistors to be turned on line by line, upon receiving gate driving signals, i.e., a frame Start Signal (STV), a scan Clock signal (CPV), and an Enable signal (Output Enable, OE), which are outputted from the timing controller 10.
The invention further provides a display device, which comprises a display panel and the display panel driving circuit, wherein the gate driving circuit and the source driving circuit of the display panel are respectively electrically connected with the display panel. The detailed structure of the display panel driving circuit can refer to the above embodiments, and is not described herein again; it can be understood that, since the display device of the present invention uses the display panel driving circuit, the embodiment of the display device of the present invention includes all technical solutions of all embodiments of the display panel driving circuit, and the achieved technical effects are also completely the same, and are not described herein again.
In this embodiment, the display device may be a display device having a display panel, such as a television, a tablet computer, or a mobile phone. The display device also comprises a time sequence control board and a source electrode printed circuit board; the Display panel 100 may be an OLED (Organic Light-Emitting Diode) Display panel 100, or may be a TFT-LCD (Thin Film Transistor Liquid Crystal Display) Display panel 100.
Referring to fig. 4, in an embodiment, the display panel 100 includes:
a pixel array 150;
an array substrate 140;
the liquid crystal layer 160 is arranged between the array substrate 140 and the color film substrate 180, the liquid crystal layer 160 includes a plurality of liquid crystal molecules, and the pixel array 150 is used for controlling the actions of the plurality of liquid crystal molecules;
a plurality of scan lines (G1, G2, G3 8230Gn) disposed on the array substrate 140;
a plurality of data lines (D1, D2, D3 8230Dn) disposed on the array substrate 140;
in this embodiment, the array substrate 140 and the color filter substrate 180 are both transparent substrates such as glass substrates or plastic substrates. The color filter substrate 180 is disposed opposite to the array substrate 140, and a corresponding circuit may be disposed between the array substrate 140 and the color filter substrate 180. The pixel array 150 is disposed on the array substrate 140.
In the above embodiment, the pixel array 150 includes a plurality of sub-pixels, each of which includes an active switch (thin film transistor) and a pixel electrode, a gate of the active switch is electrically connected to the scan line corresponding to the sub-pixel, a source of the active switch is electrically connected to the data line corresponding to the pixel unit 130, and a drain of the active switch is electrically connected to the pixel electrode of the sub-pixel. Pixel array 150 also includes an array of pixel electrodes connected to the array of active switching elements.
The display panel 100 is composed of a plurality of pixels, each of which is composed of three sub-pixels of red, green and blue. Each sub-pixel circuit structure is generally provided with a thin film transistor and a capacitor, the gate of the thin film transistor is connected to the gate driver 50 through a scan line, the source of the thin film transistor is connected to the source driver 60 through a data line, and the drain of the thin film transistor is connected to one end of the capacitor. Wherein the plurality of thin film transistors form a thin film transistor array (not shown). The tfts in the same column are connected to the source driver 60 through a data line, and the tfts in the same row are connected to the gate driver 50 through a scan line, thereby forming a tft array. These thin film transistors may be a-Si (non-Silicon) thin film transistors or Poly-Si (polysilicon) thin film transistors, which may be formed using LTPS (Low Temperature polysilicon) or the like.
It can be understood that, in the above embodiment, the display panel 100 further includes the sealant 170 disposed in the non-display area BB between the array substrate 140 and the color film substrate 180 and surrounding the liquid crystal layer 160, and the GOA circuit 100 is located between the sealant 170 and the display area AA. The sealant 170 may be coated on the array substrate 140 or the color film substrate 180 by using a sealant to connect the array substrate 140 and the color film substrate 180, so as to implement the assembling process of the display panel 100. Specifically, the pixel array 150 is a pixel array 150 of a Half Source Driving (HSD) architecture.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A driving circuit of a display panel, the driving circuit of the display panel comprising:
a timing controller configured to output a first chip select signal and a second chip select signal;
the data transmission ends of the first memory and the second memory are connected with the data transmission end of the time schedule controller; the first memory is configured to work when receiving a first chip selection signal and is used for the time schedule controller to read stored software data;
the memory switch control circuit comprises a controlled end and a control signal output end, wherein the controlled end is connected with a chip selection signal output end of the time schedule controller, and the control signal output end is connected with a chip selection pin of the second memory; the memory switch control circuit is configured to be turned on when receiving the second chip selection signal and output a chip selection signal for controlling the second memory to work to the second memory so that the timing controller can read stored software data;
the memory switch control circuit comprises a first switch tube and a pull-up resistor, wherein the controlled end of the first switch tube is the controlled end of the memory switch circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is the chip selection signal output end of the memory switch control circuit and is connected with a first direct current power supply through the pull-up resistor.
2. The driving circuit of the display panel according to claim 1, wherein the timing controller is further configured to output a third chip select signal to control the first memory to stop operating, and to control the memory control switch circuit to turn off and output a chip select signal to control the second memory to operate to control the second memory to stop operating.
3. The driving circuit of a display panel according to claim 1, wherein the software data stored in the first memory is initialization software data of the display panel;
the software data stored in the second memory is optical compensation software data.
4. The driving circuit of claim 1, wherein the driving circuit of the display panel further comprises a serial communication bus, and the timing controller is connected to the first memory and the second memory through the serial communication bus.
5. The driving circuit of a display panel according to any one of claims 1 to 4, wherein the driving circuit of a display panel further comprises a gate driving circuit and a source driving circuit, and controlled terminals of the gate driving circuit and the source driving circuit are respectively connected with an output terminal of the timing controller.
6. A driving circuit of a display panel, the driving circuit comprising:
a timing controller configured to output a first chip selection signal, a second chip selection signal, and a third chip selection signal;
a first memory configured to store initialization software data of the display panel;
a second memory configured to store optically compensated software data;
the data transmission ends of the first memory and the second memory are both connected with the data transmission end of the time sequence controller; the first memory is also configured to work when receiving a first chip selection signal, and the stored initialization software data of the display panel is read by the time schedule controller;
the memory switch control circuit comprises a controlled end and a control signal output end, wherein the controlled end is connected with a chip selection signal output end of the time schedule controller, and the control signal output end is connected with a chip selection pin of the second memory; the memory switch control circuit is configured to be switched on when receiving the second chip selection signal so as to control the second memory to work, and the stored optical compensation software data is read by the time schedule controller;
the time schedule controller is also configured to output a third chip selection signal to control the first memory to stop working and control the memory control switch circuit to be switched off to control the second memory to stop working;
the memory switch control circuit comprises a first switch tube and a pull-up resistor, the controlled end of the first switch tube is the controlled end of the memory switch circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is the chip selection signal output end of the memory switch control circuit and is connected with a first direct current power supply through the pull-up resistor.
7. The driving circuit of the display panel according to claim 6, wherein the specific operation process of the timing controller is as follows:
outputting the first chip selection signal, controlling the first memory to work, and reading the initialization software data of the display panel stored in the first memory;
outputting the second chip selection signal, controlling the on-off of the memory switch control circuit to control the second memory to work, and reading the optical compensation software data stored in the second memory by the time sequence controller after the second memory works;
and outputting the third chip selection signal to control the first memory to stop working, and controlling the memory switch control circuit to be switched off so as to control the second memory to stop working.
8. A display device comprising a display panel and a driver circuit of the display panel according to any one of claims 1 to 5; or, a driving circuit including the display panel according to any one of claims 6 and 7, the gate driving circuit and the source driving circuit of the display panel being electrically connected to the display panel, respectively.
9. The display device according to claim 8, further comprising a timing control board and a source driving printed circuit board;
the time sequence controller and the first memory of the driving circuit of the display panel are arranged on the time sequence control board;
and the second memory of the driving circuit of the display panel is arranged on the source electrode driving printed circuit board.
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| CN110930924A (en) * | 2019-11-28 | 2020-03-27 | Tcl华星光电技术有限公司 | Driving circuit |
| CN111028799B (en) * | 2019-12-10 | 2021-09-03 | Tcl华星光电技术有限公司 | Driving circuit and driving method of display panel |
| CN111063314A (en) * | 2019-12-25 | 2020-04-24 | Tcl华星光电技术有限公司 | Display device |
| CN112860125B (en) * | 2021-03-19 | 2024-04-16 | 京东方科技集团股份有限公司 | Touch display driving device and method and touch display device |
| CN113763884A (en) * | 2021-09-18 | 2021-12-07 | 京东方科技集团股份有限公司 | Data connector, data providing module, method and display device |
| CN114078416B (en) * | 2021-11-23 | 2023-12-29 | 京东方科技集团股份有限公司 | Time sequence control circuit, display module and display device |
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