CN107170415A - Horizontal substrate and control panel merge the LCD and its mura repairing control methods of framework - Google Patents
Horizontal substrate and control panel merge the LCD and its mura repairing control methods of framework Download PDFInfo
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- CN107170415A CN107170415A CN201710327646.4A CN201710327646A CN107170415A CN 107170415 A CN107170415 A CN 107170415A CN 201710327646 A CN201710327646 A CN 201710327646A CN 107170415 A CN107170415 A CN 107170415A
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- mura
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- flash memory
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- secondary signal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides the LCD and its mura repairing control methods that a kind of horizontal substrate and control panel merge framework.The repairing control method includes：Step 10, the first signal and secondary signal are high level, read flash memory；Step 20, the first signal are low level, wipe flash memory；Step 30, the first signal become high level, and secondary signal is changed into recovering high level again after low level, and timing controller is reconnected with flash memory；Step 40, the first signal and secondary signal are high level, carry out original mura image takings and offset data is calculated；Step 50, first signal are changed into low level, and new mura offset datas are write into flash memory；Step 60, the first signal revert to high level, and secondary signal is changed into reverting to high level again after low level, and display panel is shown as correct repair efficiency.The panel of the present invention can increase the utilization rate of pcb board, and repairing control method enables panel to complete to automate mending course.
Description
Technical field
Merge the LCD of framework the present invention relates to field of liquid crystal, more particularly to a kind of horizontal substrate and control panel
And its mura repairing control methods.
Background technology
The flat display apparatus such as liquid crystal display (LCD) are because thin and have a wide range of application etc. excellent with high image quality, power saving, fuselage
Point, and it is each to be widely used in mobile phone, TV, personal digital assistant, digital camera, notebook computer, desktop computer etc.
Consumption electronic products are planted, as the main flow in display device.
As shown in figure 1, it is general LCD configuration diagram.CB (control in general LCD framework
Board, control panel) 11, XB (X-board, horizontal substrate) 12, the three of glass 13 separation, pass through flexible flat cable (FFC) wire rod
14 connections；Because mura (brightness unevenness) situation of every panel is different, mura offset datas are individually stored in be connected with glass 13
In flash memory (flash) 15 on the horizontal substrate 12 connect, and the driving code (code) of timing controller (TCON IC) 16 is deposited
(control panel isolated operation in the case where being not connected to horizontal substrate/glass is set to produce letter in flash memory 17 on control panel 11
Number, it is easy to test).
As shown in Fig. 2 it is general LCD mura repairing Automated condtrol timing diagrams, explanation is combined with Fig. 1 below
Mura repairs Automated condtrol process., can be in SECO core in the acquisition of mura offset datas and storing process is carried out
In the case that piece 16 is connected with the flash memory 17 on control panel 11, data erasing is carried out to the flash memory 15 on horizontal substrate and write-in is dynamic
Make, mura repairs Automated condtrol sequential as shown in Fig. 2 being mainly controlled by two signals of SPI_EN and RSTI, works as SPI_
When EN is low level (0V), SPI (Serial Peripheral Interface (SPI)) circuit on timing controller 16 and horizontal substrate 12 between flash memory 15
(the chip end interface of timing controller 16 is changed into high impedance status, no longer controls the flash memory on horizontal substrate 12 for 18 connection disconnections
15), the flash memory 15 of horizontal substrate 12 can be carried out to wipe/data write activity, when RSTI is low level, timing controller 16
All control interfaces all no longer work, i.e., SPI circuits now on timing controller 16 and control panel 11 between flash memory 17
19 connections are also disconnected, and after RSTI recovers high level, timing controller 16 is connected with the flash memory 17 of control panel 11 again, if this
When SPI_EN still be low level, then timing controller 16 can not read the data of flash memory 15 on horizontal substrate 12, then panel show
Normal mura reset conditions are shown as, the shooting and data that can proceed by original mura pictures are calculated, the sudden strain of a muscle of horizontal substrate 12
The erasing move for depositing 15 can also be while carry out, with the time for the mura mending courses for saving every panel.
The content of the invention
It is an object of the invention to provide the LCD that a kind of horizontal substrate and control panel merge framework, increase the profit of pcb board
With rate.
A further object of the present invention is to merge the LCD of framework for horizontal substrate and control panel that there is provided arrange in pairs or groups therewith
Mura repairing control method.
To achieve the above object, the invention provides the LCD that a kind of horizontal substrate and control panel merge framework, including by
The pcb board that control panel and at least one horizontal substrate merge；The pcb board is provided with timing controller and passes through SPI circuits
The driving code of the flash memory being connected with the timing controller, mura offset datas and the timing controller is stored in this
In flash memory；The timing controller is provided with the first port for receiving the first signal and the second end for receiving secondary signal
Mouthful, first signal is used to control the SPI connection break-makes between the timing controller and the flash memory, and the secondary signal is used
In the connection break-make for controlling the timing controller and outside all circuits.
Wherein, the mura repairings automation of the LCD is by controlling the sequential of first signal and secondary signal come real
It is existing.
Wherein, first signal and the high level of secondary signal are 3.3 volts.
Wherein, the low level of first signal and secondary signal is 0 volt.
Control method is repaired the invention provides a kind of mura for above-mentioned LCD, including：
Step 10, first signal and secondary signal are high level, and timing controller reads the driving generation in flash memory
Code and old mura offset datas；
Step 20, first signal are low level, and secondary signal still keeps high level, to storing mura compensation numbers in flash memory
According to position wiped；
Step 30, first signal become high level, and secondary signal is changed into recovering high level, sequential control again after low level
Coremaking piece reconnects with flash memory and reads driving code；
Step 40, first signal and secondary signal are high level, and display panel is shown as original mura states, opened
Begin to carry out original mura image takings and offset data is calculated；
Step 50, first signal are changed into low level, and timing controller is disconnected with flash memory, and new mura is compensated
Data are written in flash memory；
Step 60, first signal revert to high level, and secondary signal is changed into reverting to high level again after low level, when
Sequence control chip reconnects with flash memory and reads driving code and new mura offset datas, and display panel is shown as correct
Mura repair efficiencies.
Wherein, first signal and the high level of secondary signal are 3.3 volts.
Wherein, the low level of first signal and secondary signal is 0 volt.
Control method is repaired present invention also offers a kind of mura for above-mentioned LCD, including：
Step 101, the secondary signal are high level, and timing controller reads driving code and old mura in flash memory
Offset data；
Step 201, the secondary signal are changed into low level, and the position that mura offset datas are stored in flash memory is wiped；
Step 301, the secondary signal recover high level, and timing controller is reconnected with flash memory and read driving generation
Code；
Step 401, the secondary signal keep high level, and display panel is shown as original mura states, proceeds by original
Beginning mura image taking and offset data are calculated；
Step 501, the secondary signal are changed into low level, and timing controller is disconnected with flash memory, and new mura is mended
Data are repaid to be written in flash memory；
Step 601, the secondary signal revert to high level, and timing controller is reconnected with flash memory and read driving generation
Code and new mura offset datas, display panel are shown as correct mura repair efficiencies.
Wherein, first signal remains low level.
To sum up, the LCD of horizontal substrate of the invention and control panel merging framework can increase the utilization rate of pcb board, together
When can also reduce the use of a flash memory；The horizontal substrate and control panel of the present invention merge the mura repairings of the LCD of framework
Control method, enables the LCD of merging framework to complete to automate mura mending courses.
Brief description of the drawings
Below in conjunction with the accompanying drawings, it is described in detail by the embodiment to the present invention, technical scheme will be made
And other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is existing LCD configuration diagram；
Fig. 2 is that existing LCD mura repairs Automated condtrol timing diagram；
Fig. 3 merges the structural representation of the preferred embodiment of LCD one of framework for horizontal substrate and control panel of the invention；
Fig. 4 merges the timing diagram of the mura repairing control methods of the LCD of framework for horizontal substrate and control panel of the invention；
Fig. 5 merge for horizontal substrate and control panel of the invention the mura repairing control methods of the LCD of framework it is another when
Sequence figure；
Fig. 6 merges the flow chart of the mura repairing control methods of the LCD of framework for horizontal substrate and control panel of the invention；
Fig. 7 merges the another stream of the mura repairing control methods of the LCD of framework for horizontal substrate and control panel of the invention
Cheng Tu.
Embodiment
As shown in figure 3, the structure of its preferred embodiment of LCD one for merging framework for horizontal substrate and control panel of the invention
Schematic diagram.Merging the LCD of framework mainly includes：Pcb board (merged by original horizontal substrate and control panel and formed) 31, it is horizontal
Substrate 32, is connected between pcb board 31 and horizontal substrate 32 by FFC wire rods 34, pcb board 31 provided with timing controller 36 and
Storage driving code and the flash memory of mura offset datas 35, timing controller 36 and flash memory 35 are connected by SPI circuits 38；When
Sequence control chip 36 is still subjected to two signals of SPI_EN and RSTI and is controlled, and SPI_EN signals are only used for control sequential control
SPI connections between chip 36 and a certain flash memory (being flash memory 35 in this embodiment), and RSTI signals can be with control sequential
The connection of control chip 36 and outside all circuits.(an at least XB and CB merge same for XB+CB merging proposed by the present invention
On pcb board) framework can increase the utilization rate of pcb board, while the use of a flash memory can also be reduced, i.e., by SECO core
The driving code and mura offset datas of piece are placed on the diverse location in same flash memory.
This XB+CB merges under framework, and the mura repairing Automated condtrol sequential in original Fig. 2 is no longer applicable, and works as SPI_EN
During for low level (low), during carrying out erasing move to flash memory 35, timing controller 36 all the time with this single flash memory 35
Connection disconnects, and timing controller 36 can not read the driving code stored in this flash memory 35, and panel can not normally show
Show, i.e. flash memory erasing can not be carried out simultaneously with mura shootings/data calculating action, in order to realize the automation control of mura repairings
System, control sequential must be redesigned.
The present invention merges the LCD of framework, i.e. timing controller driving code and mura offset datas for XB+CB
In the case of being stored in same flash memory, the mura repairing Automated condtrol sequential arranged in pairs or groups therewith is devised.Referring to Fig. 4 and Fig. 6,
Fig. 6 merges the flow chart of the mura repairing control methods of the LCD of framework for horizontal substrate and control panel of the invention, can combine figure
4 are understood, Fig. 4 show the control sequential of redesign, SPI_EN and RSTI signals are divided into 6 stage controls, and respectively
The step 10 of control method, 20,30,40,50,60 are repaired corresponding to mura：
Step 10, first signal and secondary signal are high level, and timing controller reads the driving generation in flash memory
Code and old mura offset datas；
Step 20, first signal are low level, and secondary signal still keeps high level, to storing mura compensation numbers in flash memory
According to position wiped；
Step 30, first signal become high level, and secondary signal is changed into recovering high level, sequential control again after low level
Coremaking piece reconnects with flash memory and reads driving code；
Step 40, first signal and secondary signal are high level, and display panel is shown as original mura states, opened
Begin to carry out original mura image takings and offset data is calculated；
Step 50, first signal are changed into low level, and timing controller is disconnected with flash memory, and new mura is compensated
Data are written in flash memory；
Step 60, first signal revert to high level, and secondary signal is changed into reverting to high level again after low level, when
Sequence control chip reconnects with flash memory and reads driving code and new mura offset datas, and display panel is shown as correct
Mura repair efficiencies.
First stage：First signal SPI_EN and secondary signal RSTI are high level (3.3V), and LCD is lighted, this
When timing controller read driving code in flash memory and old mura offset datas or there is no mura offset datas；
Second stage：No matter the mura offset datas whether haveing been friends in the past in flash memory, before new mura offset datas are write
Have to carry out erasing move, to ensure the accuracy after new data write-in；Change after being shown in order to avoid old mura offset datas
Original mura state is become, erasing move has been placed on before the original mura images of shooting, now SPI_EN is low level, to dodging
The position for depositing middle storage mura offset datas carries out erasing move, and the now connection between timing controller and flash memory disconnects,
Before erasing move completion, RSTI signals still keep high level；
Phase III：After erasing move is completed, SPI_EN becomes high level, while RSTI is changed into extensive again after low level
Multiple high level, timing controller reconnects with flash memory and reads driving code, due to mura offset datas storage location
Through being wiped free of, so LCD is necessarily shown as original mura states；Old mura offset datas are stored if having in flash memory,
And timing controller does not re-read data this process in flash memory, then LCD can show old mura compensation always
Mura states after compensation data, it is impossible to carry out fourth stage；
Fourth stage：SPI_EN and RSTI are high level, and LCD is shown as original mura states, proceeded by
Original mura image takings and offset data are calculated；
5th stage：SPI_EN is changed into low level, and timing controller is disconnected with flash memory, and mura patch systems will be new
Mura offset datas be written in flash memory；
6th stage：After the completion of the write-in of mura offset datas, SPI_EN reverts to high level, while RSTI is changed into low level
Revert to high level again afterwards, timing controller reconnects with flash memory and reads driving code and new mura compensation numbers
According to LCD is shown as correct mura repair efficiencies.
Referring to Fig. 5, it merges the mura repairing control methods of the LCD of framework for horizontal substrate and control panel of the invention
Another timing diagram.Referring to Fig. 7, it merges the mura repairing controlling parties of the LCD of framework for horizontal substrate and control panel of the invention
The another flow chart of method, can be understood with reference to Fig. 5.Dodged because SPI_EN signals are only used for control sequential control chip with a certain
SPI connections between depositing, and RSTI signals can be with the connection of control sequential control chip and outside all circuits, i.e. RSTI
Signal contains the function of SPI_EN signals, therefore timing Design shown in Fig. 4 can be reduced to the single RSTI signals shown in Fig. 5
Control sequential, now SPI_EN is preferably low level；When RSTI signals are low level, between timing controller and flash memory
Connection is also at off-state, when RSTI signals recover high level, is connected between timing controller and flash memory, and read again
Take the driving code and mura offset datas in flash memory.Now mura repairs control method and also corresponds to 6 stages, including：
Step 101, the secondary signal are high level, and timing controller reads driving code and old mura in flash memory
Offset data；
Step 201, the secondary signal are changed into low level, and the position that mura offset datas are stored in flash memory is wiped；
Step 301, the secondary signal recover high level, and timing controller is reconnected with flash memory and read driving generation
Code；
Step 401, the secondary signal keep high level, and display panel is shown as original mura states, proceeds by original
Beginning mura image taking and offset data are calculated；
Step 501, the secondary signal are changed into low level, and timing controller is disconnected with flash memory, and new mura is mended
Data are repaid to be written in flash memory；
Step 601, the secondary signal revert to high level, and timing controller is reconnected with flash memory and read driving generation
Code and new mura offset datas, display panel are shown as correct mura repair efficiencies.
To sum up, the LCD of horizontal substrate of the invention and control panel merging framework can increase the utilization rate of pcb board, together
When can also reduce the use of a flash memory；The horizontal substrate and control panel of the present invention merge the mura repairings of the LCD of framework
Control method, enables the LCD of merging framework to complete to automate mura mending courses.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to appended right of the invention
It is required that protection domain.
Claims (9)
1. a kind of horizontal substrate and control panel merge the LCD of framework, it is characterised in that including by control panel and at least one horizontal base
The pcb board that plate merges；The pcb board connects provided with timing controller and by SPI circuits and the timing controller
The driving code of the flash memory connect, mura offset datas and the timing controller is stored in the flash memory；The SECO
Chip is provided with the first port for receiving the first signal and the second port for receiving secondary signal, and first signal is used for
The SPI connection break-makes between the timing controller and the flash memory are controlled, the secondary signal is used to control the SECO
The connection break-make of chip and outside all circuits.
2. horizontal substrate and control panel as claimed in claim 1 merge the LCD of framework, it is characterised in that the LCD
Mura repairing automations are by controlling the sequential of first signal and secondary signal to realize.
3. horizontal substrate and control panel as claimed in claim 1 merge the LCD of framework, it is characterised in that first signal
High level with secondary signal is 3.3 volts.
4. horizontal substrate and control panel as claimed in claim 1 merge the LCD of framework, it is characterised in that first signal
Low level with secondary signal is 0 volt.
5. a kind of mura repairing control methods of LCD as claimed in claim 1, it is characterised in that including：
Step 10, first signal and secondary signal are high level, timing controller read driving code in flash memory and
Old mura offset datas；
Step 20, first signal are low level, and secondary signal still keeps high level, to storing mura offset datas in flash memory
Wiped position；
Step 30, first signal become high level, and secondary signal is changed into recovering high level, SECO core again after low level
Piece reconnects with flash memory and reads driving code；
Step 40, first signal and secondary signal are high level, and display panel is shown as original mura states, start into
The original mura image takings of row and offset data are calculated；
Step 50, first signal are changed into low level, and timing controller is disconnected with flash memory, by new mura offset datas
It is written in flash memory；
Step 60, first signal revert to high level, and secondary signal is changed into reverting to high level, sequential control again after low level
Coremaking piece reconnects with flash memory and reads driving code and new mura offset datas, and display panel is shown as correct mura
Repair efficiency.
6. the mura repairing control methods of LCD as claimed in claim 5, it is characterised in that first signal and second
The high level of signal is 3.3 volts.
7. the mura repairing control methods of LCD as claimed in claim 5, it is characterised in that first signal and second
The low level of signal is 0 volt.
8. a kind of mura repairing control methods of LCD as claimed in claim 1, it is characterised in that including：
Step 101, the secondary signal are high level, and timing controller reads driving code and old mura compensation in flash memory
Data；
Step 201, the secondary signal are changed into low level, and the position that mura offset datas are stored in flash memory is wiped；
Step 301, the secondary signal recover high level, and timing controller reconnects with flash memory and reads driving code；
Step 401, the secondary signal keep high level, and display panel is shown as original mura states, proceeded by original
Mura image takings and offset data are calculated；
Step 501, the secondary signal are changed into low level, and timing controller is disconnected with flash memory, and new mura is compensated into number
According to being written in flash memory；
Step 601, the secondary signal revert to high level, timing controller is reconnected with flash memory and read drive code and
New mura offset datas, display panel is shown as correct mura repair efficiencies.
9. the mura repairing control methods of LCD as claimed in claim 8, it is characterised in that first signal is remained
Low level.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710327646.4A CN107170415B (en) | 2017-05-10 | 2017-05-10 | Horizontal substrate and control panel merge the LCD panel of framework and its mura repairs control method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710327646.4A CN107170415B (en) | 2017-05-10 | 2017-05-10 | Horizontal substrate and control panel merge the LCD panel of framework and its mura repairs control method |
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| CN107170415B CN107170415B (en) | 2019-09-10 |
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| CN108109573A (en) * | 2017-12-06 | 2018-06-01 | 深圳市华星光电半导体显示技术有限公司 | The update method of the Mura offset datas of display panel |
| CN109389959A (en) * | 2018-12-12 | 2019-02-26 | 惠科股份有限公司 | The driving framework and method of display panel |
| CN110428767A (en) * | 2019-06-27 | 2019-11-08 | 重庆惠科金渝光电科技有限公司 | The driving circuit and display device of display panel |
| CN111063314A (en) * | 2019-12-25 | 2020-04-24 | Tcl华星光电技术有限公司 | Display device |
| CN111312151A (en) * | 2020-04-03 | 2020-06-19 | Tcl华星光电技术有限公司 | Display panel compensation circuit structure and display device |
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| CN111599307A (en) * | 2020-06-09 | 2020-08-28 | 北京交通大学 | Pixel compensation method of OLED display panel and information processing device |
| CN111724749A (en) * | 2019-03-19 | 2020-09-29 | 咸阳彩虹光电科技有限公司 | Display driving method, display driving device and display device |
| CN113160769A (en) * | 2021-04-25 | 2021-07-23 | Tcl华星光电技术有限公司 | Driving system and driving method of display panel |
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| CN110428767A (en) * | 2019-06-27 | 2019-11-08 | 重庆惠科金渝光电科技有限公司 | The driving circuit and display device of display panel |
| CN110428767B (en) * | 2019-06-27 | 2023-01-20 | 重庆惠科金渝光电科技有限公司 | Driving circuit of display panel and display device |
| CN111063314A (en) * | 2019-12-25 | 2020-04-24 | Tcl华星光电技术有限公司 | Display device |
| CN111312151A (en) * | 2020-04-03 | 2020-06-19 | Tcl华星光电技术有限公司 | Display panel compensation circuit structure and display device |
| CN111599307A (en) * | 2020-06-09 | 2020-08-28 | 北京交通大学 | Pixel compensation method of OLED display panel and information processing device |
| CN111599307B (en) * | 2020-06-09 | 2021-09-24 | 北京交通大学 | Pixel compensation method of OLED display panel and information processing device |
| WO2022227021A1 (en) * | 2021-04-25 | 2022-11-03 | Tcl华星光电技术有限公司 | Driving system and driving method for display panel |
| CN113160769A (en) * | 2021-04-25 | 2021-07-23 | Tcl华星光电技术有限公司 | Driving system and driving method of display panel |
| CN113327533A (en) * | 2021-05-20 | 2021-08-31 | Tcl华星光电技术有限公司 | Display device compensation data repair method and compensation data repair device |
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| CN107170415B (en) | 2019-09-10 |
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