CN110428767A - Driving circuit of display panel and display device - Google Patents
Driving circuit of display panel and display device Download PDFInfo
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- CN110428767A CN110428767A CN201910573180.5A CN201910573180A CN110428767A CN 110428767 A CN110428767 A CN 110428767A CN 201910573180 A CN201910573180 A CN 201910573180A CN 110428767 A CN110428767 A CN 110428767A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims description 33
- 230000003287 optical effect Effects 0.000 claims description 10
- 230000005055 memory storage Effects 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 description 20
- 239000010409 thin film Substances 0.000 description 15
- 239000012528 membrane Substances 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
- G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a drive circuit of a display panel and a display device, wherein the drive circuit of the display panel comprises a time schedule controller, a first memory and a second memory, and data transmission ends of the first memory and the second memory are connected with the data transmission end of the time schedule controller; the first memory is configured to work when receiving the first chip selection signal and is used for the time schedule controller to read the stored software data; the controlled end of the memory switch control circuit is connected with the chip selection signal output end of the time schedule controller, and the control signal output end is connected with the chip selection pin of the second memory; the memory switch control circuit receives the second chip selection signal to be conducted and outputs the chip selection signal for controlling the second memory to work to the second memory so as to enable the time schedule controller to read the stored software data. The invention solves the problems that the whole driving framework of the display panel can not be packaged in a small way, and has large volume and higher cost.
Description
Technical field
The present invention relates to display actuation techniques field, the in particular to driving circuits and display device of a kind of display panel.
Background technique
In display device, the data in sequence controller TCON IC internal stationary read-only memory SROM are generally in power down
It cannot save later, and (Electrically Erasable Programmable read only memory, can by EEPROM
Erasing memory) or flash memories Flash in the data that store after power down can save, so can be by sequence controller
Program storage is controlled in external memory EEPROM or Flash.In a display device, the quantity more than one of memory, often
A memory require by one group of connection come respectively with sequence controller communication connection.
This entire driving framework that will lead to display panel cannot do small package, and volume is big and higher cost.
Summary of the invention
The main object of the present invention is the driving circuit and display device for proposing a kind of display panel, it is intended to solve display surface
The problem of entire driving framework of plate cannot do small package, and volume is big and higher cost.
To achieve the above object, the present invention proposes a kind of driving circuit of display panel, the driving electricity of the display panel
Road includes:
Sequence controller is configured as the first chip selection signal of output and the second chip selection signal；
The data transmission terminal of first memory and second memory, the first memory and second memory with it is described
The data transmission terminal of sequence controller connects；The first memory is configured to the work when receiving the first chip selection signal, and
The software data of storage are read for the sequence controller；
Storage switch control circuit, including controlled end and control signal output, the controlled end and the timing control
The chip selection signal output end of device processed connects, and the control signal output is connect with the chip select pin of the second memory；It is described
Storage switch control circuit is configured to be connected and export the control second memory receiving second chip selection signal
The chip selection signal of work is to the second memory, so that the sequence controller reads the software data of storage.
Optionally, the sequence controller is additionally configured to output third chip selection signal, to control the first memory
It stops working, and the control memory control switch circuit turns off and exports the piece choosing for controlling the second memory work
Signal is stopped working to the second memory with controlling the second memory.
Optionally, the software data of the first memory storage are the initialization software data of display panel；
The software data of the second memory storage are optical compensation software data.
Optionally, the driving circuit of the display panel further includes serial communication bus, and the sequence controller passes through institute
It states serial communication bus and connects the first memory and the second memory.
Optionally, the storage switch control circuit includes first switch tube and pull-up resistor, the first switch tube
Controlled end be the storage switch circuit controlled end, the first switch tube first end ground connection, the first switch
The second end of pipe is the chip selection signal output end of the storage switch control circuit, and through the pull-up resistor and the first direct current
Power supply connection.
Optionally, the driving circuit of the display panel further includes gate driving circuit and source electrode drive circuit, the grid
The controlled end of pole driving circuit and the source electrode drive circuit is connect with the output end of the sequence controller respectively.
The present invention also proposes that a kind of driving circuit of display panel, the driving circuit of the display panel include:
Sequence controller is configured as output the first chip selection signal, the second chip selection signal, third chip selection signal；
First memory is configured to the initialization software data of storage display panel；
Second memory is configured to storage optical compensation software data；
Data transmission terminal of the data transmission terminal of the first memory and second memory with the sequence controller
Connection；The first memory is additionally configured to the work when receiving the first chip selection signal, and reads for the sequence controller
The initialization software data of the display panel of storage；
Storage switch control circuit, including controlled end and control signal output, the controlled end and the timing control
The chip selection signal output end of device processed connects, and the control signal output is connect with the chip select pin of the second memory；It is described
Storage switch control circuit is configured to receiving the second chip selection signal conducting, to control the second memory work
Make, and reads the optical compensation software data of storage for the sequence controller；
The sequence controller is additionally configured to output third chip selection signal, stops work to control the first memory
Make, and the control memory control switch circuit shutdown, is stopped working with controlling the second memory.
Optionally, the specific work process of the sequence controller are as follows:
First chip selection signal is exported, the first memory work is controlled, and reads the first memory storage
Display panel initialization software data；
Second chip selection signal is exported, the storage switch control circuit conducting is controlled, is deposited with controlling described second
Reservoir work, the sequence controller after second memory work, mend by the optics for reading the second memory storage
Repay software data；
The third chip selection signal is exported, the first memory is controlled and stops working, and the control memory is opened
Control circuit shutdown is closed, is stopped working with controlling the second memory.
The present invention also proposes a kind of display device, the driving circuit including display panel and display panel as described above,
The gate driving circuit and source electrode drive circuit of the display panel are electrically connected with the display panel respectively.
Optionally, the display device further includes timing control plate and source drive printed circuit board；
Sequence controller, the first memory of the driving circuit of the display panel are set on the timing control plate；
The second memory of the driving circuit of the display panel is set on the source drive printed circuit board.
The present invention passes through setting storage switch control circuit, sequence controller, first memory and second memory, and
The communication connection with first memory and second memory is realized by same serial communication bus.And it is opened by the way that memory is arranged
It closes control circuit to be arranged in series between the chip select pin and sequence controller of first memory, storage switch control circuit is based on
The chip selection signal of sequential control circuit controls, and when sequence controller control storage switch control circuit is closed, when realization
Sequence controller and first memory communication connection so that sequence controller reads the software data of first memory, and then are completed
The initial setting up of sequence controller.And when sequence controller control storage switch control circuit is opened, realize timing control
The communication connection of device and second memory, so that sequence controller reads the software data of second memory.The present invention solves
Sequence controller needs to realize the communication connection between different memories by setting multiple groups serial communication bus, cause
The problem of entire driving framework of display panel cannot do small package, and volume is big and higher cost.
Meanwhile this invention also solves sequence controller read first memory data when, the data of second memory
It may scurry into sequence controller, and cause sequence controller to read first memory data failure, or read the second storage
When the data of device, the data of first memory are sealed in sequence controller, and sequence controller reads second memory data and loses
The problem of losing.The present invention also effectively solves when using same serial communication bus connection memory, and sequence controller is soft
The problem of part read error, improves the reliability of display device.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is that the invention shows the functional block diagrams of one embodiment of driving circuit of panel；
Fig. 2 is that the invention shows the electrical block diagrams of one embodiment of driving circuit of panel；
Fig. 3 is that the invention shows the functional block diagrams of another embodiment of the driving circuit of panel；
Fig. 4 is that the invention shows the structural schematic diagrams of one embodiment of panel.
Drawing reference numeral explanation:
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that if relating to directionality instruction (such as up, down, left, right, before and after ...) in the embodiment of the present invention,
Then directionality instruction be only used for explain under a certain particular pose (as shown in the picture) between each component relative positional relationship,
Motion conditions etc., if the particular pose changes, directionality instruction is also correspondingly changed correspondingly.
In addition, being somebody's turn to do " first ", " second " etc. if relating to the description of " first ", " second " etc. in the embodiment of the present invention
Description be used for description purposes only, be not understood to indicate or imply its relative importance or implicitly indicate indicated skill
The quantity of art feature." first " is defined as a result, the feature of " second " can explicitly or implicitly include at least one spy
Sign.It in addition, the technical solution between each embodiment can be combined with each other, but must be with those of ordinary skill in the art's energy
It is enough realize based on, will be understood that the knot of this technical solution when conflicting or cannot achieve when occurs in the combination of technical solution
Conjunction is not present, also not the present invention claims protection scope within.
The present invention proposes a kind of driving circuit of display panel.
Referring to figs. 1 to Fig. 3, in an embodiment of the present invention, the driving circuit of the display panel includes:
Sequence controller 10 is configured as the first chip selection signal of output and the second chip selection signal；
First memory 20 and second memory 30, the data transmission terminal of the first memory 20 and second memory 30
It is connect with the data transmission terminal of the sequence controller 10；The first memory 20 is configured to receiving first choosing
It works when signal, and reads the software data of storage for the sequence controller 10；
Storage switch control circuit 40, including controlled end and control signal output, the controlled end and the timing
The chip selection signal output end of controller 10 connects, and the chip select pin of the control signal output and the second memory 30 connects
It connects；The storage switch control circuit 40 is configured to receiving the second chip selection signal conducting, to control described second
Memory 30 works, and the software data of storage are read for the sequence controller 10.
Referring to Fig. 3, in the present embodiment, the driving circuit of the display panel further includes that gate driving circuit 50 and source electrode drive
The controlled end of dynamic circuit 60, the gate driving circuit 50 and the source electrode drive circuit 60 respectively with the sequence controller 10
Output end connection.Sequence controller 10 generates driving gate driving circuit 50 and source drive according to the display data received
The timing control signal that circuit 60 works, so that gate driving circuit 50 drives the master of corresponding scan line connection in display panel
Dynamic switch conduction, and export source electrode drive circuit 60 to display panel to data-signal what is received, to drive display
Panel work.
First memory 20 and second memory 30 can use EEPROM (Electrically Erasable
Programmable read only memory, erasable memory) or flash memories Flash realize.Wherein, the first storage
Device 20 and sequence controller 10 can be set on timing control (Timing Controller, TCON) pcb board, and first deposits
Reservoir 20 can store the control signal for driving grid-driving integrated circuit and source electrode driven integrated circuit to work, and pass through
Serial communication bus and 10 communication connection of sequence controller, on the display apparatus when electricity work, sequence controller 10 reads first
Control signal and other setting data in memory 20 carry out initial setting up, to generate corresponding timing control signal, thus
Drive source electrode driven integrated circuit and the grid-driving integrated circuit work namely described first of the display panel in display device
The software data that memory 20 stores are the initialization software data of display panel；The data of first memory 20 are in display device
It cannot be modified when normal work, once by modifying, so that setting corrupt data, it is abnormal to will lead to display device display.
Therefore, setting write-protect pin (WP pin) mostly of first memory 20, and in input high level, it can control the first storage
Data are written in device 20, and in low level, data cannot be written, first memory 20 only reads number for sequence controller 10 at this time
According to.Second memory 30 can be set in the printed circuit board X-PCB for connecting source electrode drive circuit 60, second memory
30 to can store the software data that luminance compensation demura table data namely the second memory 30 store be that optics is mended
Repay software data.The output end that driving power 70 namely driving power 70 are additionally provided on timing control plate is deposited with first respectively
Reservoir 20, second memory 30 and sequence controller 10 connect, and the power supply of access is converted into the power supply electricity of foregoing circuit module
Source, for foregoing circuit module for power supply.Sequence controller 10 it is electric after, can from first memory 20 and second memory 30
The supplemental characteristic and demura table data for reading initialization are initialized, then through serial communication bus receiving and displaying device
The R/G/B compressed signal of MCU output on middle master control borad controls signal, and the power supply on master control borad then passes through power supply line and drives electricity
Source 70.Driving power 70 exports after the power supply received is converted into corresponding driving power to the circuit mould on timing control plate
Block.After display device normal work, the R/G/B compressed signal received, control signal are converted into fitting by sequence controller 10
Data-signal, control signal and the clock signal of source electrode drive circuit 60 and gate driving circuit 50 in display device, it is real
The image of existing display panel is shown.
Perhaps Fig. 2 memory can be that high level is enabled or low level is enabled referring to Fig.1, and the present embodiment is chosen as low
Level is enabled, and accordingly, the first chip selection signal is low level signal, and the second chip selection signal is high level signal.First memory
20 and second memory 30 include chip select pin CS, data input pin SI, output pin SO and clock signal foot SCLK, some
In embodiment, first memory 20 and second memory 30 further include Hold foot.The chip select pin of first memory 20 and timing control
Device 10 processed connects, and the chip select pin of second memory 30 is connect with storage switch control circuit 40, that is, first memory 20 by
Control in sequence controller 10, and when receiving the first chip selection signal be selected, and when receiving the second chip selection signal not by
It chooses.Second memory 30 is controlled by storage switch control circuit 40, and storage switch control circuit 40 is according to timing control
The chip selection signal ON/OFF of device 10.Specifically, the closing when receiving sequence controller 10 and exporting the first chip selection signal, this
When storage switch control circuit 40 export the chip selection signal of high level to second memory 30, therefore second memory 30 not by
It chooses.And the conducting when receiving sequence controller 10 and exporting the second chip selection signal, storage switch control circuit 40 is defeated at this time
Low level chip selection signal is to second memory 30 out, to keep second memory 30 selected.
It should be noted that passing through two groups between sequence controller 10 and first memory 20 and second memory 30 respectively
Serial communication bus carries out communication connection, this prevents the entire driving framework of display panel from doing small package, volume it is big and
Higher cost.For this purpose, in the present embodiment, first memory 20 and second memory 30 are using same group of serial communication bus come real
It is existing, and during sequence controller 10 reads data, other chips may be had an impact, such as in sequence controller 10
Read first memory 20 data when, the data of second memory 30 may be scurried into sequence controller 10, or when
When sequence controller 10 reads the data of second memory 30, the data-signal of first memory 20 export to sequence controller 10 and
Lead to the work disorder of sequence controller 10, so that sequence controller 10 reads the data failure of two memories.
To solve the above-mentioned problems, storage switch control can be further arranged in the driving circuit of the present embodiment display panel
Circuit 40 processed realizes the switching of memory.Specifically, storage switch control circuit 40 receives what sequence controller 10 exported
Chip selection signal and open/disconnect, when electric on the display apparatus, sequence controller 10 exports the first chip selection signal, to control storage
Device ON-OFF control circuit 40 is closed and first memory 20 is selected.Sequence controller 10 passes through serial communication bus at this time
It is realized with reading the software data of the first memory 20 to sequence controller 10 with 20 communication connection of first memory
Initial setting up.In this process, storage switch control circuit 40 is in an off state, therefore the data of second memory 30
It will not be exported through serial communication bus to first memory 20 or sequence controller 10, and first is read to sequence controller 10
20 data of memory generate interference.And the second chip selection signal is exported in sequence controller 10, to control storage switch control electricity
Road 40 is connected, to export low level chip selection signal to second memory 30, second memory 30 is selected, timing control at this time
Device 10 processed is by serial communication bus and 30 communication connection of second memory, to read the software number of the second memory 30
According to luminance compensation of the realization to display panel.In this process, first memory 20 receives the second chip selection signal without quilt
It chooses, therefore the data of first memory 20 will not be exported through serial communication bus to second memory 30 or sequence controller
10, and 30 data of second memory are read to sequence controller 10 and generate interference.Terminate in initialization, display device enters normal
When working condition, sequence controller 10 is by serial communication bus and control 20 communication connection of chip, to receive control chip
Control signal, data-signal and the clock signal of 20 outputs, and exported after being converted to corresponding driving signal, complete display panel
Image show.
The present invention is deposited by setting storage switch control circuit 40, sequence controller 10, first memory 20 and second
Reservoir 30, and the communication connection with first memory 20 and second memory 30 is realized by same serial communication bus.And lead to
It crosses setting storage switch control circuit 40 to be arranged in series between the chip select pin and sequence controller 10 of first memory 20, deposit
Reservoir ON-OFF control circuit 40 is controlled based on the chip selection signal of sequential control circuit, and is controlled memory in sequence controller 10 and opened
When closing the closing of control circuit 40, sequence controller 10 and 20 communication connection of first memory are realized, so that sequence controller 10 is read
The software data of first memory 20 are taken, and then complete the initial setting up of sequence controller 10.And it is controlled in sequence controller 10
When storage switch control circuit 40 is opened, the communication connection of sequence controller 10 and second memory 30 is realized, so that timing
The software data of the reading second memory 30 of controller 10.The present invention solves sequence controller 10 and needs through setting multiple groups string
Row communication bus realizes the communication connection between different memories, causes the entire driving framework of display panel cannot to do
The problem of small package, volume is big and higher cost.
Meanwhile this invention also solves sequence controller 10 read first memory 20 data when, second memory 30
Data may scurry into sequence controller 10, and cause sequence controller 10 read 20 data failure of first memory, or
When reading the data of second memory 30, the data of first memory 20 are sealed in sequence controller 10, and sequence controller 10
The problem of reading 30 data failure of second memory.The present invention is also effectively solved to be connected using same serial communication bus
When memory, the problem of 10 software read error of sequence controller, the reliability of display device is improved.
Referring to figs. 1 to Fig. 3, in one embodiment, the sequence controller 10 is additionally configured to output third piece choosing letter
Number, it is stopped working with controlling the first memory 20, and the control storage switch control circuit 40 turns off, with control
The second memory 30 stops working.
In the present embodiment, the number of the data second memory 30 of first memory 20 has been successively read in sequence controller 10
According to, and after completing power-up initializing, sequence controller 10 will export third chip selection signal namely high-impedance state signal, so that the
The chip select pin of one memory 20 is in high-impedance state, and under high-impedance state signal, storage switch control circuit 40 is not turned on, and is made
The chip select pin input of second memory 30 is high level, will not be equally selected.
Referring to Figures 1 and 2, in an alternative embodiment, the storage switch control circuit 40 includes first switch tube
The controlled end of Q1 and pull-up resistor R1, the first switch tube Q1 be the storage switch circuit controlled end, described first
The first end of switching tube Q1 is grounded, and the second end of the first switch tube Q1 is that the piece of the storage switch control circuit 40 selects
Signal output end, and connect through the pull-up resistor R1 with the first DC power supply.
In the present embodiment, first switch tube Q1 can realize that the present embodiment can using switching tubes such as triode, metal-oxide-semiconductors
Choosing is realized using N-MOS pipe.First resistor R1 is pull-up resistor R1, is deposited for exporting the chip selection signal of low high level to second
Reservoir 30, so that it is selected second memory 30 not, and it is in a state of stopping working.When electric on the display apparatus, timing
When controller 10 exports low level first chip selection signal, storage switch control circuit 40 is failure to actuate, so that N-MOS pipe be made to protect
Off state is held, first resistor is by the high level output of the first DC power supply to second memory 30 at this time, so that the second storage
Device 30 is in idle state, and in the second chip selection signal of the second sequence controller 10 output high level, N-MOS pipe is led
It is logical, and low level output is exported to second memory 30, so that second memory 30 is selected.Terminate in initialization, display dress
It sets when entering normal operating conditions, sequence controller 10 exports third chip selection signal, so that the cut-off of N-MOS pipe is controlled, so that the
One resistance R1 exports the chip selection signal of low high level to second memory 30, so that second memory 30 be made not to be selected, and locates
In the state to stop working.
The present invention also proposes a kind of driving circuit of display panel.
Referring to figs. 1 to Fig. 3, the driving circuit of the display panel includes:
Sequence controller 10 is configured as output the first chip selection signal, the second chip selection signal, third chip selection signal；
First memory 20 is configured to the initialization software data of storage display panel；
Second memory 30 is configured to storage optical compensation software data；
Data of the data transmission terminal of the first memory 20 and second memory 30 with the sequence controller 10
Transmission end connection；The first memory 20 is additionally configured to be selected when receiving the first chip selection signal, and supplies the timing
Controller 10 reads the initialization software data of the display panel of storage；
Storage switch control circuit 40, including controlled end and control signal output, the controlled end and the timing
The chip selection signal output end of controller 10 connects, and the chip select pin of the control signal output and the second memory 30 connects
It connects；The storage switch control circuit 40 is configured to receiving the second chip selection signal conducting, to control described second
Memory 30 is selected, and the optical compensation software data of storage are read for the sequence controller 10；
The sequence controller 10 is additionally configured to output third chip selection signal, is stopped with controlling the first memory 20
It is only selected, and the control storage switch control circuit 40 turns off, stops being chosen to control the second memory 30
In.
Wherein, the specific selected process of the first memory 20 and second memory 30 are as follows:
After sequence controller 10 works on power, first chip selection signal is exported, 20 quilt of first memory is controlled
It chooses, sequence controller 10 instructs to lower read of first memory 20 after SCLK gets up, through MOSI (SI) and starts to read
Address, then sequence controller 10 beginning the initial code being stored therein, Ye Jixian are read from first memory 20
Show the initialization software data of panel；
After the power-up initializing of sequence controller 10, second chip selection signal is exported, the storage switch control is controlled
Circuit 40 processed is connected, and selected to control the second memory 30, sequence controller 10 is by MOSI (SI) to the second storage
Device 30 is lower to be read instruction and starts the address read, and then the beginning of sequence controller 10 reads described the from second memory 30
The optical compensation software data of two memories 30 storage, namely demura table is read, it is completed until reading.
After the parameter and demura table for reading initialization are initialized, the third chip selection signal is exported, is controlled
It makes the first memory 20 to stop being selected, and the control storage switch control circuit 40 turns off, described in control
Second memory 30 is not selected.
After sequence controller 10 has read the initial code in first memory 20 and second memory 30, timing control
Device 10 processed discharges spi bus, and the chip selection signal CS of output is high-impedance state signal Hi-Z, and first memory 20 will not be selected, this
When second memory 30 chip selection signal also because the presence of pull-up resistor R1, can be pulled to high level H, therefore second memory 30
It will not be selected, the code that can avoid in memory is written over.
Referring to Fig. 3, in one embodiment, the driving circuit of display panel further includes gamma circuit 80, is configured for producing
Raw multichannel gamma electric voltage, and export the timing control exported to source electrode driver 40, source electrode driver 40 according to sequence controller 10
Signal and gamma electric voltage processed, the corresponding pixel of control thin film transistor (TFT) charges, so that source electrode driver 40 believes data
Number output shows image to be shown to corresponding pixel.Gamma circuit 80 is optional to be realized using programmable gamma chip, or
Person is realized using the discrete element such as resistance string, memory, can produce one group of gamma electric voltage (Vγ1~Vγ14) can be used as
Pixel gray level reference voltage.Gate drivers 20 are originated in the gate drive signal for receiving the output of sequence controller 10, i.e. frame
Signal (Start Vertical, STV), scan clock pulse signal (Clock Pulse Vertical, CPV) and enable signal
When (Output Enable, OE), scanning signal is exported line by line, to drive thin film transistor (TFT) to open line by line.
The present invention also proposes a kind of display device, including display panel and display panel, drive circuit as described above, institute
The gate driving circuit and the source electrode drive circuit for stating display panel are electrically connected with the display panel respectively.The display panel
The detailed construction of driving circuit can refer to above-described embodiment, and details are not described herein again；It is understood that due to the invention shows
Above-mentioned display panel, drive circuit is used in device, therefore, the embodiment of the display device of that present invention includes above-mentioned display panel
Whole technical solutions of driving circuit whole embodiments, and technical effect achieved is also identical, details are not described herein.
In the present embodiment, display device can be television set, tablet computer, mobile phone etc. and fill with the display of display panel
It sets.The display device further includes timing control plate and source electrode printed circuit board；Display panel 100 can be OLED (Organic
Light-Emitting Diode, Organic Light Emitting Diode) display panel 100, it is also possible to TFT-LCD (Thin Film
Transistor Liquid Crystal Display) display panel 100.
Referring to Fig. 4, in one embodiment, the display panel 100 includes:
Pixel array 150；
Array substrate 140；
Liquid crystal layer 160 is set between the array substrate 140 and the color membrane substrates 180, and the liquid crystal layer 160 wraps
Several liquid crystal molecules are included, the pixel array 150 is used to control the movement of several liquid crystal molecules；
Multi-strip scanning line (G1, G2, G3 ... Gn) is arranged in the array substrate 140；
Multiple data lines (D1, D2, D3 ... Dn) are arranged in the array substrate 140；
In the present embodiment, array substrate 140 and color membrane substrates 180 are usually the light transmissions material such as glass substrate or plastic base
Expect substrate.Color membrane substrates 180 are oppositely arranged with array substrate 140, can be set between array substrate 140 and color membrane substrates 180
Set corresponding circuit.Pixel array 150 is set in array substrate 140.
In above-described embodiment, the pixel array 150 includes multiple sub-pixels, and each sub-pixel includes an active
Switch (thin film transistor (TFT)) and a pixel electrode, the grid of active switch scan line corresponding with the sub-pixel electrically connect
Connect, the source electrode of active switch data line electrical connection corresponding with the pixel unit 130, the drain electrode of the active switch with
The pixel electrode of the sub-pixel is electrically connected.Pixel array 150 further includes the pixel electrode battle array for connecting active switching element array
Column.
Display panel 100 is made of multiple pixels, each pixel again by three sub-pix groups of RGB at.Each sub-pix
Circuit structure is typically provided with a thin film transistor (TFT) and a capacitor, and the grid of thin film transistor (TFT) is driven by scan line and grid
Dynamic device 50 connects, and the source electrode of thin film transistor (TFT) is connect by data line with source electrode driver 60, the drain electrode of thin film transistor (TFT) and electricity
One end of appearance connects.Wherein, multiple thin film transistor (TFT)s constitute thin film transistor (TFT) array (figure does not indicate).Positioned at the thin of same row
Film transistor is connect by a data line with source electrode driver 60, and the thin film transistor (TFT) positioned at same a line passes through scan line and grid
Driver 50 connects, so to constitute thin film transistor (TFT) array.These thin film transistor (TFT)s can be a-Si (non-silicon wafer) film
Transistor or Poly-Si (polysilicon) thin film transistor (TFT), wherein Poly-Si thin film transistor (TFT) can use LTPS (Low
Temperature Poly-Silicon, low temperature polycrystalline silicon) etc. technologies formed.
It is understood that display panel 100 further includes frame glue 170 in above-described embodiment, it is set to array substrate 140
In non-display area BB between color membrane substrates 180 and around liquid crystal layer 160 be arranged, GOA circuit 100 be located at frame glue 170 and
Between the AA of display area.Frame glue 170 can be coated in array substrate 140 or on color membrane substrates 180 using sealant, with
Array substrate 140 and color membrane substrates 180 are connected, to realize that the assembling to display panel 100 is handled.Specifically, the pixel
Array 150 is the pixel array 150 of half source drive (Half source driving, HSD) framework.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (10)
1. a kind of driving circuit of display panel, which is characterized in that the driving circuit of the display panel includes:
Sequence controller is configured as the first chip selection signal of output and the second chip selection signal；
The data transmission terminal of first memory and second memory, the first memory and second memory with the timing
The data transmission terminal of controller connects；The first memory is configured to the work when receiving the first chip selection signal, and for institute
State the software data that sequence controller reads storage；
Storage switch control circuit, including controlled end and control signal output, the controlled end and the sequence controller
The connection of chip selection signal output end, the control signal output connect with the chip select pin of the second memory；The storage
Device ON-OFF control circuit is configured to be connected and export control second memory work receiving second chip selection signal
Chip selection signal to the second memory, so that the sequence controller reads the software data of storage.
2. the driving circuit of display panel as described in claim 1, which is characterized in that the sequence controller is also configured
To export third chip selection signal, stopped working with controlling the first memory, and the control memory control switch electricity
Road turns off and exports the chip selection signal for controlling the second memory work to the second memory, is deposited with controlling described second
Reservoir stops working.
3. the driving circuit of display panel as described in claim 1, which is characterized in that the software of the first memory storage
Data are the initialization software data of display panel；
The software data of the second memory storage are optical compensation software data.
4. the driving circuit of display panel as described in claim 1, which is characterized in that the driving circuit of the display panel is also
Including serial communication bus, the sequence controller connects the first memory and described the by the serial communication bus
Two memories.
5. the driving circuit of display panel as described in claim 1, which is characterized in that the storage switch control circuit packet
First switch tube and pull-up resistor are included, the controlled end of the first switch tube is the controlled end of the storage switch circuit, institute
The first end ground connection of first switch tube is stated, the second end of the first switch tube is that the piece of the storage switch control circuit selects
Signal output end, and connect through the pull-up resistor with the first DC power supply.
6. the driving circuit of the display panel as described in claim 1 to 5 any one, which is characterized in that the display panel
Driving circuit further include gate driving circuit and source electrode drive circuit, the gate driving circuit and the source electrode drive circuit
Controlled end connect respectively with the output end of the sequence controller.
7. a kind of driving circuit of display panel, which is characterized in that the driving circuit of the display panel includes:
Sequence controller is configured as output the first chip selection signal, the second chip selection signal, third chip selection signal；
First memory is configured to the initialization software data of storage display panel；
Second memory is configured to storage optical compensation software data；
The data transmission terminal of the first memory and second memory is connect with the data transmission terminal of the sequence controller；
The first memory is additionally configured to the work when receiving the first chip selection signal, and reads storage for the sequence controller
Display panel initialization software data；
Storage switch control circuit, including controlled end and control signal output, the controlled end and the sequence controller
The connection of chip selection signal output end, the control signal output connect with the chip select pin of the second memory；The storage
Device ON-OFF control circuit is configured to receiving the second chip selection signal conducting, to control the second memory work, and
The optical compensation software data of storage are read for the sequence controller；
The sequence controller is additionally configured to output third chip selection signal, is stopped working with controlling the first memory, with
And the control memory control switch circuit shutdown, it is stopped working with controlling the second memory.
8. the driving circuit of display panel as claimed in claim 7, which is characterized in that the specific works of the sequence controller
Process are as follows:
First chip selection signal is exported, the first memory work is controlled, and reads the aobvious of the first memory storage
Show the initialization software data of panel；
Second chip selection signal is exported, the storage switch control circuit conducting is controlled, to control the second memory
Work, for the sequence controller after second memory work, the optical compensation for reading the second memory storage is soft
Volume data；
The third chip selection signal is exported, the first memory is controlled and stops working, and the control storage switch control
Circuit shutdown processed, is stopped working with controlling the second memory.
9. a kind of display device, which is characterized in that the display including display panel and as described in claim 1 to 6 any one
The driving circuit of panel；Alternatively, include the driving circuit of the display panel as described in any one of claim 7 and 8, it is described aobvious
The gate driving circuit and source electrode drive circuit for showing panel are electrically connected with the display panel respectively.
10. display device as claimed in claim 9, which is characterized in that the display device further includes timing control plate and source
Pole drives printed circuit board；
Sequence controller, the first memory of the driving circuit of the display panel are set on the timing control plate；
The second memory of the driving circuit of the display panel is set on the source drive printed circuit board.
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| CN112860125A (en) * | 2021-03-19 | 2021-05-28 | 京东方科技集团股份有限公司 | Touch display driving device and method and touch display device |
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| CN114078416A (en) * | 2021-11-23 | 2022-02-22 | 京东方科技集团股份有限公司 | Sequential control circuit, display module and display device |
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