JP2003099018A - Flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update part of a display image with small power consumption. SOLUTION: The flat display device is equipped with a plurality of display pixels PX having memory elements 15 respectively, a vertical decoding part 120 which selectively specify a row block of the display pixels PX, a horizontal decoding part 110 which selectively specifies a column block of the display pixels, a video RAM 80 which holds image data allocated to the memory elements 15 of the plurality of display pixels PX, and a controller 60 which controls the operations of the vertical and horizontal decoding parts 110 and 120 so that the contents of the video RAM 80 are written to the block unit specified by the row and column blocks. This device is equipped with an interface 90 which determines a rewriting range corresponding to the display pixels of at least one block including display pixels for the part of the image data when part of the image data is altered in the video RAM 80 and supplies image data allocated to the respective blocks included in the rewriting range to the controller 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device in which a plurality of display pixels are arranged in a matrix, and more particularly to a flat panel display device in which each display pixel includes a memory element holding image data.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display panel has been widely used as a monitor display of a notebook PC or a mobile terminal device because of its beautiful display and high product reliability. This liquid crystal display panel is generally held between an array substrate in which a plurality of pixel electrodes are arranged in a matrix, a counter substrate in which a counter electrode is opposed to the plurality of pixel electrodes, and between the array substrate and the counter substrate. It is composed of a liquid crystal layer. The array substrate has, in addition to a plurality of pixel electrodes, a plurality of scanning lines arranged along rows of these pixel electrodes, a plurality of signal lines arranged along columns of these pixel electrodes, and these scanning lines and signal lines. A plurality of pixel switches arranged near the intersection position of Each pixel switch is connected so as to apply the signal voltage of the corresponding signal line to the corresponding pixel electrode when driven through the corresponding scanning line. By using this pixel switch, crosstalk between adjacent pixels can be sufficiently reduced and a high-contrast image can be obtained.

A pixel switch is generally composed of a thin film transistor using a semiconductor thin film of amorphous silicon. Recently, advances in manufacturing technology have made it possible to form polysilicon semiconductor thin films having higher carrier mobility than amorphous silicon. By using this thin film forming technique, not only pixel switches for pixel electrodes but also vertical drivers and horizontal drivers can be incorporated in the array substrate.

By the way, a mobile terminal such as a mobile phone is mainly operated by a battery power source, and therefore it is preferable that the power consumption is as low as possible. For this reason, it is common practice to reduce the brightness of the display screen in the standby state of the mobile phone. Recently, there is known a technique capable of stopping the vertical driver and the horizontal driver. With this technology,
A plurality of memory elements are respectively provided in the display pixels forming the display screen, and hold image data representing the same image in the standby state. The vertical driver and the horizontal driver are stopped while the same image is being displayed corresponding to the contents of these memory elements, and as a result the power consumption of the display can be reduced.

[0005]

However, if these vertical and horizontal drivers are completely stopped, it becomes difficult to update only a part of the display image.

In view of the above technical problems, an object of the present invention is to provide a flat display device capable of updating a part of a display image with low power consumption.

[0007]

According to one aspect of the present invention, a matrix array of a plurality of display pixels each having a memory element for displaying an image corresponding to the contents of the memory element and a row of the plurality of display pixels. A vertical scanning circuit that selectively designates a block and enables writing of display pixels corresponding to the selected row block to a memory element, and a column block of a plurality of display pixels is selectively designated and corresponds to the selected column block. Refer to the horizontal scanning circuit that writes image data to the memory element of the display pixel, the interface that writes and reads the address data and image data for each display pixel supplied from the outside to the video memory, and the address data and image data supplied from the interface. Interface controller that controls the operation of the vertical and horizontal scanning circuits. Is different from the image data in the video memory and detects the address data of the display pixel portion corresponding to the image data supplied from the outside, and the row including the portion of the display pixel specified by the detected address data and There is provided a flat display device having an operation mode in which a column block is determined as a rewriting range and partial image data corresponding to the rewriting range is supplied to a controller.

In this flat panel display device, the interface is different from the image data in the video memory and the address data of the display pixel portion corresponding to the image data supplied from the outside is detected and specified by the detected address data. Addressing of the vertical scanning circuit and the horizontal scanning circuit is simplified because the row and column block including the portion of the display pixel to be determined is determined as the rewriting range and the partial image data corresponding to this rewriting range is supplied to the controller. As a result, even if this display pixel portion is insufficient for rewriting the image data for the display pixel of each block, the shortage of the image data can be complemented by the contents of the video memory. That is, when the image data of one address format is supplied from the outside for updating a part of the image data held in the video memory, this address format can be adapted to the addressing system of the controller. Therefore, it does not require power consumption such as when rewriting the memory elements of all display pixels,
You can update part of the displayed image.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flat panel display device according to an embodiment of the present invention will be described below with reference to the drawings. This flat display device is configured to be operable in a normal writing mode for updating the entire screen and a random writing mode for updating a part of an image in block units.

FIG. 1 schematically shows the structure of this flat display device, FIG. 2 shows the structure of the display pixel of the liquid crystal display panel shown in FIG. 1, and FIG. 3 is a partial cross section of the display pixel shown in FIG. The structure is shown.

The flat-panel display device includes, for example, a reflective liquid crystal display panel LCD having a display area DA in which a plurality of display pixels PX are arranged in a matrix and a drive area DR for driving these display pixels PX, and this liquid crystal display panel. LCD
And an external control circuit PCB for controlling the. The liquid crystal display panel LCD includes an array substrate 10, a counter substrate 20 facing the array substrate 10, and a liquid crystal layer 3 as a light modulation layer sandwiched between the array substrate 10 and the counter substrate 20.
Including 0. The liquid crystal layer 30 is obtained by injecting a liquid crystal composition into the gap between the array substrate 10 and the counter substrate 20 and sealing the liquid crystal composition. The light transmittance of the liquid crystal layer 30 is determined by the pixel electrode 11
And the potential difference between the counter electrodes 22 are set.
The array substrate 10 and the counter substrate 20 have polarizing plates PL1 and PL2 on their outer surfaces.

The counter substrate 20 is a light transmissive insulating substrate GL2 such as a glass plate, a color filter 21 formed on the insulating substrate GL2, a counter electrode 22 facing the plurality of pixel electrodes 11 and covering the color filter 21, and An alignment film 23B that covers the counter electrode 22 is included.

Next, the array substrate 10 will be described. The display area DA of the array substrate 10 is a light-transmissive insulating substrate GL1 such as a glass plate, a plurality of pixel electrodes 11 arranged corresponding to the display pixels PX, and a plurality of scans arranged along rows of these pixel electrodes 11. It has a line 12, a plurality of signal lines 13 arranged along the column of these pixel electrodes 11, and a plurality of pixel switches 14 arranged near the intersections of these scanning lines 12 and signal lines 13. Further, the display area DA is arranged in the column direction of the plurality of display pixels PX and is arranged in parallel with the plurality of scanning lines 11 near the intersection of the input gate line 19A and the output gate line 19B, the signal line 13, and the input gate line. The memory input switch 16 disposed, the memory element 15 such as a static RAM which is connected to the memory input switch 16 and holds the image data VD supplied from the corresponding signal line 13, and the memory element 15 are connected to the memory element 15 via the polarity inversion circuit 17. The memory output switch 18 is provided. Each of the pixel switch 14 and the memory output switch 18 is connected to an auxiliary capacitance CS formed by capacitively coupling the corresponding pixel electrode 11 and an auxiliary capacitance line arranged in parallel with the corresponding scanning line 12.
In the normal writing mode, via the pixel switch 14,
In the random writing mode, image data is written in the pixel electrode 11 and the auxiliary capacitance CS via the memory output switch 18.

Further, each pixel switch 14 and each memory output switch 18 are composed of thin film transistors formed on the insulating substrate GL1 using a semiconductor thin film of polysilicon, and are driven via the corresponding scanning line 12 or output gate line 19B. It is connected so as to apply the signal voltage of the corresponding signal line 13 to the corresponding pixel electrode 11 at the time. Further, like the counter substrate 20, the plurality of pixel electrodes 11 are covered with the alignment film 23A as shown in FIG.

The drive region DR of the array substrate 10 includes a vertical driver 40 for driving a plurality of scanning lines 12 and a plurality of signal lines 1.
The vertical decoding unit 110 that controls the horizontal driver 50 and the vertical driver 40 that drive the unit 3 to operate in each unit row.
And a horizontal decoding unit 120 for controlling the horizontal driver 50 to operate for each unit column, and a controller 60 for controlling these operations. The vertical driver 40, the horizontal driver 50, the controller 60, and the vertical decoding unit 11
0, and the horizontal decoding unit 120 has a plurality of display pixels PX.
Is formed outside the display area DA constituted by the above, and is formed in the same process as the pixel switch 14 by forming a thin film transistor using a semiconductor thin film of polysilicon as a segment like the pixel switch 14.

The external control circuit PCB comprises a video RAM 80 and an interface IC 90 arranged on a printed wiring board provided outside the liquid crystal display panel LCD. The video RAM 80 has a plurality of display pixels P.
The address data and the image data for one frame written in X are held. The interface IC 90 temporarily stores address data and image data supplied from the outside in the video RAM 80, sequentially extracts data from the video RAM 80 according to the operation mode, and supplies the data to the controller 60 of the liquid crystal display panel LCD. That is, in the normal write mode, the data corresponding to all the display pixels PX is output to the controller 60, and in the random write mode, the data corresponding to the block to be rewritten is used as the block address data and the update image data. Output to the controller.

Next, the display operation in the normal writing mode will be described. The controller 60 supplies a vertical scan control signal CT with a vertical start pulse and a plurality of vertical clock pulses generated in synchronization with an image frame period in the normal writing mode.
Y is supplied to the vertical driver 40. Further, the controller 60 horizontally sets the horizontal start pulse and a plurality of horizontal clock pulses generated in synchronization with the horizontal scanning period of the image as the horizontal scanning control signal CTX together with the image data VD whose polarity is inverted every frame period or horizontal scanning period. Supply to the driver 50. The vertical driver 40 drives the scanning lines 12 sequentially by shifting the vertical start pulse in response to these vertical clock pulses. On the other hand, the horizontal driver 40 drives the signal lines 13 sequentially by shifting the horizontal start pulse in response to these horizontal clock pulses. Thereby, the image data is written in the pixel electrodes 11 of the display pixels PX of each row while the display pixels PX of each row are driven, and the potentials of the pixel electrodes 11 are set. The memory input switch 16 and the memory output switch 18 also function in the normal write mode, the image data supplied to the signal line 13 is written in the memory element 15, and the voltage of this image data is supplied to the pixel electrode 11.

Next, the display operation in the random writing mode will be described. FIG. 5 shows an example of the rewriting range set for the received image data. The block address data of the block corresponding to the rewriting range and the update image data are supplied from the interface IC of the external drive circuit PCB to the controller. In the example shown in FIG. 5, the shaded area is 4
The display pixels PX for the blocks are set in the rewriting range, and the block address data representing the head positions B1 to B4 of these blocks and the update image data are supplied to the controller 60.

The controller 60 generates a vertical address signal ADY and a horizontal address signal ADX based on this block address data. Then, the vertical clock signal CKY and the vertical address signal ADY are supplied to the vertical decoding unit 110, and the horizontal address signal ADX and the horizontal clock signal CKX are supplied to the horizontal decoding unit 120.
The polarity inversion signal POL that inverts in a predetermined cycle such as a frame period or a horizontal scanning period is supplied to the polarity inversion circuit 17.

As a result, the vertical decoding unit 110 causes the display pixel P of the row block corresponding to the vertical address signal ADY.
Rows of X are sequentially selected and corresponding gate lines 19A and 19B
To drive. While the display pixels PX of each row are selected, the horizontal decoding unit 120 controls the horizontal driver 50 to sequentially select the columns of the display pixels PX of the column block corresponding to the horizontal address signal ADX and drive the corresponding signal lines 13. To do.
The horizontal driver 50 supplies the image data supplied from the controller 60 to the signal line 13 corresponding to the display pixel PX of the selected column under the control of the horizontal decoding unit 120.

More specifically, the horizontal decoding unit 120
Includes a shift register circuit 120A composed of a plurality of shift registers S / R connected in series so as to divide a plurality of display pixels PX into a plurality of column blocks, and a horizontal decoder 120B for decoding a horizontal address signal ADX. The horizontal decoder 120B outputs the scan pulse SP to the shift register S / R corresponding to the horizontal address signal ADX. This shift register S / R is a horizontal clock signal C
In response to KX, the scanning pulse SP is shifted, and the horizontal driver 50 is controlled so as to sequentially drive the number of signal lines 13 corresponding to the number of display pixels of the column block.

The vertical decoding unit 110 is constructed in substantially the same manner as the horizontal decoding unit 120, and is a shift register circuit composed of a plurality of shift registers connected in series so as to divide a plurality of display pixels PX into a plurality of row blocks. And a vertical decoder for decoding the vertical address signal ADY. The vertical decoder outputs a scan pulse to the shift register corresponding to the vertical address signal ADY. The shift register shifts the scanning pulse in response to the vertical clock signal CKY, and sequentially drives the input gate line 19A and the output gate line 19B corresponding to the number of display pixels of the row block. Here, the input gate line 19A and the output gate line 19B are set to have a complementary potential relationship.

In the display pixel PX, when the pixel switch 14 is off, the memory input switch 16 is driven via the input gate line 19A and the memory output switch 18 is driven via the output gate line 19B. Polarity inversion circuit 1
7 is controlled by the polarity inversion signal POL from the controller 60.

In this way, the memory input switch 16 is conducted prior to the memory output switch 18, and the image data on the signal line 13 is written in the memory element 15. When this writing is completed, the memory output switch 18 becomes conductive instead of the memory input switch 16. As a result, the image data is supplied from the memory element 15 to the pixel electrode 11 via the polarity inversion circuit 17. The polarity inversion circuit 17 periodically inverts the voltage polarity of image data.

With the above-described structure, the entire image can be displayed once in the normal writing mode, and then a part of the image can be updated in the random writing mode. In the random write mode, the controller 60 controls the supply of the clock signal to control the vertical driver 40 and the horizontal driver 5.
The operation of 0 can be partially stopped or restricted.

Next, the data transmission from the computer set side, which is the image data source, to the external drive circuit PCB will be described. External control circuit P from the computer set side
The data transmitted to the CB is transmitted in a packet format as shown in FIG. 4, for example. Here, for example, three display pixels PX (corresponding to one dot) corresponding to R, G, and B are transmitted as one set, and the address data and the image data are transmitted respectively.

For example, data transmission from the computer set side to the external drive circuit PCB is switched between a normal writing mode and a random writing mode, and in the normal writing mode, data for all display pixels is transmitted in a packet format. , In random write mode, the data of the part that is changed compared to the previous frame (hereinafter referred to as received data)
Only are transmitted in packet form. Interface IC
Updates some of the image data stored in the video RAM 80 with received data in order to rewrite the display pixels PX in units of row and column blocks, and the row and column blocks of the display pixels PX including the display area to which this received data is assigned. Is output to the controller 60 as partial image data corresponding to the rewriting range specifying

FIG. 6 details the operation of the interface IC 90 performed in the random write mode. The interface IC 90 updates a part of the image data held in the video RAM 80 with the received data in step ST1, determines the rewriting range for specifying the row and column blocks based on the address data for the received data in step ST2,
At step ST3, each block of the partial image data VD corresponding to the rewriting range is read out, and this partial image data V is read.
The block of D is supplied to the controller 60 together with the block address data assigned to it. Since the display area of the reception data is only a part of the rewriting range, the shortage of the reception data is complemented by the contents of the video RAM 80.

In the flat panel display device of this embodiment, the addressing of the vertical decoding section 110 and the horizontal decoding section 120 is simplified by designating the rewriting range of the display pixel in block units. On the other hand, the interface IC90
Since the image data that is lacking due to such rewriting in block units is supplemented by the contents of the video RAM 80, rewriting can be performed normally. That is, the addressing format of the partial image data supplied from the outside and the addressing system of the controller can be matched. As a result, it is possible to update a part of the display image without requiring power consumption as in the case of rewriting the memory elements 15 of all the display pixels PX.

The present invention is not limited to the above embodiment, but can be variously modified.

For example, in the above-described embodiment, the case where the data transfer from the computer set side to the interface IC 90 differs according to the operation mode has been described, but one frame of data is transferred from the computer set side to the interface IC 90 regardless of the operation mode. It may be transmitted to. In this case, the interface IC
At 90, the previous frame stored in the video RAM 80 is read and the transmitted data is transferred to the video R.
Store in AM80. Then, the changed portion is detected by comparing the image data of the previous frame with the image data of the next frame. Then, based on the changed portion, it is controlled to operate in the normal writing mode or the random writing mode. In this control, it is desirable to set appropriately according to the application of the flat panel display device. When operating in the random write mode, the image data corresponding to the display pixels PX of all blocks including the changed portion is supplied to the controller 60 together with the block address data.

As described above, when the random writing mode is performed, the changed portion can be updated in block units, and the external drive circuit PCB and the liquid crystal display panel LC can be updated.
It is possible to reduce the power consumption required for data transfer between D. In the liquid crystal display panel LCD,
Only the drive circuit corresponding to the block to be changed can be partially operated, and the power consumption can be further reduced.

If the random writing mode continues for a predetermined time or longer, all display pixels PX may be rewritten periodically even if the changed portion of the image is a part of the display area DA.

Further, the above-mentioned embodiment is a liquid crystal display panel L.
Although the flat display device using the CD has been described, the present invention can be applied to all active matrix display devices, for example, an organic EL display panel.

For example, when applied to an organic EL display panel, the polarity reversing circuit 17 shown in FIG. 2 becomes unnecessary, and the display pixel P as shown in FIG. 7 can be used. In this example, the display pixel P is the organic EL light emitting element P1,
Between the power supply terminals VDD and VSS, the organic EL light emitting element P1
A driving transistor P2 which is a P-channel thin film transistor connected in series with the driving transistor P2, and a capacitor P3 connected between the gate and the source of the driving transistor P2. Further, the number of wirings can be reduced by configuring as shown in FIG. In this example, the OR gate circuit MX is commonly connected to the gate line 19A driven by the vertical decoding unit 110 and the scanning line 12 driven by the vertical driver 40. The output line 12 ′ of the OR gate circuit MX is connected to the gate of the pixel switch 14 formed of an N-channel thin film transistor and the gate of the memory output switch 18 ′ formed of a P-channel thin film transistor, and the memory element 15 is connected to the pixel switch 1.
4 and the memory output switch 18 '. When the output line 12 'of the OR gate circuit MX rises to a high level, the pixel switch 14 becomes conductive and the memory output switch 1
8'is non-conducting. As a result, the image data is written from the signal line 13 to the memory element 15 via the pixel switch 14. In addition, the output line 12 'of the OR gate circuit MX
Falls to a low level, the pixel switch 14 becomes non-conductive and the memory output switch 18 'becomes conductive. As a result, the image data is supplied from the memory element 15 to the gate of the drive transistor P2 via the memory output switch 18 '.

[0036]

As described above, according to the present invention, it is possible to provide a flat display device capable of updating a part of a display image with low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram schematically showing a configuration of a flat panel display device according to an embodiment of the present invention.

2 is a circuit diagram showing a configuration of a display pixel of the liquid crystal display panel shown in FIG.

3 is a diagram showing a partial cross-sectional structure of the display pixel shown in FIG.

4 is a diagram showing a format of a packet externally supplied to the interface IC shown in FIG.

5 is a diagram showing a rewriting range set for the received image data shown in FIG.

FIG. 6 is a flowchart showing in detail an operation performed by the interface IC shown in FIG. 1 in a random write mode.

7 is a circuit diagram showing a configuration of a display pixel of an organic EL panel according to a first modification of the flat panel display device shown in FIG.

8 is a circuit diagram showing a configuration of a display pixel of an organic EL panel according to a second modification of the flat panel display device shown in FIG.

[Explanation of symbols]

PX ... Display pixel 10 ... Array substrate 12 ... Scan line 13 ... Signal line 60 ... Controller 80 ... Video RAM 90 ... Interface IC 110 ... Vertical decoding section 120 ... Horizontal decoding section

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 612U 621 621D 621E 624 624B 631 631B F term (reference) 2H093 NA11 NA16 NC28 NC34 NC40 NC50 NC71 ND39 NE10 NG20 5C006 AA01 AC11 AF03 AF04 AF31 AF44 AF45 AF51 AF53 AF61 AF69 AF71 BB16 BC03 BC11 BC16 BF02 BF16 FA47 5C080 AA05 AA06 AA10 BB05 DD26 EE19 GG12 JJ02 JJ05 JJ07

Claims (5)

[Claims] 1. A matrix array of a plurality of display pixels each having a memory element for displaying an image corresponding to the contents of these memory elements, and a row block of the plurality of display pixels is selectively designated to be the selected row block. A vertical scanning circuit that enables writing of a corresponding display pixel to a memory element, and a horizontal scanning circuit that selectively designates a column block of the plurality of display pixels and writes image data to the memory element of the display pixel corresponding to the selected column block. A scanning circuit and an interface for writing and reading address data and image data for each display pixel supplied from the outside into a video memory,
A controller for controlling the operation of the vertical and horizontal scanning circuits with reference to address data and image data supplied from the interface is provided, and the interface is different from the image data in the video memory and is externally supplied. The address data of the display pixel portion corresponding to the image data is detected, the row and column blocks including the display pixel portion specified by the detected address data are determined as the rewriting range, and the partial image corresponding to this rewriting range A flat panel display device having an operation mode for supplying data to the controller. 2. The interface is configured to write the supplied image data so as to update a part of the image data held in the video memory, and read the image data assigned to each block included in the rewriting range. The flat display device according to claim 1, wherein the flat display device is a display device. 3. The interface reads the image data held in the video memory as image data of a preceding frame and compares the image data of the preceding frame with the image data of the next frame supplied to the interface. The flat panel display according to claim 1, wherein the flat panel display is configured to detect a changed portion of image data. 4. The flat panel display device of claim 1, wherein the interface is configured to receive image data supplied in packet form. 5. The partial image data includes image data supplied from the outside and image data selected from image data assigned to each block included in a rewriting range to complement the externally supplied image data. The flat panel display device according to claim 1, wherein the flat panel display device is a combination.