KR100960279B1

KR100960279B1 - Iii-nitride semiconductor light emitting device

Info

Publication number: KR100960279B1
Application number: KR20070142023A
Authority: KR
Inventors: 김창태; 나민규
Original assignee: 주식회사 에피밸리
Priority date: 2007-12-31
Filing date: 2007-12-31
Publication date: 2010-06-04
Also published as: KR20090073943A

Abstract

The present invention provides a grooved substrate, comprising: a substrate having a first surface and a second surface; A plurality of group III nitride semiconductor layers formed on the first side of the substrate and including an active layer that generates light through recombination and a first group III nitride semiconductor layer positioned between the first side and the active layer of the substrate; An opening formed along the plurality of group III nitride semiconductor layers over the groove; A first electrode in electrical contact with the first group III nitride semiconductor layer; A second electrode plated on the first electrode through the opening; And a third electrode electrically contacting the first electrode and the second electrode from the second surface of the substrate.

Nitride, Semiconductor, Light Emitting Diode, Electrode, Opening, Hole, Plating, Recombination, Conductive

Description

Group III nitride semiconductor light emitting device {III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE}

TECHNICAL FIELD The present invention relates to a group III nitride semiconductor light emitting device, and more particularly, to a vertical group III nitride semiconductor light emitting device having a hole penetrating the device, and more particularly, to a vertical group III nitride semiconductor light emitting device using plating. It relates to the electrode structure of the device.

Here, the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device, such as a light emitting diode including, and does not exclude the inclusion of a material or a semiconductor layer of these materials with elements of other groups such as SiC, SiN, SiCN, CN.

1 is a view showing an example of a conventional group III nitride semiconductor light emitting device, the group III nitride semiconductor light emitting device is epitaxially grown on the substrate 100, the substrate 100, the buffer layer 200, the buffer layer 200 N-type nitride semiconductor layer 300 to be grown, active layer 400 epitaxially grown on n-type nitride semiconductor layer 300, p-type nitride semiconductor layer 500 and p-type nitride semiconductor layer to be epitaxially grown on active layer 400 The p-side electrode 600 formed on the 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type nitride semiconductor layer 500 and the active layer 400 are mesa-etched and exposed. and an n-side electrode 800 and a protective film 900 formed on the n-type nitride semiconductor layer.

As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a SiC substrate, or a Si substrate is used as the heterogeneous substrate. Any substrate may be used as long as the nitride semiconductor layer can be grown. When a SiC substrate is used, the n-side electrode 800 may be formed on the SiC substrate side.

The nitride semiconductor layers epitaxially grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).

The buffer layer 200 is for overcoming the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the nitride semiconductor, and US Pat. No. 5,122,845 has a thickness of 100Å to 500Å at a temperature of 380 ℃ to 800 800 on a sapphire substrate. A technique for growing an AlN buffer layer having a thickness is disclosed, and U.S. Patent No. 5,290,393 discloses Al (x) Ga (1-x) N (0) having a thickness of 10 Pa to 5000 Pa at a temperature of 200 to 900 ° C. on a sapphire substrate. ≤ x <1) A technique for growing a buffer layer is disclosed. International Publication No. WO / 05/053042 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C., followed by In (x) Ga. Techniques for growing a (1-x) N (0 <x≤1) layer are disclosed.

In the n-type nitride semiconductor layer 300, at least a region (n-type contact layer) on which the n-side electrode 800 is formed is doped with an impurity, and the n-type contact layer is preferably made of GaN and doped with Si. U. S. Patent No. 5,733, 796 discloses a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.

The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells. International Publication WO / 02/021121 discloses a technique for doping only a plurality of quantum well layers and a part of barrier layers.

The p-type nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has a p-type conductivity through an activation process. US Patent No. 5,247,533 discloses a technique for activating a p-type nitride semiconductor layer by electron beam irradiation, and US Patent No. 5,306,662 discloses a technique for activating a p-type nitride semiconductor layer by annealing at a temperature of 400 ° C or higher. International Patent Publication No. WO / 05/022655 discloses a technique in which a p-type nitride semiconductor layer has a p-type conductivity without an activation process by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growth of a p-type nitride semiconductor layer. Is disclosed.

The p-side electrode 600 is provided to provide a good current to the entire p-type nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type nitride semiconductor layer and is a p-type nitride semiconductor. A light-transmitting electrode of Ni and Au in ohmic contact with layer 500 is disclosed. US Pat. No. 6,515,306 discloses forming an n-type superlattice layer on a p-type nitride semiconductor layer. A technique is disclosed in which a translucent electrode made of indium tin oxide (ITO) is formed thereon.

On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, this technique is referred to as flip chip (flip chip) technology. U. S. Patent No. 6,194, 743 discloses a technique for an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.

The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 discloses a technique in which the n-side electrode is composed of Ti and Al.

The protective film 900 is formed of a material such as silicon dioxide and may be omitted.

Meanwhile, the n-type nitride semiconductor layer 300 or the p-type nitride semiconductor layer 500 may be composed of a single layer or a plurality of layers, and recently, the substrate 100 may be nitrided by laser or wet etching. A technique for manufacturing a vertical light emitting device separately from the above is being introduced.

In general, in the case of the group III nitride semiconductor light emitting device, sapphire is mainly used as the substrate 100. Since sapphire does not conduct electricity, electrodes for supplying current are horizontally positioned. At this time, some of the light generated in the active layer 400 escapes to the outside to affect the external quantum efficiency, but a large amount of light is trapped in the sapphire substrate 100 and the nitride semiconductor layer is not escaped by heat disappears. In addition, since current is applied in the horizontal direction, an imbalance in current density occurs in the light emitting device, which adversely affects the performance of the device.

Therefore, after growing a plurality of nitride semiconductor layers on the sapphire substrate 100, techniques for removing the sapphire substrate 100 and manufacturing a highly efficient light emitting device having an electrode structure in the vertical direction have been studied. In general, a method using a laser is used to remove the sapphire substrate 100. When the laser is irradiated to the lower part of the sapphire substrate 100, the sapphire substrate 100 does not absorb the laser light but transmits it as it is, but the nitride semiconductor layer absorbs the laser light to separate the group III element and the nitrogen element. Since gallium, which is the main group III element, maintains a liquid phase even at room temperature, the sapphire substrate 100 and the nitride semiconductor layer are separated. However, the method using the laser generates high heat during laser irradiation, which adversely affects the device, and also the nitride semiconductor layer is broken due to the stress between the sapphire substrate 100 and the nitride semiconductor layer.

FIG. 2 is a view showing an example of a vertical group III nitride semiconductor light emitting device shown in WO / 07/119919, the inventor of which is the owner, and the group III nitride semiconductor light emitting device includes a sapphire substrate having grooves 110 formed therein (FIG. 100), buffer layer 200, n-type nitride semiconductor layer 300, active layer 400 for generating light by recombination of electrons and holes, p-type nitride semiconductor layer 500, p-side electrode 600, p Side bonding pads 700. An opening 910 is formed in the plurality of nitride semiconductor layers 200, 300, 400, and 500 along the groove 110, and the first n-side electrode 800a is electrically connected to the n-type nitride semiconductor layer 300 through the opening 910. The second n-side electrode 800b is in electrical contact with the n-type nitride semiconductor layer 300 through the groove 110 to form a vertical light emitting device. In this case, the first n-side electrode 800a may be omitted.

The opening 910 corresponding to the groove 110 may be formed by growing the plurality of nitride semiconductor layers 200, 300, 400, and 500 under conditions in which horizontal growth does not occur. For example, as the n-type nitride semiconductor layer 300, trimetalgallium (TMGa), ammonia (NH ₃ ), and SiH ₄ are 365 sccm and 11 slm, respectively. It is supplied at 8.5 slm, and the opening 910 can be formed by growing a GaN layer of about 4 μm at a growth temperature of 1050 ° C., a doping concentration of 3 × ¹⁰ ¹⁸ / cm ³ , and a pressure of 300 to 500 torr (at this time, diameter 30). Circular groove 110 of μm is used).

On the other hand, the light emitting device has a problem that the light emitting device is penetrated by the groove 110 and the opening 910, so that a material such as epoxy, which should be located below the light emitting device, may rise to the top of the light emitting device when the package is made. have.

An object of the present invention is to provide a vertical group III nitride semiconductor light emitting device which solves the above problems.

Another object of the present invention is to provide a vertical group III nitride semiconductor light emitting device having an electrode structure using plating.

To this end, the present invention provides the invention as described in claims 1 to 5. The present invention is particularly suitable for light emitting devices using an insulating substrate such as sapphire. This is because in the case of a light emitting device using a conductive substrate such as SiC, a direct vertical light emitting device can be realized.

According to the group III nitride semiconductor light emitting device according to the present invention, it is possible to overcome the problem of the light emitting device in which two electrodes are formed together on one side, and also to overcome the problem of the vertical light emitting device in which the substrate is removed.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

3 is a view showing an example of a group III nitride semiconductor light emitting device according to the present invention, in which the group III nitride semiconductor light emitting device is epitaxially grown on the substrate 10 and the substrate 10 on which the grooves 91 are formed. ), An n-type nitride semiconductor layer 30 epitaxially grown on the buffer layer 20, an active layer 40 and an active layer 40 grown on the n-type nitride semiconductor layer 30 to generate light by recombination of electrons and holes. A p-type nitride semiconductor layer 50 epitaxially grown thereon, a p-side electrode 60 which is a translucent electrode formed on the p-type nitride semiconductor layer 50, and a p-side bonding pad 70 grown on the p-side electrode 60 And a second n electrically contacting the n-type nitride semiconductor layer 30 through the first n-side electrode 81 and the groove 91 formed on the n-type nitride semiconductor layer 30 exposed by the opening 90. And an auxiliary metal electrode 80 formed on an outer wall of the side electrode 82, the first n-side electrode 81, and the second n-side electrode 82.

The method of forming the groove of the substrate 10 in which the groove 91 is formed uses a laser in the 355 nm wavelength region, and has a circular, elliptical, or various shapes having a diameter of several micrometers to several hundred micrometers while the laser is focused. The polygonal groove 91 may be formed. In addition, the depth of the groove 91 can be adjusted by a laser energy or the like to control the depth of the groove 91 from several micrometers to several hundred micrometers, and the groove 91 may be formed through the substrate 10.

The laser used for the formation of the groove 91 is an yttria-based oxide in which the active medium is neodymium, and the wavelength of the laser was a 532 nm DPSS (Diode Pumped Solid State) laser. At this time, the output of the laser was 10W (10 ~ 100KHz), the drilling speed was 20 ~ 50 holes / sec.

A plurality of group III nitride semiconductors including an n-type nitride semiconductor layer 30 epitaxially grown on the buffer layer 20, an active layer 40 generating light by recombination of electrons and holes, and a p-type nitride semiconductor layer 50. The layer grows so that horizontal growth does not occur by controlling growth conditions, that is, growth temperature, growth rate and growth pressure. As described above, in the plurality of nitride semiconductor layers grown under growth conditions in which the horizontal growth does not occur, an opening 90 starting from the groove 91 formed in the substrate is formed. Meanwhile, the plurality of group III nitride semiconductor layers may be grown to cover the grooves 91, and then the openings 90 may be formed by etching.

After the p-side electrode 60 is formed on the p-type nitride semiconductor layer 50, a process of exposing the n-type nitride semiconductor layer 30 is performed. The method of exposing the n-type nitride semiconductor layer 30 uses dry etching and / or wet etching. In this case, in order to increase the surface area where the n-type nitride semiconductor layer 30 is exposed, it is preferable to etch in a form having one step.

After the p-side electrode 60 is formed, a p-side bonding pad 70 is formed on the p-type nitride semiconductor layer 50 and the p-side electrode 60. In this process, the n-type nitride semiconductor exposed through the opening 90 is exposed. The first n-side electrode 81 is simultaneously formed in the layer 30. The first n-side electrode 81 serves to enlarge an electrode contact area for supplying current to the n-type nitride semiconductor layer 30.

After forming the p-side bonding pad 60 and the first n-side electrode 81, a process of polishing the rear surface of the substrate 10 is performed. Polishing of the substrate 10 causes the groove 91 formed from the first surface of the substrate 10 to be exposed at least to the place where the groove 91 is formed. After the process of polishing the back surface of the substrate 10 is performed, the second n-side electrode 82 is formed. The second n-side electrode 82 is formed below the n-type nitride semiconductor layer 30 through the formed groove 91, and is in electrical contact with the first n-side electrode 81. Preferably, the second n-side electrode 82 is formed on the entire rear surface of the substrate 10 to function as a reflective film.

Electroplating connects the object to be plated to the (-) pole and the plating material to the (+) pole. At this time, the plating material is a solution containing metal ions having good electrical conductivity such as gold, silver, copper, aluminum. When a current is flowed into a solution containing metal ions having good electrical conductivity, a reduction reaction occurs at the negative electrode and an oxidation reaction occurs at the positive electrode. At this time, the metal ions included in the solution form the auxiliary metal electrode 80 due to the reduction reaction on the object to be plated connected to the negative electrode.

In the present invention, the auxiliary metal electrode 80 is formed using a solution containing copper ions. The conditions of the electroplating process were to position the wafer and the plating material horizontally so that the plating was well inside the groove. In addition, by using a magnetic bar inside the container to generate turbulence to make the plating uniform. This is shown in FIG. 4.

In forming the auxiliary metal electrode 80, in order to improve the quality of the auxiliary metal electrode 80, a low current is applied as much as possible to the current applied in the plating process. In the present invention, a current of 150 mA was applied. At this time, the auxiliary metal electrode 80 was formed with an auxiliary metal electrode 80 of about 1700 kW per minute.

By forming the auxiliary metal electrode 80, thermal problems and electrical contact characteristics due to the current drift caused by the thin thickness of the first n-side electrode 81 can be improved by a relatively easy electroplating method. It can increase the reliability. In addition, after the second n-side electrode 82 is formed, the auxiliary metal electrode 80 is formed using the electroplating method, so that the first n-side electrode 81 and the second n-side electrode 82 are smoothly contacted. The electrical properties are improved.

5 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention, in which the group III nitride semiconductor light emitting device has a material such as an epoxy, which is placed under the light emitting device at the time of packaging in the groove 91, to the upper part of the light emitting device. A plated protective film 83 is provided to prevent movement. The passivation layer 83 is formed in the process of forming the auxiliary metal electrode 80 of FIG. 3. The formation of the protective film 83 is made by increasing the probability that the nitride semiconductor layer over the grooves is plated laterally due to the electrolyte solution being driven to the side rather than the top as the plating time passes.

In the plating method, platinum or phosphorus copper (P: 0.04% to 0.06%) metal is used as the anode, and the wafer to be plated is used as the cathode. In this case, the electrolyte solution used is a sulfuric acid-based liquid, and commercially available plating solutions may be used. The temperature at the time of plating was maintained at 25 ℃, generally over 30 ℃ tends to rough the surface of the plating. Adjust the current density so that it is 1 ~ 4A / dm ² . If it is lower than 1A / dm ² , the plating rate is lowered, there is a problem that the plating uniformity is worse, and when higher than 4A / dm ² , the plating rate is increased, but the surface is rough, adhesion is worse. The amount of the plating metal deposited according to the plating thickness is calculated as (volume x density). For this purpose, the uniformity of the plating may be maintained by a method of replenishing the electrolyte depending on the number of plating. In general, the protective layer 83 is selected from one or more of materials such as gold, silver, and copper, which have good adhesion and electrical conductivity with existing metals. The thickness of the protective film 83 is preferably 1 to 15 um. If the thickness of the passivation layer 83 (that is, the auxiliary metal electrode 80) is too thin, the value of the current per electrode unit area is low, so that effects such as contact characteristics are not improved. Mechanical defects such as peeling of the plated metal appear. In the present invention, the temperature of the electrolyte was controlled to supply a current of ² A / dm ^{2 to} a ² inch wafer at about 24 ° C. to a thickness of about 10 μm to 14 μm at a rate of about 0.2 μm per minute.

FIG. 6 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention. The group III nitride semiconductor light emitting device is different from the light emitting devices shown in FIGS. 3 and 5. Prior to the formation, the auxiliary metal electrode 80 formed through plating and filling the groove 91 and a second n-side electrode 82 formed after the plating are included. Through such a configuration, since only the second n-side electrode 82 is positioned on the bottom surface of the light emitting device, the thickness of the electrode added to the substrate may be reduced to facilitate separation into the unit light emitting device. The auxiliary metal electrode 80 has a function of the protective film 83 in FIG. 5 and may be formed in the same process.

7 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention, wherein the protective film 83 is formed by plating using the first n-side electrode 81 as a seed through the opening 90. It is. In this case, the protective layer 83 may fill at least a portion of the groove 91, thereby filling all of the grooves 91 of the second n-side electrode 82 formed by the sputtering method, the E-beam deposition method, or the like. As a result, the thickness becomes excessively thick, thereby improving a problem in the separation process into individual devices. Here, the protective film 83 has a function of improving electrical contact between the first n-side electrode 81 and the second n-side electrode 82 as in FIG. 3.

The passivation layer 83 forms the p-side bonding pad 70 and the first n-side electrode 70, and then, except for a region in which the first n-side electrode 70 is formed using SiO ₂ or photoresistor, It can be formed by forming a plating prevention film and then performing plating. Thereafter, the sapphire substrate 10 is polished to expose the groove 91, and the second n-side electrode 82 is formed to complete the device.

FIG. 8 is a view showing an example of a protective film that is actually implemented according to the present invention shown in FIG. 7, wherein the protective film 83 blocks the groove 91 and extends upward beyond the opening 90. In the present invention, since the anti-plating film is formed in the region except the first n-side electrode 70 and the protective film 83 is formed, the protective film 83 is electrically different from the element regions other than the first n-side electrode 70. Not connected.

1 is a view showing an example of a conventional group III nitride semiconductor light emitting device,

2 is a view showing an example of a vertical group III nitride semiconductor light emitting device (Korean Patent Application No. 2006-35149) to which the present owner is entitled;

3 is a view showing an example of a group III nitride semiconductor light emitting device according to the present invention;

4 is a view for explaining an example of plating according to the present invention;

5 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention;

6 is a view showing another example of a group III nitride semiconductor light emitting device according to the present invention;

7 is a view showing another example of a group III nitride semiconductor light emitting device according to the present invention;

8 is a view showing an example of a protective film actually implemented according to the present invention shown in FIG.

Claims

A substrate having a groove and having a first surface and a second surface;

A plurality of group III nitride semiconductor layers formed on the first side of the substrate and including an active layer that generates light through recombination and a first group III nitride semiconductor layer positioned between the first side and the active layer of the substrate;

An opening formed along the plurality of group III nitride semiconductor layers over the groove;

A first electrode in contact with the first group III nitride semiconductor layer;

An auxiliary metal electrode plated on the first electrode; And,

And a second electrode in electrical contact with the auxiliary metal electrode from the second surface of the substrate.

The method according to claim 1,

The group III nitride semiconductor light emitting device according to claim 2, wherein the second electrode is connected to the first electrode by a groove.

The method according to claim 2,

An auxiliary metal electrode is a group III nitride semiconductor light emitting device, characterized in that formed on the outer wall of the first electrode and the second electrode.

The method according to claim 1,

A group III nitride semiconductor light-emitting device, characterized in that the auxiliary metal electrode fills in at least a part of the groove.

The method according to claim 1,

A group III nitride semiconductor light emitting device comprising: a plated protective film which blocks communication between the opening and the groove and is connected to the auxiliary metal electrode.