KR100924855B1 - Loading table for plasma processing apparatus and plasma processing apparatus - Google Patents

Abstract

Provided are a mounting table for a plasma processing apparatus capable of improving the in-plane uniformity of electric field strength in plasma and performing a plasma treatment having high in-plane uniformity with respect to a substrate, and a plasma processing apparatus including the mounting table.

The mounting table 2 for the plasma processing apparatus 1 is provided so as to cover the conductor member serving as the lower electrode 21 for plasma generation and the upper center portion of the conductor member, and the substrate to be processed (wafer W). The dielectric layer 22 for uniformizing the high frequency electric field applied to the plasma through the layer and the dielectric layer 22, and are divided into a plurality of parts separated from each other in the radial direction of the mounting table so that the high frequency can pass therebetween. An electrostatic chuck in which the electrode film is embedded is provided. Here, the outer edge of the dielectric layer 22 is located just below or outside the inner edge of the separation region 23c between the divided electrode films 23b and 23d, and the divided electrode films 23b and 23d. Are insulated from each other by high frequency.

Description

LOADING TABLE FOR PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING APPARATUS}

The present invention relates to a mounting table for mounting a substrate to be processed, such as a semiconductor wafer subjected to plasma processing, and a plasma processing apparatus including the mounting table.

In the manufacturing process of a semiconductor device, a process gas is often plasma-processed like dry etching or ashing, and a process of a board | substrate is performed in many cases. In the plasma processing apparatus performing such a treatment, for example, a pair of electrodes having a parallel flat plate face up and down, and a high frequency is applied between these electrodes to plasma the processing gas introduced into the apparatus, thereby lowering the electrodes on the lower side. BACKGROUND ART A type of processing a substrate such as a semiconductor wafer (hereinafter referred to as a wafer) mounted thereon is often used.

In recent years, in plasma processing, the processing which requires "low energy, high density plasma" with low ion energy in a plasma and high electron density is increasing. For this reason, the frequency of the high frequency which generates a plasma may become very high, for example, 100 MHz compared with the conventional (for example, about tens of MHz). However, when the frequency of high frequency is increased, the electric field strength tends to be strong at the center of the electrode surface, i.e., the center of the wafer, while the electric field strength tends to be weak at the edge. In this way, if the distribution of the electric field intensity is nonuniform, the electron density of the generated plasma also becomes nonuniform, and the processing speed and the like vary depending on the position in the wafer. Was occurring.

In response to such a problem, Patent Document 1 discloses, for example, a plasma processing apparatus in which a dielectric layer such as ceramics is embedded in a center portion of an opposite surface of one electrode to make the electric field intensity distribution uniform, thereby improving the in-plane uniformity of the plasma treatment. It is described.

The embedding of this dielectric layer will be described with reference to Fig. 13A. When a high frequency is applied from the high frequency power source 93 to the lower electrode 91 of the plasma processing apparatus 9, the high frequency wave propagates the surface of the lower electrode 91 by the skin effect and reaches the upper portion of the surface of the wafer W. Accordingly, a part leaks toward the lower electrode 91 side toward the center, and then flows outward in the lower electrode 91. Here, in the region where the dielectric layer 94 is provided to make the plasma uniform, a TM mode cylindrical cavity resonance in which the high frequency is deeply submerged is generated, and consequently, the plasma is supplied from the wafer W surface to the plasma. The electric field of the center portion can be lowered, and the electric field in the wafer W surface becomes uniform. In the figure, reference numeral 92 denotes an upper electrode, and PZ denotes a plasma.

By the way, plasma processing is often performed in a vacuum atmosphere under reduced pressure, and in such a case, the electrostatic chuck 95 is often used for fixing the wafer W as shown in Fig. 13B. The electrostatic chuck 95 has, for example, a structure in which a conductive electrode film 96 is sandwiched between two dielectric layers on the lower surface side and the upper surface side formed by spraying alumina or the like. The wafer W is electrostatically attracted and fixed by applying a high voltage direct current power to the electrode film 96 by using a high voltage direct current power on the surface of the dielectric layer.

By the way, when the electrostatic chuck 95 is provided on the lower electrode 91 on which the dielectric layer 94 for lowering the potential of the plasma is placed and plasma processing of the wafer W is performed, the high-frequency electrode film 96 of the electrostatic chuck 95 is formed. ) Cannot pass through, resulting in an outward flow in the electrode film 96. In other words, since the electrode film 96 for the electrostatic chuck is present, the dielectric layer 94 cannot be seen from the plasma, and thus the effect of lowering the potential of the plasma in the region where the electrostatic chuck 95 is embedded cannot be exerted. . As a result, the potential of the plasma above the center portion of the wafer W is high, the potential of the edge is low, and the processing speeds are different at the center portion and the edge of the wafer W. Therefore, in-plane unevenness in plasma processing such as etching is caused. It was a factor.

(Patent Document 1) Japanese Unexamined Patent Publication No. 2004-363552: Page 15 Paragraphs 84 to 85

This invention is made | formed based on such a situation, The objective is the mounting table for plasma processing apparatuses which can improve the in-plane uniformity of the electric field intensity in plasma, and can perform the plasma process with high in-plane uniformity with respect to a board | substrate. And it is providing the plasma processing apparatus provided with this mounting table.

The mounting table for a plasma processing apparatus according to the present invention is a mounting table for a plasma processing apparatus for mounting a substrate on a mounting surface, the conductor being connected to a high frequency power source and serving as an electrode for plasma generation or an ion introduction electrode in the plasma. A dielectric layer is provided to cover the member, and a central portion of the upper surface of the conductor member to uniformize the high frequency electric field applied to the plasma through the substrate, and a high frequency can pass therebetween. And an electrostatic chuck embedded with a plurality of divided electrode films spaced apart from each other in the radial direction of the mounting table, wherein an outer edge of the dielectric layer is located directly below or outside the inner edge of the separation region between the divided electrode films. The divided electrode films are insulated from each other by high frequency.

The dielectric layer may be stacked in a plurality of stages such that the outer edge thereof is inward as the lower one, and the number of divisions of the electrode film may be at least one larger than the number of stages of the dielectric layer.

In addition, the same type of mounting table is provided with an electrostatic chuck in which an electrode film with a hole is formed at a position corresponding to the center of the mounting table, and the dielectric layer may be disposed below the hole.

Here, the dielectric layer may be formed in a cylindrical shape to generate a TM mode cylindrical cavity resonance, or may be configured such that the thickness thereof is smaller than the center portion. The frequency of the high frequency power supplied from the high frequency power supply is preferably 13 MHz or more.

According to the present invention, the separation region is provided between the divided electrode films, or the hole is formed in the electrode film at a position corresponding to the center portion of the mounting table, so that the high frequency waves propagating on the substrate to be processed, such as a wafer, are these separation regions. Or through the hole. The high frequency that has exited these regions can cause the cylindrical cavity resonance of the TM mode to enter the lower portion of the dielectric layer for uniformizing the high frequency electric field applied to the plasma through the substrate to be processed. As a result, even when the electrostatic chuck is provided, the cylindrical cavity resonance of the TM mode can be generated by utilizing the dielectric layer, so that it is possible to lower the electric field of the central portion supplied to the plasma from the surface of the substrate to be processed. The area | region where the electric field intensity of a shape electric field intensity distribution is large can be planarized. As a result, in-plane uniformity with respect to a plasma process, for example, an etching process, can be improved.

EMBODIMENT OF THE INVENTION Embodiment which applied the mounting table which concerns on this invention to the plasma processing apparatus as an etching apparatus is demonstrated, referring FIG. 1 illustrates an example of a reactive ion etching (RIE) plasma processing apparatus 1. The plasma processing apparatus 1 includes, for example, a processing container 11 including a vacuum chamber having an airtight space inside, a mounting table 2 disposed at the bottom center in the processing container 11, and a mounting table ( The upper electrode 31 provided above 2) is provided so as to face this mounting table 2.

The processing container 11 consists of a cylindrical upper chamber 11a with a small diameter, and a cylindrical lower chamber 11b with a large diameter. The upper chamber 11a and the lower chamber 11b communicate with each other, and the entire processing container 11 is airtight. In the upper chamber 11a, the mounting table 2, the upper electrode 31, etc. are stored, and in the lower chamber 11b, the support case 17 which supports the mounting table 2, and contains piping etc. Is stored. The exhaust device 14 is connected to the exhaust port 12 of the bottom face of the lower chamber 11b via the exhaust pipe 13. A pressure regulator (not shown) is connected to the exhaust device (14), and the pressure regulator is configured to evacuate the entire inside of the processing container (11) in accordance with a signal from a controller (not shown) to maintain the desired vacuum degree. . On the other hand, the carrying in / out port 15 of the wafer W which is a to-be-processed board | substrate is provided in the side surface of the upper chamber 11a, This carrying in / out port 15 is made possible to open and close by the gate valve 16. As shown in FIG. The processing container 11 is made of a conductive member such as aluminum and is grounded.

The mounting table 2 includes, for example, a lower electrode 21 for plasma generation, which is a conductor member made of aluminum, and a dielectric layer 22 embedded to cover the center of the upper surface of the lower electrode 21 to uniformly adjust the electric field. And the electrostatic chuck 23 for fixing the wafer W are stacked in this order from the bottom. The lower electrode 21 is fixed to the support base 21a provided on the support case 17 with the insulating member 24 interposed therebetween, and is fully electrically floating with respect to the processing container 11.

In the lower electrode 21, a coolant flow path 26 for flowing a coolant is formed, and the coolant flows through the coolant flow path 26 so that the lower electrode 21 is cooled, and the wafer W mounted on the mounting surface is formed. It is configured to cool to a desired temperature.

The electrostatic chuck 23 is also provided with a through hole 25 for emitting a thermally conductive backside gas for enhancing heat transfer between the mounting surface and the back surface of the wafer W. As shown in FIG. The through hole 25 communicates with a gas flow passage 27 formed in the lower electrode 21 or the like, and is a backside gas such as helium (He) supplied from a gas supply unit (not shown) via the gas flow passage 27. Is to be released.

Further, the lower electrode 21 is, for example, a first high frequency power supply 41a for supplying a high frequency with a frequency of 100 MHz, and a second frequency supply having a frequency lower than the first high frequency power supply 41a, for example, for supplying a high frequency with 3.2 MHz. Two high frequency power supplies 41b are connected via matching devices 42a and 42b, respectively. The high frequency supplied from the first high frequency power supply 41a plays a role of plasmaizing the processing gas described later, and the high frequency supplied from the second high frequency power supply 41b applies ions in the plasma by applying a bias power to the wafer W. Is introduced into the wafer W surface.

In addition, a focus ring 28 is disposed on the upper outer peripheral portion of the lower electrode 21 so as to surround the electrostatic chuck 23. The focus ring 28 adjusts the plasma state of the region outside the edge of the wafer W, for example, widens the plasma than the wafer W, and serves to improve the uniformity of the etching rate in the wafer surface.

The baffle plate 18 is provided in the lower outer side of the support stand 21a so that the mounting table 2 may be enclosed. The baffle plate 18 flows the processing gas in the upper chamber 11a through the gap formed between the baffle plate 18 and the wall of the upper chamber 11a to the lower chamber 11b to adjust the flow of the processing gas. It plays a role as a rectifying plate.

In addition, the upper electrode 31 is formed in a hollow shape, and a plurality of gas supply holes 32 for distributing and supplying the processing gas into the processing container 11 are formed on the lower surface thereof, for example, by being evenly distributed. The gas shower head is constituted. The gas introduction pipe 33 is provided in the center of the upper surface of the upper electrode 31, This gas introduction pipe 33 penetrates through the center of the upper surface of the process container 11, and is connected to the process gas supply source 35 upstream. . The processing gas supply source 35 has a processing gas supply amount control mechanism (not shown), and the plasma processing apparatus 1 can control the supply interruption and increase / decrease of the processing gas supply amount. The upper electrode 31 is fixed to the wall of the upper chamber 11a, whereby a conductive path is formed between the upper electrode 31 and the processing container 11.

In addition, two multipole ring magnets 47a and 47b are disposed around the upper chamber 11a above and below the carry-in port 15. In the multipole ring magnets 47a and 47b, a plurality of anisotropic segment bar magnets are attached to the casing of the ring-shaped magnetic body, and the plurality of adjacent segment bar magnets are arranged so that the directions of the adjacent plurality of segment bar magnets are opposite to each other. As a result, magnetic lines of force are formed between adjacent segment bar magnets, and magnetic fields are formed in the periphery of the processing space between the upper electrode 31 and the lower electrode 21, thereby confining the plasma in the processing space. In addition, a device configuration without the multipole ring magnets 47a and 47b may be employed.

By the above-mentioned each apparatus structure, a pair of parallel flat electrode which consists of the lower electrode 21 and the upper electrode 31 is formed in the processing container 11 (upper chamber 11a) of the plasma processing apparatus 1. do. After adjusting the inside of the processing container 11 to a predetermined pressure, the processing gas is converted into plasma by introducing the processing gas and supplying a high frequency from the high frequency power supplies 41a and 41b. The high frequency is the lower electrode 21 → plasma → A path consisting of the upper electrode 31 → the wall of the processing vessel 11 → earth flows. By this action of the plasma processing apparatus 1, etching with plasma is performed on the wafer W fixed on the mounting table 2.

Next, with reference to FIG. 2, FIG. 3, the mounting table 2 which concerns on this embodiment is explained in full detail. In addition, in the longitudinal side view of the mounting table 2 shown in FIG. 2, description of the refrigerant | coolant flow path 26, the through-hole 25 of backside gas, etc. is abbreviate | omitted.

The dielectric layer 22 is embedded in the upper center portion of the lower electrode 21 as shown in Fig. 2A. The dielectric layer 22 has a function of lowering the potential of the plasma in the region where the dielectric layer 22 is embedded. The dielectric layer 22 is made of, for example, ceramics having a relative dielectric constant of 10 having alumina (Al ₂ O ₃ ) as a main component. As shown in FIG. 2B, the dielectric layer 22 has a disk shape having a thickness t _D = 5 mm and a diameter Φ _D = 240 mm, for example.

Next, the electrostatic chuck will be described. As shown in Fig. 2A, the electrostatic chuck 23 has a structure in which an electrode film is provided between the lower surface side and the upper insulating film 23a formed by thermal spraying alumina or the like, for example. The electrode film is made of an electrode material having a resistivity of approximately 1.0 × 10 ⁻⁴ μm. In the present embodiment, as shown in FIG. 3A, the electrostatic chuck 23 has the first electrode film 23b with the circular first electrode film 23b interposed therebetween and the separation region 23c without the electrode film therebetween. ) Is composed of an annular second electrode film 23d provided so as to surround (). That is, these electrode films 23b and 23d are divided into a plurality of parts spaced apart from each other in the radial direction of the mounting table 2. Here, for example, the first electrode film 23b has a diameter Φ _C1 = 158 mm, the second electrode film 23d has an inner diameter Φ _C2 = 162 mm and an outer diameter Φ _C3 = 298 mm.

As shown in Fig. 2A, the electrode films 23b and 23d are connected to the high impedance circuits 43a and 43b, respectively, to form high-frequency independent circuits. The common switch 44 and the resistor 45 Is connected to the high-voltage DC power supply 46 via. When high voltage direct current is applied from the high voltage direct current power supply 46 to the electrode films 23b and 23d, the wafer W is placed on the upper surface of the electrostatic chuck 23 serving as the mounting surface by the Coulomb force generated on the surface of the electrostatic chuck 23. Is electrostatically adsorbed. The high impedance circuits 43a and 43b are circuits (low pass filter: LPF) which become high impedance with respect to the high frequency supplied to the lower electrode 21. In the present embodiment, the first and second electrode films 23b and 23d are provided. Is connected to a common high voltage direct current power supply 46, and is provided in order to insulate between these electrode films 23b and 23d with respect to a high frequency. In addition, the method of insulating the electrode films 23b and 23d with respect to a high frequency is not limited to the above-mentioned example, For example, even if a high voltage DC power supply and a high impedance circuit LPF are provided in each of the electrode films 23b and 23d, good. In addition, the two electrode films 23b and 23d are connected by the pattern of the electrode film serving as the inductor component. For example, only the outer electrode film 23 is connected to the high voltage DC power supply 46 via the high impedance circuit 43a. By connecting, you may comprise so that each electrode film 23b, 23d may be insulated with respect to a high frequency.

In the state where the lower electrode 21, the dielectric layer 22, and the electrostatic chuck 23 are stacked, the positional relationship between the dielectric layers 22 and the electrode films 23b and 23d of the electrostatic chuck 23 is shown in FIG. 2B. As shown in the enlarged longitudinal cross-sectional view of the cross section, the outer edge of the dielectric layer 22 is set to be located outside the outer edge of the electrode film 23b. That is, when the vertical projection surfaces of the electrode films 23b and 23d which are the same as the vertical projection surface of the dielectric layer 22 with respect to the mounting surface of the wafer W are viewed from the mounting surface side, as shown in Fig. 3 (c), the outer side of the dielectric layer 22 is shown. The edge is located outside the inner edge of the separation region 23c between the divided electrode films 23b and 23d.

The operation of the mounting table 2 according to the above-described embodiment will be described below. The high frequency current supplied from the first high frequency power supply 41a and propagating through the surface of the lower electrode 21 is partially moved from the surface of the wafer W toward the electrostatic chuck 23 as shown in FIG. 4 (a). Leaks. At this time, the electrode films 23b and 23d embedded in the electrostatic chuck 23 are divided and embedded in a state in which they are separated from each other in the radial direction, so that a high frequency wave is applied to the dielectric layer 22 as indicated by arrows in the figure. It is possible to reach. In the region where the dielectric layer 22 is embedded, the high frequency is deeper than other regions, and the potential of the plasma in the region can be lowered.

By the above-described action, even in the mounting table 2 of the type which fixes the wafer W by the electrostatic chuck 23, the action of lowering the potential of plasma using the dielectric layer 22 is performed by the electrode films 23b and 23d. Is not damaged by its presence. As a result, when the effect of the dielectric layer 22 is not exerted, the peak of the electric field intensity distribution which becomes acidic can be flattened by exhibiting the effect, so that high in-plane uniformity can be obtained with respect to the electron density in the plasma. It can be, for example, it is possible to improve the in-plane uniformity for the plasma treatment such as etching treatment.

In this case, the outer edge of the dielectric layer 22 may be located outside the inner edge of the separation region 23c in order to achieve the effect of making the electric field uniform by the dielectric layer 22. Therefore, as shown in FIG. 5, the diameter of the dielectric layer 22 is shortened, and the mounting table 2 of the structure in which the outer edge of the dielectric layer 22 is located between the inner edge and outer edge of the separation region 23c is shown. ) Is also included in the technical scope of the present invention.

Next, the structure of the mounting table 2 which concerns on Embodiment 2 is demonstrated. Embodiment 2 differs from Embodiment 1 in that the outer edge of the dielectric layer 22 is located just below the inner edge of the separation region 23c, and is located outside the inner edge of the separation region 23c.

Specifically, for example, as shown in FIG. 6, the sizes of the dielectric layer 22 and the first electrode film 23b are formed to be substantially the same, and the mounting table 2 is assembled so that their center portions coincide. have. As a result, the outer edge of the dielectric layer 22 is located just below the inner edge of the separation region 23c.

As described above, since the outer edge of the dielectric layer 22 is located directly below the inner edge of the separation region 23c, as shown by the arrow in FIG. 4 (b), the high frequency from the surface of the wafer W is increased. ) Can be reached. In the region where the dielectric layer 22 is embedded, the high frequency is deeper than other regions, and the potential of the plasma in the region can be lowered. In addition, in order to form a uniform plasma, the electrostatic chuck 23 may not have the 2nd electrode film 23d.

In addition, the dielectric layer for lowering the potential of the plasma is not limited to one stage, and as shown in FIG. 7, for example, the second dielectric layer 22b is further embedded below the first dielectric layer 22a to form the second dielectric layer. The mounting table 2 may be configured such that the outer edge of the 22b is inward of the outer edge of the first dielectric layer 22a. As a result, when the effect of the dielectric layer is not exerted, the high frequency can be locked more deeply in the region where the peak of the electric field intensity distribution becoming an acid form becomes larger, thereby making the electric field intensity distribution flatter. In the case where the dielectric layers 22a and 22b are formed in two stages, the electrode films 23b, 23d and 23f are divided into three so as to have two separation regions 23c and 23e so that each of the dielectric layers 22a and 22b is separated. The outer edge may be configured to be located directly below or outside the inner edge of each of the separation regions 23c and 23e. The number of steps of stacking the dielectric layers is not limited to two steps, but may be a structure of three or more steps. In this case, the number of divisions of the electrode film may be at least one larger than the number of stages of the dielectric layer.

In addition, as a modification of the embodiment, the electrode film 23b of the electrostatic chuck is formed in a shape in which a hole is formed at a position corresponding to the center of the mounting table as shown in FIG. 8, and the dielectric layer 22 is located below this hole. It is good also as a structure.

In addition, the structure of the dielectric layer 22 is not limited to the cylindrical shape shown in embodiment mentioned above, For example, it forms a dome shape as shown to FIG. 9 (a), and a cone as shown to FIG. 9 (b). It may be a shape. Thus, by making the thickness of the dielectric layer 22 smaller than a center part, the electric field intensity of a center part can be made weaker than a center part, and it can be made more flat distribution. At this time, the electrode film may be divided into three or more to provide a plurality of separation regions.

In addition, since the general coefficient of linear expansion of the ceramics used as the dielectric layer is 2 × 10 ⁻⁶ / ° C. to 11 × 10 ⁻⁶ / ° C., it is preferable to use the one whose linear expansion coefficient of the conductor member serving as the electrode is also close to this range. Do.

EXAMPLE

(Simulation 1)

The parallel plate type plasma processing apparatus shown in FIG. 1 was modeled, and simulation was performed to estimate the distribution of the electric field strength on the wafer.

A. Simulation Conditions

Resistivity of the electrode films 23b and 23d: 1.0 × 10 ⁻⁶ μm

Resistivity of Wafer W: 5.0 × 10 ⁻² μm

   Plasma Resistivity: 1.5Ωm

   Dielectric constant ε of dielectric layer 22: 10

   Applied power: 2 ㎾ (2 conditions of frequency 40MHz, 100MHz)

Under the above conditions, the electric field intensity distribution in the radial direction of the wafer W mounted on the mounting surface of the mounting table 2 according to the following Examples and Comparative Examples was simulated.

(Example 1)

As shown to Fig.10 (a), the mounting table 2 which has a structure similar to what was demonstrated in Embodiment 2 was simulated.

Here, the diameter Φ _C1 = 158 mm of the first electrode film 23b, the second electrode film 23d was an inner diameter Φ _C2 = 162 mm, an outer diameter Φ _C3 = 298 mm, and the diameter Φ _D = 158 mm of the dielectric layer.

(Example 2)

As shown in FIG. 10 (b), the mounting table 2 having the same configuration as that described in Embodiment 1 was simulated.

Here, the sizes of the first electrode film 23b and the second electrode film 23d were the same as those of the first embodiment, and the diameter of the dielectric layer 22 was set to Φ _D = 240 mm.

(Comparative Example 1)

As shown in FIG.10 (c), the mounting base 2 of the structure in which the dielectric layer 22 is not embedded and the electrode film 23b of the electrostatic chuck 23 is not divided | segmented was performed.

(Comparative Example 2)

As shown in Fig. 10 (d), the mounting table 2 having the structure in which the dielectric layer 22 is embedded but the electrode film 23b is not divided is simulated. In addition, the diameter of the dielectric layer 22 was Φ _D = 160 mm.

(Comparative Example 3)

As shown in Fig. 10E, the electrode films 23b and 23d are divided similarly to the first embodiment and the second embodiment, but since the diameter of the dielectric layer 22 is smaller than that of the electrode film 23b, the dielectric layer 22 The outer edge of () was simulated with respect to the mounting table 2 of the structure where the outer edge is located inward of the inner edge of the separation region 23c.

Here, the sizes of the first electrode film 23b and the second electrode film 23d were the same as those in the first embodiment, and the diameter of the dielectric layer 22 was set to Φ _D = 100 mm.

B. Simulation Results

The simulation result of the electric field intensity distribution in each Example and a comparative example is shown in FIG. Fig. 11A shows a simulation result when the applied high frequency frequency is 40 MHz. Similarly, Fig. 11B shows the result when the frequency is 100 MHz. The horizontal axis of each graph shows the distance [mm] from the center in the radial direction when the center of the wafer W is made "0". The vertical axis represents "electric field strength (= maximum field strength E _max at each position obtained as a result of the simulation / simulation results at all positions)." Each simulation result plots Example 1 by a triangle (△), Example 2 by inverse triangle (▼), Comparative Example 1 by rhombus (◇), Comparative Example 2 by square (■), and Comparative Example 3 Plot each as (●).

According to the results of the simulation, in Comparative Example 1 in which the dielectric layer 22 was not embedded, the electric field intensity distribution in which the electric field strength of the center region of the wafer W was maximized under both conditions of high frequency of 40 MHz and 100 MHz was obtained. (FIG. 11 (a), (b) (◇)). In addition, although the dielectric layer 22 is embedded, Comparative Example 2 (■) in which the electrode film 23b is not divided, and the electrode films 23b and 23d are divided, the diameter of the dielectric layer 22 is the electrode film. The simulation result of Comparative Example 3 (●) smaller than that of (23b) also has an electric field intensity distribution in which the electric field strength of the center region of the wafer W is maximized in the same manner as in Comparative Example 1. As a result, since the electrode film 23b of the electrostatic chuck is present between the wafer W and the dielectric layer 22, the dielectric layer 22 is not visible, and the dielectric layer 22 exhibits the effect of lowering the potential of plasma. It can be said that it shows that it becomes impossible.

For these comparative examples, in the simulation results of Comparative Example 1 corresponding to the second embodiment, when the frequency of the high frequency is 40 MHz, the electric field strength in the region near the outer edge where the distance from the center of the wafer W is about 120 mm Is the maximum electric field intensity distribution ((Δ) in Fig. 11 (a)). In addition, when the frequency of the high frequency is 100 MHz, the electric field strength is maximized in two regions, the center region of the wafer W and the region near the outer edge where the distance from the center of the wafer W is about 100 mm. () of b). In addition, the simulation result of Example 2 corresponding to Embodiment 1 also has an electric field distribution substantially the same as that of Example 1 at each frequency (40 MHz, 100 MHz) (see Figs. 11A and 11B). ▼)).

In the simulation results of Examples 1 and 2, the electric field intensity distribution in which only the electric field intensity of the center region of the wafer W seen in Comparative Examples 1 to 3 is increased is not seen. This is so that even if there is an electrode film 23b of the electrostatic chuck between the wafer W and the dielectric layer 22, the dielectric layer 22 embedded in the lower electrode 21 with the separation region 23c therebetween is visible from the plasma. It can be considered that the dielectric layer 22 can exhibit the effect of lowering the potential of the plasma in the region where the dielectric layer 22 is embedded.

(Experiment 1)

The effect of the difference in the structure of each mounting table 2 on the actual plasma processing was created, and the mounting table 2 which has a structure as shown in Example 1, 2 of (Simulation 1), and Comparative Examples 2, 3 was created. Investigated.

A. Experimental Method

In the experiment, those in which the mounting tables 2 shown in Examples 1 and 2 and Comparative Examples 2 and 3 of FIG. 10 were inserted into the parallel plate type plasma processing apparatus shown in FIG. 1 were used. And the wafer W which apply | coated the resist film was mounted on the mounting surface of the mounting table 2, plasma was produced and the ashing process of the resist film was performed. The pressure in the processing container 11 was 0.7 kPa (5 mTorr), the processing gas was O ₂ gas (supplied at 100 sccm), and the high frequency for plasma generation was set at a frequency of 100 MHz and 2 kPa. After the predetermined time ashing treatment, the film thickness of the resist film was measured at a predetermined measurement point on the wafer W, and the ashing speed per unit time was calculated.

B. Experimental Results

FIG. 12 shows the results of plotting the ashing speed calculated from the experimental results at each measurement point on the wafer W. FIG. 12 (a) and 12 (b) show the experimental results for the mounting table 2 of Comparative Example 2 and Comparative Example 3, respectively. FIGS. 12 (c) and 12 (d) show the mounting of Example 1 and Example 2. FIG. The experimental results for the table 2 are shown, respectively. Here, in the case where the coordinate axis is set in the direction shown in Fig. 10 (a), the horizontal axis of each graph is the X-axis direction (left and right directions along the drawing, and the right side is positive), and the Y-axis direction (in front of itself along the drawings). The distance [mm] from the center of the wafer W to the inner direction and the inner side is defined. In addition, the vertical axis | shaft has shown the ashing speed [nm / min]. For each experimental result, the ashing speed in the X-axis direction is plotted with a rhombus and the Y-axis direction is plotted with a triangular (Δ). In addition, the number described in the graph has shown the average value of the ashing speed in each experimental condition, and the relative change width [%] of the experimental result with respect to this average value.

According to the experimental results, under all conditions (Comparative Example 2, Comparative Example 3, Example 1, Example 2), the difference in the ashing speed due to the difference in the axial direction between the X axis and the Y axis is not seen, and the ashing speed is measured in the wafer. There was a symmetrical distribution in the radial direction with respect to the center of W. As shown to Fig.12 (a), (b), in the experiment result of the comparative example 2 and the comparative example 3, the ashing speed of the center area | region of the wafer W became the largest distribution. This is because the electrode film 23b is not divided and the separation region 23c is not formed, so that the dielectric layer 22 cannot be seen from the plasma, and the action of lowering the potential of the plasma by the dielectric layer 22 is caused. It can be said that it was not exercised.

In contrast, in the experimental results of Examples 1 and 2, the peak of the ashing speed cannot be seen in the center region of the wafer W as shown in Figs. 12 (c) and (d). Moreover, the change width of the ashing speed is also reduced by approximately half compared with Comparative Example 2 or Comparative Example 3 (27.6% to 28.5%) (12.7% to 14.7%). This tends to coincide with the simulation results of the electric field intensity distribution for each of the above-described embodiments. Even if there is an electrode film 23b of the electrostatic chuck between the wafer W and the dielectric layer 22, the separation region 23c is interposed therebetween. The dielectric layer 22 embedded in the lower electrode 21 can be seen from the plasma, and the action of lowering the potential of plasma in the region where the dielectric layer 22 is embedded is exerted, and the effect of the dielectric layer 22 is not exerted. In this case, it can be said that it is the result which was able to flatten the peak of the electric field intensity distribution which becomes a mountain shape. In addition, the conditions which can acquire such an effect are not limited to the case where the high frequency power of the frequency illustrated by simulation or experiment is applied. For example, the same effect can be obtained even when high frequency power with a frequency of 13 MHz or 27 MHz is applied.

BRIEF DESCRIPTION OF THE DRAWINGS The longitudinal side view which shows an example of the plasma processing apparatus provided with the mounting base which concerns on Embodiment 1 of this invention,

2 is a vertical side view showing an example of the mounting table according to the first embodiment;

3 is an explanatory diagram for explaining the shape of an electrode film of an electrostatic chuck, the shape of a dielectric layer for lowering the potential of plasma, and the like;

4 is an explanatory diagram for explaining the operation of the mounting table according to the embodiment;

5 is an explanatory diagram showing a modification of the mounting table according to the first embodiment;

6 is a longitudinal side view showing an example of the mounting table according to the second embodiment;

7 is an explanatory diagram showing an example of a mounting table in which a plurality of dielectric layers are laminated;

8 is an explanatory diagram for illustrating a modification of the electrode film according to the embodiment;

9 is an explanatory diagram for explaining a modification of the dielectric layer according to the embodiment;

10 is a vertical side view showing the configuration of each mounting table in which the electric field intensity distribution is simulated;

11 is a characteristic diagram showing a result of an example performed to confirm the effect of the present invention;

12 is a characteristic diagram showing a result of an example performed to confirm the effect of the present invention;

It is explanatory drawing for demonstrating the prior art example of the plasma processing apparatus provided with the mounting table.

Explanation of symbols for the main parts of the drawings

PZ: Plasma W: Wafer

1 plasma processing apparatus 2 mounting table

9 plasma processing apparatus 11 processing container

11a: upper chamber 11b: lower chamber

12 exhaust port 13 exhaust pipe

14 exhaust device 15 inlet and outlet

16 gate valve 17 support case

18 baffle plate 21 lower electrode

21a: support 22: dielectric layer

22a: first dielectric layer 22b: second dielectric layer

23 electrostatic chuck 23a insulating film

23b: electrode film (first electrode film) 23c: separation region (first separation region)

23d: electrode film (second electrode film) 23e: second separation region

23f: third electrode film 24: insulating member

25 through hole 26 refrigerant channel

27: gas passage 28: focus ring

31 upper electrode 32 gas supply hole

33 gas introduction pipe 35 process gas supply source

41a: High frequency power supply (first high frequency power supply)

41b: high frequency power supply (second high frequency power supply)

42a, 42b: matcher 43a, 43b: high impedance circuit

44 switch 45 resistance

46: high voltage DC power 47a, 47b: multi-pole ring magnet

91: lower electrode 92: upper electrode

93: high frequency power supply 94: dielectric layer

95: electrostatic chuck 96: electrode film

97: high voltage DC power

Claims (7)

As a mounting table for a plasma processing apparatus for mounting a target substrate on a mounting surface, A conductor member connected to a high frequency power source and serving as an electrode for plasma generation or ion introduction in the plasma; A dielectric layer provided to cover the central portion of the upper surface of the conductor member and for uniformizing the high frequency electric field applied to the plasma through the substrate to be processed; An electrostatic chuck laminated on the dielectric layer and embedded with a plurality of divided electrode films spaced apart from each other in the radial direction of the mounting table so that high frequencies can pass therebetween. Provided with The outer edge of the dielectric layer is located directly below or outside the inner edge of the separation region between the divided electrode films, The divided electrode films are insulated from each other by high frequency, The dielectric layer is formed in a cylindrical shape Mounting table for plasma processing apparatus, characterized in that. As a mounting table for a plasma processing apparatus for mounting a target substrate on a mounting surface, A conductor member connected to a high frequency power source and serving as an electrode for plasma generation or ion introduction in the plasma; A dielectric layer provided to cover the central portion of the upper surface of the conductor member and for uniformizing the high frequency electric field applied to the plasma through the substrate to be processed; An electrostatic chuck laminated on the dielectric layer and embedded with a plurality of divided electrode films spaced apart from each other in the radial direction of the mounting table so that high frequencies can pass therebetween. Provided with The outer edge of the dielectric layer is located directly below or outside the inner edge of the separation region between the divided electrode films, The dielectric layer is laminated in a plurality of stages so that the outer edge is inward as the bottom one, The divided electrode films are insulated from each other with respect to a high frequency, and the number of divisions of the electrode films is at least one greater than that of the dielectric layers. Mounting table for plasma processing apparatus, characterized in that. As a mounting table for a plasma processing apparatus for mounting a target substrate on a mounting surface, A conductor member connected to a high frequency power source and serving as an electrode for plasma generation or ion introduction in the plasma; A dielectric layer provided to cover the central portion of the upper surface of the conductor member and for uniformizing the high frequency electric field applied to the plasma through the substrate to be processed; An electrostatic chuck stacked on this dielectric layer and having an electrode film embedded therein with a hole formed at a position corresponding to the center of the mounting table so that high frequency can pass therethrough. Provided with The dielectric layer is located below the hole The dielectric layer is formed in a cylindrical shape Mounting table for plasma processing apparatus, characterized in that. delete The method of claim 2, The thickness of the dielectric layer is smaller on the edge portion than the center portion, the mounting table for a plasma processing apparatus. The method according to any one of claims 1 to 3, The high frequency frequency supplied from the said high frequency power supply is 13 MHz or more, The mounting table for plasma processing apparatuses characterized by the above-mentioned. A processing container in which plasma processing is performed on the substrate to be processed, A processing gas introduction unit for introducing a processing gas into the processing container; The mounting table for plasma processing apparatus in any one of Claims 1-3 provided in the said processing container, An upper electrode provided above the mount so as to face the mount; Means for evacuating the interior of the processing vessel Plasma processing apparatus comprising the.

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