JP5186394B2 - Mounting table and plasma etching or ashing device - Google Patents

Description

The present invention relates to a mounting table on which a substrate subjected to plasma processing is mounted and a plasma etching or ashing apparatus including the mounting table, and more particularly to a mounting table in which a dielectric layer is embedded.

  In the manufacturing process of a semiconductor device, plasma processing such as dry etching or ashing is performed on a semiconductor wafer (hereinafter simply referred to as “wafer”) using plasma generated from a processing gas. In a plasma processing apparatus that performs such plasma processing, for example, a pair of parallel plate-like electrodes are disposed so as to face each other, and high-frequency power is applied between the facing electrodes to generate plasma from the processing gas. When the plasma processing is performed, the wafer is placed on the lower electrode as a mounting table.

  In recent years, in plasma processing, plasma with low ion energy and high electron density is often used. Correspondingly, the frequency of the high-frequency power applied between the electrodes is conventional (for example, about 10 MHz or so). Compared to, for example, 100 MHz is very high. However, when the frequency of the applied high frequency power is increased, the electric field strength increases in the central portion of the electrode surface, that is, the space facing the central portion of the wafer, while the electric field strength is increased in the space facing the peripheral portion of the electrode surface. It has been confirmed that the strength of is weakened. When the intensity distribution of the electric field becomes non-uniform in this way, the electron density of the generated plasma also becomes non-uniform. For example, in dry etching using ions, the etching rate varies depending on the position of the wafer. There was a problem that it was difficult to ensure the uniformity inside.

  To solve this problem, for example, by embedding a dielectric layer such as ceramics in the center of the opposing surface of the lower electrode (mounting table), the electric field strength distribution is made uniform, and the in-plane uniformity of the plasma treatment is achieved. Has been proposed (see, for example, Patent Document 1).

  As shown in FIG. 9A, in the plasma processing apparatus 90, when high-frequency power is applied from the high-frequency power source 92 to the lower electrode 91, the high-frequency current that has propagated through the surface of the lower electrode 91 by the skin effect and reached the upper part is A part of the surface of the wafer W leaks from the central portion of the surface of the wafer W to the lower electrode 91 side, and then flows outward in the lower electrode 91 while moving toward the central portion along the surface of W. Here, in the portion where the dielectric layer 93 is buried, the high-frequency current can dive deeper than the other portions, and thereby, TM mode cavity cylindrical resonance occurs in the central portion of the lower electrode 91. As a result, the electric field strength in the space facing the central portion of the wafer W can be lowered, and the electric field strength distribution in the space facing the wafer W can be made uniform.

  Normally, since the plasma processing is performed in a reduced pressure atmosphere, an electrostatic chuck 94 is used for fixing the wafer W in the plasma processing apparatus 90 as shown in FIG. 9B. In the electrostatic chuck 94, a conductive electrode film 95 is sandwiched between a lower member and an upper member made of a dielectric, for example, alumina. In the plasma processing, a high-voltage DC power is applied from the high-voltage DC power source 96 to the electrode film 95, and the wafer W is electrostatically adsorbed and fixed by a Coulomb force generated on the upper member surface of the electrostatic chuck 94.

  By the way, each component of the plasma processing apparatus 90 is considered to constitute an electric circuit related to a high-frequency current. On the other hand, since the wafer W is made of a semiconductor such as silicon, the wafer W is also considered to be a component of the electric circuit. Here, when the wafer W is electrostatically attracted to the electrostatic chuck 94, the wafer W and the electrode film 95 are parallel to each other. Therefore, the wafer W and the electrode film 95 are arranged in parallel in the electric circuit. It is thought that it corresponds to the resistance.

  Therefore, although the value of the high-frequency current flowing through the wafer W depends on the balance between the resistance value of the wafer W and the resistance value of the electrode film 95, the resistance value of the electrode film 95 is extremely large or extremely small. However, the semiconductor device on the wafer W has a problem that the gate oxide film is charged up and deteriorates (charge-up damage occurs).

  Therefore, the present applicant grasps the relationship between the resistance value of the electrode film 95 and the occurrence rate of charge-up damage through experiments, and the range of the resistance value of the electrode film 95 where charge-up damage does not occur, specifically, skin depth and The range of surface resistivity (sheet resistivity) was found (for example, refer to Patent Document 2).

JP 2004-363552 A Japanese Patent Application No. 2008-029348

  However, in order to strictly manage the resistance value range, it is necessary to strictly manage the upper and lower limits of the film thickness of the electrode film 95. On the other hand, it is necessary to contact the electrode film 95 with a power supply pin for applying high-voltage DC power, and it is necessary to strictly manage the structure for that purpose. That is, when manufacturing the mounting table, it is necessary to strictly manage not only the upper and lower limits of the film thickness of the electrode film 95 but also the contact structure for contacting the power supply pins. As a result, the mounting table is easily manufactured. There is a problem that can not be.

An object of the present invention is to provide a mounting table and a plasma etching or ashing apparatus that can be easily manufactured while preventing deterioration of an insulating film in a semiconductor device on a substrate.

To achieve the above object, table for plasma etching or ashing apparatus of claim 1, wherein the substrate is a table for plasma etching or ashing apparatus is mounted, the high frequency power source and for generating a plasma A conductor member connected to a high-frequency power source for ion attraction; a dielectric layer embedded in a central portion of the upper surface of the conductor member; an electrostatic chuck placed on the dielectric layer; and the substrate And the conductive film disposed between the dielectric layers, the electrostatic chuck has an electrode film connected to a high-voltage DC power source, and the conductive film has a condition “δ ₁ / z ₁ ≧ 85 and ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ ”, and the electrode film satisfies the condition“ δ ₂ / z ₂ ≧ 85 ”. However, δ ₁ = (ρ _v1 / (μ ₁ πf)) ^1/2 , z ₁ : thickness of the conductive film, δ ₁ : the conductivity with respect to the high frequency power applied from the high frequency power source for plasma generation. Skin depth of the film, f: frequency of the high-frequency power applied from the high-frequency power source for generating plasma, π: circumference, μ ₁ : permeability of the conductive film, ρ _v1 : specific resistance of the conductive film, ρ _{s1 is} the surface resistivity of the conductive film, δ ₂ = (ρ _v2 / (μ ₂ πf)) ^1/2 , z ₂ is the thickness of the electrode film, δ _{2 is} a high frequency for generating the plasma The skin depth of the electrode film with respect to the high frequency power applied from the power source, μ ₂ : permeability of the electrode film, and ρ _v2 : specific resistance of the electrode film.

To achieve the above object, table for plasma etching or ashing apparatus of claim 2 wherein the substrate is a table for plasma etching or ashing apparatus is mounted, the high frequency power source and for generating a plasma A conductor member connected to a high-frequency power source for ion attraction; a dielectric layer embedded in a central portion of the upper surface of the conductor member; an electrostatic chuck placed on the dielectric layer; and the substrate And the conductive film disposed between the dielectric layers, the electrostatic chuck has an electrode film connected to a high-voltage DC power source, and the conductive film has a condition “115Ω / □ ≦ ρ _s1 ≦ 2. 67 × 10 ⁵ Ω / □ ”, and the electrode film satisfies the condition“ 115Ω / □ ≦ ρ _s2 ”. Where ρ _{s1 is} the surface resistivity of the conductive film and ρ _s2 is the surface resistivity of the electrode film.

Plasma etching or table for ashing device according to claim 3, wherein, in the table for plasma etching or ashing device according to claim 1 or 2, wherein the surface resistivity [rho _s1 of the conductive film is 304Ω / □ or less It is characterized by that.

Mounting table according to claim 4 for plasma etching or ashing apparatus described in table for plasma etching or ashing device according to any one of claims 1 to 3, it viewed the conductive layer from the substrate side In some cases, the conductive film hides the dielectric layer.

Table for plasma etching or ashing device according to claim 5, in table for plasma etching or ashing device according to any one of claims 1 to 4, the surface resistivity [rho _s1 of the conductive film The surface resistivity of the electrode film is smaller than _s2 .

Table for plasma etching or ashing device according to claim 6, wherein, in the table for plasma etching or ashing device according to any one of claims 1 to 5, wherein the conductive member and the electrostatic chuck The conductive films are bonded and bonded to each other, and the conductive film is sandwiched between the conductive member and the electrostatic chuck.

Table for plasma etching or ashing device according to claim 7, wherein, in the table for plasma etching or ashing device according to claim 6, wherein the conductive film is formed on a sheet made of a resin, the sheet is said conductive It is affixed on the surface of a body member or the electrostatic chuck.

Table for plasma etching or ashing apparatus of claim 8, wherein, in the table for plasma etching or ashing device according to claim 6, wherein the conductive film is formed on the conductive member or the surface of the electrostatic chuck It is characterized by that.

Table for plasma etching or ashing apparatus of claim 9, wherein, in the table for plasma etching or ashing device according to claim 7 or 8, wherein said conductive film is characterized by being formed by vapor deposition.

Mounting table of claim 10 for plasma etching or ashing apparatus described, built in the mounting table for plasma etching or ashing device according to any one of claims 1 to 5, wherein the conductive film to the electrostatic chuck It is characterized by being.

In order to achieve the above object, a plasma etching or ashing apparatus according to claim 11 includes a mounting table on which a substrate is mounted, and the mounting table is a high-frequency power source for plasma generation and a high-frequency power source for ion attraction. A conductor member to be connected; a dielectric layer embedded in a central portion of the upper surface of the conductor member; an electrostatic chuck placed on the dielectric layer; and between the substrate and the dielectric layer A plasma etching or ashing device having a conductive film disposed on the electrostatic chuck, wherein the electrostatic chuck has an electrode film connected to a high-voltage DC power source, and the conductive film has a condition “δ ₁ / z ₁ ≧ 85 and ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ ”, and the electrode film satisfies the condition“ δ ₂ / z ₂ ≧ 85 ”. However, δ ₁ = (ρ _v1 / (μ ₁ πf)) ^1/2 , z ₁ : thickness of the conductive film, δ ₁ : the conductivity with respect to the high frequency power applied from the high frequency power source for plasma generation. Skin depth of the film, f: frequency of the high-frequency power applied from the high-frequency power source for generating plasma, π: circumference, μ ₁ : permeability of the conductive film, ρ _v1 : specific resistance of the conductive film, ρ _{s1 is} the surface resistivity of the conductive film, δ ₂ = (ρ _v2 / (μ ₂ πf)) ^1/2 , z ₂ is the thickness of the electrode film, δ _{2 is} a high frequency for generating the plasma The skin depth of the electrode film with respect to the high frequency power applied from the power source, μ ₂ : permeability of the electrode film, and ρ _v2 : specific resistance of the electrode film.

In order to achieve the above object, a plasma etching or ashing apparatus according to claim 12 includes a mounting table on which a substrate is mounted, and the mounting table is a high-frequency power source for plasma generation and a high-frequency power source for ion attraction. A conductor member to be connected; a dielectric layer embedded in a central portion of the upper surface of the conductor member; an electrostatic chuck placed on the dielectric layer; and between the substrate and the dielectric layer A plasma etching or ashing apparatus having a conductive film disposed on the electrostatic chuck, wherein the electrostatic chuck has an electrode film connected to a high-voltage DC power source, and the conductive film has a condition of “115Ω / □ ≦ ρ _s1 ≦ 2 .67 × 10 ⁵ Ω / □ ”, and the electrode film satisfies the condition“ 115Ω / □ ≦ ρ _s2 ”. Where ρ _{s1 is} the surface resistivity of the conductive film and ρ _s2 is the surface resistivity of the electrode film.

According to the plasma etching or ashing device of the mounting table and claim 11 for plasma etching or ashing apparatus of claim 1, wherein, the condition "[delta] _{1 /} z ₁ ≧ 85" and condition "ρ _s1 ≦ 2.67 × 10 A conductive film satisfying “ ⁵ Ω / □” and an electrostatic chuck having an electrode film satisfying the condition “δ ₂ / z ₂ ≧ 85”. δ (skin depth) is a thickness at which the strength of the electric field is reduced by 1 / e in the conductive film or electrode film. The larger the δ, the easier the electric field is transmitted through the conductive film or electrode film. It tends to penetrate deeply through the film in the thickness direction. Therefore, if δ ₁ / z ₁ ≧ 85 and δ ₂ / z ₂ ≧ 85, most of the high-frequency current does not flow through the conductive film or electrode film, but passes through the conductive film or electrode film in the thickness direction. As a result, TM mode hollow cylindrical resonance can be generated, and the electric field intensity distribution in the space facing the substrate can be made uniform. Generation of current can be prevented. Further, the smaller the surface resistivity of the conductive film, the easier the high frequency current flows through the conductive film. Therefore, if ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □, it is possible to prevent an excessive high-frequency current from flowing through the electrode film or the substrate. As a result, deterioration of the insulating film in the semiconductor device on the substrate can be prevented.

  Furthermore, the upper limit of the surface resistivity in the electrode film only needs to be managed considering the electrostatic attraction force of the substrate, so the management of the film thickness of the electrode film can be simplified, and a high voltage DC power supply is connected to the conductive film. Therefore, it is not necessary to provide a contact structure for bringing the power feeding pin into contact with the conductive film. As a result, the quality control of the electrode film and the conductive film can be performed relatively easily, and the mounting table can be easily manufactured.

According to the plasma etching or ashing device of the mounting table and claim 12 for plasma etching or ashing device according to claim 2, satisfying the condition _{"115Ω / □ ≦ ρ s1 ≦ 2.67} × 10 5 Ω / □ " A conductive film and an electrostatic chuck having an electrode film that satisfies the condition “115Ω / □ ≦ ρ _s2 ”. The higher the surface resistivity of the conductive film or electrode film, the more difficult the high-frequency current flows through the conductive film or electrode film. Therefore, the high-frequency current easily penetrates the conductive film or electrode film in the thickness direction and deeply dive. Therefore, if 115Ω / □ ≦ ρ _s1 and 115Ω / □ ≦ ρ _s2 , most of the high-frequency current does not flow through the conductive film or the electrode film, but passes through the conductive film or the electrode film in the thickness direction so as to be dielectric. It is possible to dive deep toward the body layer, and as a result, TM mode hollow cylinder resonance can be generated, and the electric field intensity distribution in the space facing the substrate can be made uniform. Can be prevented. Further, the smaller the surface resistivity of the conductive film, the easier the high frequency current flows through the conductive film. Therefore, if ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □, it is possible to prevent an excessive high-frequency current from flowing through the electrode film or the substrate. As a result, deterioration of the insulating film in the semiconductor device on the substrate can be prevented.

  Furthermore, the upper limit of the surface resistivity in the electrode film only needs to be managed considering the electrostatic attraction force of the substrate, so the management of the film thickness of the electrode film can be simplified, and a high voltage DC power supply is connected to the conductive film. Therefore, it is not necessary to provide a contact structure for bringing the power feeding pin into contact with the conductive film. As a result, the electrode film and the conductive film can be manufactured relatively easily, and the mounting table can be easily manufactured.

According to the mounting table for the plasma etching or ashing apparatus according to claim 3, since the surface resistivity ρ _s1 of the conductive film is 304Ω / □ or less, it is ensured that an excessive high-frequency current flows through the electrode film or the substrate. Can be prevented.

According to the mounting table for the plasma etching or ashing apparatus according to claim 4, when the conductive film is viewed from the substrate side, the conductive film hides the dielectric layer, so that the high-resistance dielectric layer is visible from the substrate side. Absent. As a result, the high-frequency current actively flows through the conductive film instead of the substrate, and it is possible to more reliably prevent an excessive high-frequency current from flowing through the substrate.

According to the mounting table for plasma etching or ashing apparatus according to claim 5, since the surface resistivity ρ _s1 of the conductive film is smaller than the surface resistivity ρ _{s2 of the} electrode film, the high-frequency current actively flows through the conductive film. . Thereby, it is possible to more reliably prevent an excessive high-frequency current from flowing through the substrate.

According to the mounting table for the plasma etching or ashing device according to claim 6, the conductor member and the electrostatic chuck are bonded and bonded together, and the conductive film is sandwiched between the conductor member and the electrostatic chuck. The surface resistivity of the conductive film can be measured before bonding the conductor member and the electrostatic chuck, and the range of the actual surface resistivity of the conductive film can be guaranteed. As a result, it is possible to provide a highly reliable mounting table for preventing deterioration of the insulating film in the semiconductor device.

According to the mounting table for the plasma etching or ashing device according to claim 7, the conductive film is formed on the resin sheet, and the sheet is adhered to the surface of the conductor member or the electrostatic chuck. The conductive film can be easily attached to the mounting table, so that the mounting table can be manufactured more easily.

According to the mounting table for the plasma etching or ashing apparatus according to claim 8, since the conductive film is formed on the surface of the conductive member or the electrostatic chuck, the mounting is performed simply by bonding the conductive member and the electrostatic chuck to each other. A conductive film can be attached to the mounting table, so that the mounting table can be manufactured more easily.

According to the mounting table for the plasma etching or ashing apparatus according to claim 9, since the conductive film is formed by vapor deposition, a conductive film having a uniform film thickness can be easily obtained, so that the surface resistance of the conductive film can be obtained. The rate can be easily managed.

According to the mounting table for the plasma etching or ashing apparatus according to claim 10, since the conductive film is built in the electrostatic chuck, the conductive film can be reliably attached to the mounting table. It can be manufactured easily.

It is sectional drawing which shows schematically the structure of the plasma processing apparatus provided with the mounting base which concerns on embodiment of this invention. FIG. 2A is a diagram for explaining a case where high-power plasma generation power is applied when it is assumed that no conductive film is present in the plasma processing apparatus of FIG. 1, and FIG. FIG. 2B is a diagram showing an electric circuit composed of a first high-frequency power source and the like. FIG. 3 is a diagram for explaining a case where a high-power bias power is applied when it is assumed that no conductive film is present in the plasma processing apparatus of FIG. 1, and FIG. FIG. 3B is a diagram showing an electric circuit including a second high-frequency power source and the like. It is a graph which shows the distribution of the etching rate of the photoresist in the surface of each wafer at the time of using the several conductive thin film from which the value of (delta) / z differs. It is a table | surface which shows the grade of the deterioration of the gate oxide film of TEG in each test wafer at the time of using the several conductive thin film from which the value of (delta) / z differs. It is an expanded sectional view which shows schematically the structure of the mounting base in FIG. FIG. 7 is a diagram for explaining a case where a high output bias power is applied in the plasma processing apparatus of FIG. 1, and FIG. 7A is a partial cross-sectional view schematically showing a configuration in the vicinity of the electrostatic chuck. 7 (B) is a diagram showing an electric circuit including a second high-frequency power source and the like. FIG. 8 is an enlarged cross-sectional view schematically showing a configuration of a modified example of the mounting table in FIG. 1, FIG. 8 (A) is a first modified example, and FIG. 8 (B) is a second modified example; 8 (C) is a third modification, and FIG. 8 (D) is a fourth modification. FIG. 9A is a cross-sectional view schematically showing a configuration of a plasma processing apparatus capable of improving the in-plane uniformity of the conventional plasma processing, and FIG. 9A shows a case where an electrostatic chuck is not arranged. 9 (B) shows a case where an electrostatic chuck is arranged.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a plasma processing apparatus including a mounting table according to the present embodiment. This plasma processing apparatus is configured to perform plasma etching, for example, RIE (Reactive Ion Etching) or ashing, on a semiconductor wafer (substrate) having a diameter of, for example, 300 mm.

  In FIG. 1, a plasma processing apparatus 10 includes, for example, a processing container 11 composed of a vacuum chamber, a mounting table 12 disposed in a central portion of the bottom surface in the processing container 11, and a mounting table 12 above the mounting table 12. And an upper electrode 13 provided to face each other.

  The processing container 11 has a small-diameter cylindrical upper chamber 11a and a large-diameter cylindrical lower chamber 11b. The upper chamber 11a and the lower chamber 11b communicate with each other, and the entire processing container 11 is configured to be airtight. In the upper chamber 11a, the mounting table 12 and the upper electrode 13 are stored, and in the lower chamber 11b, a supporting case 14 that supports the mounting table 12 and stores piping for refrigerant and backside gas is stored.

  An exhaust port 15 is provided on the bottom surface of the lower chamber 11 b, and an exhaust device 17 is connected to the exhaust port 15 through an exhaust pipe 16. The exhaust device 17 has an APC (Adaptive Pressure Control) valve, DP (Dry Pump) and TMP (Turbo Molecular Pump) (none of them are shown), and the APC valve is controlled by a signal from a control unit (not shown). Then, the entire inside of the processing container 11 is evacuated to maintain a desired degree of vacuum. On the other hand, a loading / unloading port 18 for the wafer W is provided on the side surface of the upper chamber 11 a, and the loading / unloading port 18 can be opened and closed by a gate valve 19. The upper chamber 11a and the lower chamber 11b are made of a conductive member such as aluminum and are grounded.

  The mounting table 12 includes, for example, a lower electrode 20 (conductor member) for plasma generation, which is a base member made of aluminum as a conductor, and a lower electrode in order to make the electric field strength uniform in a processing space described later. For example, a dielectric layer 21 made of ceramic, which is a dielectric material, embedded in the center of the upper surface of the substrate 20, an electrostatic chuck 22 for electrostatically adsorbing and fixing the wafer W on the mounting surface, and a conductive film 45 And have. The conductive film 45 will be described in detail later.

  In the mounting table 12, the lower electrode 20, the dielectric layer 21, and the electrostatic chuck 22 are laminated in this order. In addition, the lower electrode 20 is fixed to a support base 23 installed on the support case 14 via an insulating member 24, and is in a state of being sufficiently electrically floated with respect to the processing container 11.

  A coolant channel 25 for allowing a coolant to flow therethrough is formed in the lower electrode 20, and the coolant flows through the coolant channel 25, whereby the lower electrode 20 is cooled and placed on the mounting surface on the upper surface of the electrostatic chuck 22. The processed wafer W is cooled to a desired temperature.

The electrostatic chuck 22 is made of a dielectric and includes an electrode film 37. The electrode film 37 is made of, for example, an electrode material in which silicon carbide (SiC) is contained in alumina (Al ₂ O ₃ ), and exhibits conductivity. A high voltage DC power source 42 is connected to the electrode film 37, and the high voltage DC power applied to the electrode film 37 generates a Coulomb force between the mounting surface of the electrostatic chuck 22 and the wafer W, thereby electrostatically Adsorb and fix.

  Further, the electrostatic chuck 22 has a through hole 26 for releasing a backside gas for improving heat transfer between the mounting surface and the back surface of the wafer W. The through hole 26 communicates with a gas flow path 27 formed in the lower electrode 20 or the like, such as helium (He) supplied from a gas supply unit (not shown) through the gas flow path 27. Backside gas is released.

  The lower electrode 20 has a frequency higher than that of the first high-frequency power supply 28 and a first high-frequency power supply 28 that applies a high-frequency power (plasma generation power) of, for example, 27 MHz or more. And a second high-frequency power source 29 (high-frequency power source for ion attraction) that applies a high-frequency power (bias power) of 27 MHz or less, for example, is connected via matching units 30 and 31, respectively. The plasma generation power applied from the first high frequency power supply 28 generates plasma from a processing gas, which will be described later, and the bias power applied from the second high frequency power supply 29 draws ions in the plasma to the surface of the wafer W. .

  A focus ring 32 is disposed on the outer edge of the upper surface of the lower electrode 20 so as to surround the electrostatic chuck 22. The focus ring 32 spreads plasma in a processing space, which will be described later, more than a space where the wafer W faces, thereby improving the uniformity of the etching rate in the surface of the wafer W.

  A baffle plate 33 is provided outside the lower side of the support base 23 so as to surround the support base 23. The baffle plate 33 rectifies the flow of the processing gas by allowing the processing gas in the upper chamber 11a to flow to the lower chamber 11b through a gap formed between the baffle plate 33 and the wall of the upper chamber 11a. While serving as a plate, it prevents plasma in the processing space described later from leaking into the lower chamber 11b.

  The upper electrode 13 includes a ceiling electrode plate 34 made of a conductive material facing the upper chamber 11a, an electrode plate support 35 that supports the ceiling electrode plate, and a buffer chamber provided in the electrode plate support 35. 36. One end of a gas introduction pipe 38 is connected to the buffer chamber 36, and the other end of the gas introduction pipe 38 is connected to a processing gas supply source 39. The processing gas supply source 39 includes a processing gas supply amount control mechanism (not shown), and controls the processing gas supply amount. The ceiling electrode plate 34 is formed with a large number of gas supply holes 40 that pass through the ceiling electrode plate 34 and communicate with the buffer chamber 36 and the upper chamber 11a.

  In the upper electrode 13, the processing gas supplied from the processing gas supply source 39 to the buffer chamber 36 is distributed and supplied into the upper chamber 11 a through the gas supply holes 40, so that the upper electrode 13 functions as a processing gas showerhead. . Further, a conductive path is formed between the upper electrode 13 and the processing vessel 11 by fixing the upper electrode 13 to the wall portion of the upper chamber 11a.

  In the plasma processing apparatus 10, two multipole ring magnets 41a and 41b are disposed above and below the gate valve 19 around the upper chamber 11a. In the multipole ring magnets 41a and 41b, a plurality of anisotropic segment columnar magnets (not shown) are accommodated in a ring-shaped magnetic casing (not shown), and the magnetic poles of a plurality of adjacent segment columnar magnets in the casing. Are arranged so that their directions are opposite to each other. As a result, magnetic field lines are formed between adjacent segment columnar magnets, and a magnetic field is formed around the processing space located between the upper electrode 13 and the lower electrode 20, and the plasma is confined to the processing space by the magnetic field. The apparatus configuration of the plasma processing apparatus 10 may be an apparatus configuration that does not include the multipole ring magnets 41a and 41b.

  In the plasma processing apparatus 10, when RIE or ashing is performed on the wafer W, the pressure in the processing container 11 is adjusted to a desired degree of vacuum, and then a processing gas is introduced into the upper chamber 11 a and is supplied from the first high frequency power supply 28. A plasma generation power is applied, and a bias power is applied from the second high-frequency power source 29 to generate plasma from the processing gas, and ions in the plasma are drawn into the wafer W. At this time, in order to generate a plasma having a low ion energy and a high electron density, the first high frequency power supply 28 may apply a high frequency power of 27 MHz or higher, preferably 40 MHz or higher. In order to surely attract ions toward the wafer W, the second high frequency power supply 29 may apply high frequency power of 27 MHz or less, preferably 13.56 MHz or less. The high-frequency power applied from the first high-frequency power source 28 or the second high-frequency power source 29 flows through a path consisting of the lower electrode 20 → plasma → the upper electrode 13 → the wall of the processing vessel 11 → the ground.

  In the plasma processing apparatus 10, since the frequency of the plasma generation power applied by the first high frequency power supply 28 is relatively high (40 MHz or higher), the strength of the electric field at the portion facing the central portion of the wafer W in the processing space is increased. Tend. In order to eliminate this tendency and make the intensity distribution of the electric field uniform in the processing space, the plasma processing apparatus 10 includes a dielectric layer 21 of the lower electrode 20. Due to the presence of the dielectric layer 21, the high-frequency current from the first high-frequency power source 28 lies deeply from the central portion of the wafer W toward the dielectric layer 21 of the lower electrode 20 via the electrostatic chuck 22. As a result, TM mode hollow cylindrical resonance occurs in the central portion of the lower electrode 20, and the electric field strength distribution in the processing space is made uniform.

Here, when it is assumed that the conductive film 45 does not exist in the plasma processing apparatus 10, it is generated in the first high frequency power supply 28, the lower electrode 20, the dielectric layer 21, the electrostatic chuck 22, the electrode film 37, the wafer W, and the processing space. The plasma PZ and the like (FIG. 2A) to form an electric circuit 43 as shown in FIG. Further, the second high-frequency power source 29 and the like (FIG. 3A) constitute an electric circuit 44 as shown in FIG. In the plasma processing apparatus 10, since the dielectric layer 21 exists only in the central portion of the lower electrode 20, the electric circuit 43 (44) has a circuit 43 a (44 a) corresponding to the central portion of the lower electrode 20 and the lower electrode 20. considered is a circuit 43b corresponding to the peripheral portion (44b) are present, are bridged by the resistance _{R E} of the resistor _{R W} and the electrode film 37 of the wafer W from the circuit 43a (44a) and circuit 43b (44b) The Further, when the wafer W is mounted on the mounting surface of the electrostatic chuck 22, because the the wafer W and the electrode film 37 is parallel to each other, the resistance R _W and the resistance R _E is arranged in an electric circuit to parallel The Rukoto.

When the high-power plasma generation power is applied from the first RF power supply 28, the resistance R _E of the electrode film 37 is small, the transmitting from the central portion of the wafer W to the electrostatic chuck 22 in the thickness direction The high-frequency current from one high-frequency power supply 28 flows from the central portion of the electrostatic chuck 22 to the peripheral portion through the electrode film 37 instead of diving toward the dielectric layer 21. As a result, it is difficult to generate an electric field that is generated due to the high-frequency current that flows into the dielectric layer 21 and that is transmitted through the electrode film 37. This phenomenon will be described below.

In the present embodiment, the skin depth δ of the thin film is used as an index indicating the degree of decrease in the electric field transmitted through the conductive thin film such as the electrode film 37. Skin depth δ is the thickness at which the electric field transmitted through the thin film is reduced by 1 / e. The electric field is difficult to decrease when the skin depth δ is large, the electric field penetrates the thin film well, and the electric field decreases when the skin depth δ is small. And the electric field does not easily penetrate the thin film. The skin depth δ is represented by the following formula (5).
δ = (2ρ _v / (μω)) ^1/2 = (ρ _v / (μπf)) ^1/2 (5)
Here, μ is the magnetic permeability (H / m) of the thin film, and ω is 2πf (π: pi, f: frequency of the plasma generating power applied from the first high frequency power supply 28 (Hz)). There, [rho _v is the specific resistance of the electrode material constituting the thin film (Ω · m).

The electric field E formed in the thin film is expressed by the following formula (6) from Maxwell's equation.
E = E ₀ exp (−iωt) exp (iz / δ) exp (−z / δ) (6)
Here, z is the thickness (m) of the thin film, and E ₀ is the strength of the electric field incident on the thin film.

That is, the transmittance “E / E ₀ ” through which the electric field of the plasma generation power applied from the first high frequency power supply 28 passes through the electrode film 37 is expressed by “exp (−z) as shown in the following formula (7). / Δ) ”.
E / E ₀ ∝exp (−z / δ) (7)
From the above equation (7), the electric field transmittance approaches 1.0 (100%) as the value of “z / δ” approaches “0”, and the electric field transmittance decreases as “δ” decreases. Since the resistance _{R E} of the electrode film 37 is small are such that there is no specific resistance [rho _v of the electrode film 37 is small, the resistance _{R E} and is small ^{_{"(ρ v / (μπf))}} 1/2 " The displayed skin depth δ becomes smaller, and it becomes difficult to generate an electric field that passes through the electrode film 37.

  When almost no electric field that passes through the electrode film 37 is generated, TM-mode hollow cylindrical resonance does not occur in the central portion of the lower electrode 20, and the central portion of the wafer W in the processing space (hereinafter referred to as "central space"). The strength of the electric field in the facing portion is larger than the strength of the electric field in the portion facing the peripheral portion (hereinafter referred to as “peripheral space”) of the wafer W in the processing space, and the electron density of the plasma is increased in the central space. . As a result, the etching rate distribution in the surface of the wafer W becomes non-uniform.

At this time, due to non-uniformity of the plasma electron density distribution in the processing space, the resistance R _{C of} the plasma PZ, the sheath capacitor C _P of the plasma PZ, the capacitor C _T of the gate oxide film, and the wafer W DC current in the circuit formed by the resistor R _W (indicated by a dotted arrow in FIG. 2 (B)) occurs. When a direct current flows through the wafer W, a gate oxide film (insulating film) in a semiconductor device on the wafer W (hereinafter simply referred to as “device”) is charged up and damaged and deteriorates.

In order to make the distribution of the etching rate uniform within the surface of the wafer W and to prevent the gate oxide film from deteriorating in the device when a high-power plasma generation power is applied, the first high-frequency power source 28 It is necessary to suppress the flow of the high-frequency current through the electrode film 37 and to generate an electric field that penetrates the electrode film 37 by deeply diving the high-frequency current toward the dielectric layer 21. From 7), “δ / z” may be increased. In order to increase “δ / z”, the skin depth δ may be increased or the thickness “z” of the electrode film 37 may be decreased. Since the skin depth δ is represented by “(ρ _v / (μπf)) ^1/2 ” as described above, in order to increase the skin depth δ, an electrode having a large specific resistance ρ _v is used when the frequency is constant. What is necessary is _just to enlarge resistance RE of the electrode film 37 using a material. Further, since the skin depth δ decreases as the frequency of the high frequency power increases (δ∝ (1 / ω) = (1 / 2πf)), when the frequency of the high frequency power is increased, the constituent material of the electrode film 37 is it may be used a larger electrode material resistivity [rho _v.

Further, in the electric circuit 44, the bias power is applied from the second RF power supply 29, since the circuit 44a corresponding to the center portion of the lower electrode 20 is present the capacitor C _I of the dielectric layer 21, the second The high-frequency current from the high-frequency power source 29 mainly flows not through the circuit 44a but through the circuit 44b corresponding to the peripheral portion of the lower electrode 20, and eventually returns to the circuit 44a (indicated by a thick solid arrow in FIG. 3B). Here, when the resistance R _E of the electrode film 37 is set larger than the resistance R _W of the wafer W, through a high-frequency current rather than primarily electrode film 37 wafers W to reflux to the circuit 44a. Thereby, a potential difference is generated in the plane of the wafer W, and the balance of the charge of the gate oxide film (insulating film) in the plane of the wafer W is lost. As a result, the gate oxide film is charged up in the device on the wafer W and deteriorates due to damage.

In order to prevent deterioration of the gate oxide film in the device when a high output bias power is applied from the second high frequency power supply 29, the high frequency current from the second high frequency power supply 29 mainly flows through the wafer W. it is necessary to prevent, or be allowed to flow positively frequency current to the electrode film 37 to reduce the resistance R _E of the electrode film 37 for that.

From the above, in order to make the distribution of the etching rate in the plane of the wafer W uniform when a high-power plasma generation power is applied, δ / z may be made larger than a certain value (in other words, the resistance R _E of the electrode film 37 may be greater than a certain value.). In order to prevent deterioration of the gate oxide film in both cases where high output plasma generation power is applied and high output bias power is applied, "δ / z" is set to a certain value. as well as larger, when the "[delta] / z" a may be smaller than other certain value (in other words, some other of the resistor R _E together with the resistance R _E of the electrode film 37 is larger than a certain value It should be smaller than the value.)

  FIG. 4 is a graph showing the photoresist etching rate distribution in the plane of each wafer when a plurality of conductive thin films having different values of δ / z are used.

In the graph of FIG. 4, electrode films 37 as a plurality of conductive thin films having different values of δ / z (and resistance R _E ) are prepared, and the plasma processing apparatus 10 (the conductive film 45 is formed using each electrode film 37. The result of ashing the photoresist on the wafer W and observing the distribution of the etching rate of the photoresist in the plane of each wafer W in FIG.

In the graph of FIG. 4, to a resistor R _E of the electrode film 37 removes the effect of the thickness of the electrode film 37, and represents the resistance value of the electrode film 37 in the surface resistivity [rho _s of the conductive thin film. The surface resistivity ρ _s of the thin film is expressed by the following formula (8), indicates a resistance value per unit area, and is determined by the physical property value (specific resistance ρ _v ) of the electrode material constituting the thin film and the thickness of the thin film.
ρ _s = ρ _v / z (Ω / □) (8)
Δ / z (and ρ _s ) of each electrode film 37 as a thin film used here is 7518 (and 8.9 × 10 ⁵ Ω / □), 6711 (and 2.67 × 10 ⁵ Ω / □), 297 (and 1740 Ω / □), 195 (and 750 Ω / □), 124 (and 304 Ω / □), 103 (and 208 Ω / □), 92 (and 166 Ω / □), 85 (and 115 Ω / □), and 47 (And 35Ω / □).

Further, in ashing at this time, a single O ₂ gas as a processing gas is introduced into the upper chamber 11a at a flow rate of 100 sccm, the frequency of the plasma generation power applied by the first high frequency power supply 28 is set to 100 MHz, and The value was set to 2000 W, but no bias power was applied from the second high-frequency power source 29.

In the graph of FIG. 4, the horizontal axis represents the distance from the center of the wafer W, and the vertical axis represents the etching rate (nm / min). The broken line corresponds to δ / z (and surface resistivity) = 47 (and 35Ω / □), and the other solid line corresponds to δ / z (and surface resistivity) ≧ 85 (and 115Ω / □). It corresponds to. According to the graph of FIG. 4, if δ / z is 85 or more (ρ _s is 115 Ω / □ or more), the etching rate distribution in the surface of the wafer W can be made substantially uniform.

  FIG. 5 is a table showing the degree of deterioration of the TEG gate oxide film in each test wafer when a plurality of conductive thin films having different values of δ / z are used.

In the table of FIG. 5, electrode films 37 as a plurality of conductive thin films having different values of δ / z (and resistance R _E ) are prepared, and the plasma processing apparatus 10 (the conductive film 45 is formed using each electrode film 37. The result is that the RIE or ashing is performed on the test wafer and the deterioration of the gate oxide film of the TEG (Test Element Group) in each test wafer is observed.

  Normally, the antenna ratio is set to 10 times or less in the TEG and set to 100 times or less at the maximum. However, in order to accelerate the deterioration of the gate oxide film of the TEG, the antenna ratio of the TEG is 10,000 (10K). ) And a test wafer in which the antenna ratio of the TEG is set to 100,000 (100K) times (hereinafter referred to as “100K test wafer”). In addition, as an indicator of the deterioration of the gate oxide film, the ratio of the number of gate oxide films whose degree of deterioration did not exceed a predetermined value before and after RIE or ashing with respect to the total number of gate oxide films in the test wafer (hereinafter referred to as “gate oxidation film”). Membrane viability (%) ”was used.

  Regarding the threshold value of the gate oxide film survival rate, RIE is applied to the 100K test wafer in an ordinary plasma processing apparatus which does not have the dielectric layer 21 in the lower electrode 20 and uses high frequency power of a relatively low frequency for plasma generation. Since the gate oxide film survival rate at that time was 54%, a normal threshold value of the gate oxide film survival rate when the RIE was applied to the 100K test wafer (hereinafter referred to as “normal threshold value”). It was. In the normal plasma processing apparatus, the gate oxide film did not deteriorate even when RIE was performed on a test wafer having a TEG having a normal antenna ratio (about 10 times). The yield required when RIE or ashing is performed on a special device corresponds to 65% when converted to the gate oxide film survival rate when RIE or ashing is performed on the 100K test wafer. % Is a threshold value of the gate oxide film survival rate in a special device when RIE is applied to a 100K test wafer (hereinafter referred to as “special device threshold value”).

Further, where each electrode film 37 using [delta] / z (and [rho _s) is, [delta] / z when the observed distribution of the etching rate of the photoresist in the plane of the wafer W as described above (and [rho _s) Set the same.

When high-power plasma generation power is applied, O ₂ single gas is introduced as a processing gas into the upper chamber 11a at a flow rate of 200 sccm, the frequency of the plasma generation power is set to 100 MHz, and the value is set. While setting to 2400 W, ashing was performed on each test wafer without applying bias power from the second high-frequency power source 29. Further, when a high output bias power is applied (in this case, a high output plasma generation power is also applied), a mixed gas of C ₄ F ₈ gas, Ar gas and O ₂ gas (as a processing gas) The flow rate ratio: C ₄ F ₈ gas / Ar gas / O ₂ gas = 35/200/30 sccm) is introduced into the upper chamber 11a, the frequency of the plasma generation power is set to 100 MHz, and the value is set to 500 W. At the same time, the frequency of the bias power was set to 3.2 MHz and the value was set to 4000 W, and each test wafer was subjected to RIE. Note that “high power HF” in FIG. 5 corresponds to the case where high output plasma generation power is applied, and “high power LF” corresponds to the case where high output bias power is applied.

  In addition, the table of FIG. 5 shows a plan view of the test wafer and the gate oxide film survival rate showing the distribution state of the gate oxide film whose degree of deterioration did not exceed a predetermined value for each test condition in shades.

According to the table of FIG. 5, when high-power plasma generation power is applied (in the case of high power HF), if δ / z is 85 or more (ρ _s is 115Ω / □ or more), a 100K test wafer When the gate oxide film survival rate when ashing is performed is equal to or higher than the normal threshold (54%) and a high output bias power is applied (in the case of high power LF), ρ _s is 2.67 × 10 ^5. If it is Ω / □ or less, the gate oxide film survival rate when RIE is performed on a 100K test wafer is equal to or higher than the normal threshold (54%).

That is, the high-frequency current from the first high-frequency power supply 28 is suppressed from flowing through the electrode film 37 for the purpose of preventing the deterioration of the gate oxide film of the device having a normal antenna ratio, and the high-frequency current is applied to the dielectric layer. In order to generate an electric field that penetrates deeply toward the electrode 21 and passes through the electrode film 37, δ / z may be set to 85 or more (ρ _s is set to 115Ω / □ or more). Further, in order to prevent the high-frequency current from the second high-frequency power source 29 from flowing mainly through the wafer W, ρ _s may be set to 2.67 × 10 ⁵ Ω / □ or less.

Further, according to the table of FIG. 5, when high-power plasma generation power is applied (in the case of high power HF), if δ / z is 85 or more (ρ _s is 115Ω / □ or more), 100K a gate oxide film survival is a special device threshold (65%) or more when subjected to the ashing test wafer, and if the bias power of the high output is applied (in the case of high power LF), a ρ _s 304Ω / □ In the following, the gate oxide film survival rate when RIE is performed on a 100K test wafer becomes a special device threshold (65%) or more.

That is, for the purpose of preventing deterioration of the gate oxide film of a special device, the high-frequency current from the first high-frequency power supply 28 is suppressed from flowing through the electrode film 37, and the high-frequency current is directed toward the dielectric layer 21. In order to generate an electric field that penetrates deeply and passes through the electrode film 37, δ / z may be 85 or more (ρ _s is 115Ω / □ or more). Further, in order to high-frequency current from the second RF power supply 29 is prevented primarily flowing a wafer W may be a ρ _s 304Ω / □ below.

Here, for example, in order to prevent deterioration of the gate oxide film of a device having a normal antenna ratio, the ρ _{s of the} electrode film 37 is set to 115Ω / □ or more, and the ρ _s is 2.67 × 10 ^5. In order to set Ω / □ or less, since the surface resistivity is inversely proportional to the thickness of the thin film, it is necessary to strictly manage the upper and lower limits of the thickness of the electrode film 37. On the other hand, as described above, since it is necessary to contact the electrode film 37 with a power supply pin for applying high-voltage DC power, the contact structure for contacting the power supply pin with the electrode film 37 needs to be strictly managed. is there.

  Therefore, when the electrode film 37 is used to prevent the deterioration of the gate oxide film of the device, it is necessary to strictly manage not only the upper limit and the lower limit of the film thickness but also the contact structure for contacting the power supply pin in the electrode film 37. . As a result, quality control of the electrode film 37 is accompanied with great difficulty, and the mounting table 12 cannot be easily manufactured.

  By the way, when a high output bias power is applied, the high-frequency current from the second high-frequency power source 29 may flow in a current path other than the wafer W in order to prevent the deterioration of the gate oxide film of the device. The high-frequency current does not necessarily have to flow through the electrode film 37. In the present embodiment, in response to this, a current path for a high-frequency current from the second high-frequency power supply 29 is provided separately from the electrode film 37 in the mounting table 12. Specifically, a conductive film 45 that functions as a current path disposed in parallel with the electrode film 37 on the mounting table 12 is provided on the mounting table 12.

  FIG. 6 is an enlarged cross-sectional view schematically showing the configuration of the mounting table in FIG.

  In FIG. 6, the conductive film 45 is disposed between the wafer W electrostatically attracted to the electrostatic chuck 22 and the dielectric layer 21. The conductive film 45 is made of a conductive member, for example, a disk-shaped metal film, and has a size capable of hiding the dielectric layer 21 when the dielectric layer 21 is viewed from the wafer W side.

  The electrostatic chuck 22 includes a disk-shaped base material 22a made of a sintered ceramic material, an electrode film 37 formed on the surface of the base material 22a (upper surface in the drawing), and an electrode film 37 on the electrode film 37. A disc-shaped upper member 22b made of a sintered ceramic material, which is laminated and pressure-bonded to the electrode film 37 and the base material 22a, and one end of which is in contact with the electrode film 37 and the other end is the back surface of the base material 22a (see FIG. And a cylindrical power supply pin 46 exposed on the lower surface in the middle. In the electrostatic chuck 22, the electrode film 37 is arranged so as to be parallel to the back surface of the substrate 22a.

  The conductive film 45 is formed on the resin sheet 47 by vapor deposition, for example, CVD, and the resin sheet 47 is attached to the back surface of the base material 22 a in the electrostatic chuck 22. As a result, the conductive film 45 is bonded to the electrostatic chuck 22 in parallel with the electrode film 37.

  The electrostatic chuck 22 to which the conductive film 45 is bonded is placed on the upper surface of the lower electrode 20, and the lower electrode 20 is sandwiched between the lower electrode 20 and the electrostatic chuck 22 by an insulating adhesive 48. Glued to. At this time, the other end of the power supply pin 46 is electrically connected to the high-voltage DC power source 42 via the energizing rod 49. Thereby, the high voltage DC power source 42 can supply a high voltage DC voltage to the electrode film 37.

In the plasma processing apparatus 10, when a high output bias power is applied, the electric circuit 50 (FIG. 7B) is established in consideration of the presence of the conductive film 45 as illustrated in FIG. 7A. . In this electric circuit 50, it is considered that a circuit 50a corresponding to the central portion of the lower electrode 20 where the dielectric layer 21 exists and a circuit 50b corresponding to the peripheral portion of the lower electrode 20 are present. The circuit 50 b is bridged by the resistance R _{W of the} wafer W, the resistance R _E of the electrode film 37, and the resistance R _{L of the} conductive film 45. Further, when the wafer W is mounted on the mounting surface of the electrostatic chuck 22, the wafer W and the electrode film 37, since the conductive film 45 is parallel to each other, the resistance R _W and the resistance R _E, the resistance R _L is It will be arranged in parallel in the electric circuit.

To the electrical circuit 50 high-frequency current from the second RF power supply 29 is prevented primarily flowing a wafer W may be set smaller than the resistance R _E or resistance R _L resistor R _W. In other words, using the results shown in the table of FIG. 5, when the purpose is to prevent the deterioration of the gate oxide film of a device having a normal antenna ratio, the ρ of the electrode film 37 or the conductive film 45 is used. _{The s} may be set to 2.67 × 10 ⁵ Ω / □ or less. For the purpose of preventing deterioration of the gate oxide film of a special device, the ρ _s of the electrode film 37 or the conductive film 45 may be set to 304Ω / □ or less.

Here, even if the high-frequency current from the second high-frequency power source 29 does not mainly flow through the electrode film 37, if the high-frequency current mainly flows through the conductive film 45, the high-frequency current is prevented from flowing mainly through the wafer W. And deterioration of the gate oxide film of the device can be prevented. Therefore, in the present embodiment, only ρ _{s of} the conductive film 45 is set to 2.67 × 10 ⁵ Ω / □ or less, preferably 304 Ω / □ or less. As a result, as indicated by a thick solid arrow in FIG. 7B, a high-frequency current from the second high-frequency power source 29 can flow mainly through the conductive film 45 (resistor R _L ).

  In addition, when high-power plasma generation power is applied, a high-frequency current from the first high-frequency power source 28 is deeply hidden toward the dielectric layer 21 in order to prevent deterioration of the gate oxide film of the device. In order to achieve this, it is necessary to suppress the high-frequency current from the first high-frequency power supply 28 from flowing not only through the electrode film 37 but also through the conductive film 45.

Here, according to the table of FIG. 5, in order to prevent deterioration of the gate oxide film of a device having a normal antenna ratio and a special device when high-power plasma generation power is applied, 37 and [delta] / z of the conductive film 45 may be (a ρ _s 115Ω / □ or higher) 85 or more. Therefore, in the present embodiment, not only the electrode film 37 but also δ / z of the conductive film 45 is set to 85 or more (ρ _s is 115 Ω / □ or more).

According to the mounting table 12 according to the present embodiment, the conductive film 45 that satisfies the condition “δ / z ≧ 85” and the condition “ρ _s ≦ 2.67 × 10 ⁵ Ω / □”, and the condition “δ / z ≧ And the electrostatic chuck 22 having the electrode film 37 satisfying “85”. The larger the skin depth δ, the easier the electric field is transmitted through the electrode film 37 and the conductive film 45. Therefore, the high-frequency current from the first high-frequency power supply 28 passes through the electrode film 37 and the conductive film 45 in the thickness direction and is dielectric. It is easy to dive deeply toward the layer 21. Therefore, if the electrode film 37 and the conductive film 45 satisfy the condition “δ / z ≧ 85”, most of the high-frequency current flows through the electrode film 37 and the conductive film 45 in the thickness direction without flowing through the electrode film 37 and the conductive film 45. And penetrates deeply into the dielectric layer 21. As a result, TM mode hollow cylindrical resonance is generated in the central portion of the lower electrode 20 to make the electric field intensity distribution uniform in the processing space, and the generation of a direct current in the wafer W can be prevented. . In addition, the smaller the surface resistivity ρ _s of the conductive film 45, the easier the high frequency current from the second high frequency power supply 29 flows through the conductive film 45. Therefore, if the conductive film 45 satisfies the condition “ρ _s ≦ 2.67 × 10 ⁵ Ω / □”, it is possible to prevent an excessive high-frequency current from flowing from the second high-frequency power source 29 to the wafer W. Thereby, deterioration of the gate oxide film of the device having a normal antenna ratio on the wafer W can be prevented.

Further, according to the mounting table 12 described above, the electrode film 37 and the conductive film 45 satisfy the condition “115Ω / □ ≦ ρ _s ”. The higher the surface resistivity ρ _s of the electrode film 37 and the conductive film 45, the more difficult the high-frequency current flows through the electrode film 37 and the conductive film 45, so that the high-frequency current from the first high-frequency power supply 28 flows through the electrode film 37 and the conductive film 45. It is easy to dive deeply through the thickness direction. Therefore, if the electrode film 37 and the conductive film 45 satisfy the condition “115Ω / □ ≦ ρ _s ”, most of the high-frequency current from the first high-frequency power supply 28 is transmitted through the electrode film 37 and the conductive film 45 in the thickness direction. Then, it is possible to deeply dip into the dielectric layer 21.

In the mounting table 12 described above, the conductive film 45 may be set to satisfy the condition “ρ _s ≦ 304Ω / □”. If the surface resistivity ρ _s of the conductive film 45 is 304Ω / □ or less, it is possible to reliably prevent an excessive high-frequency current from flowing from the second high-frequency power source 29 to the wafer W. Thereby, the deterioration of the gate oxide film of a special device on the wafer W can be prevented.

Furthermore, in the table 12 described above, only the [rho _s of the conductive film 45 2.67 × 10 ⁵ Ω / □ or less, preferably, so may be set to 304Ω / □ or less, the upper limit of [rho _s in the electrode film 37 May be managed considering only the electrostatic attraction force of the wafer W, and as a result, the management of the film thickness of the electrode film 37 can be simplified. In addition, since the high voltage DC power source 42 is not connected to the conductive film 45, it is not necessary to provide a contact structure for bringing the power supply pin 46 into contact with the conductive film 45. As a result, quality control of the electrode film 37 and the conductive film 45 can be performed relatively easily, and the mounting table 12 can be easily manufactured.

  Further, in the mounting table 12 described above, when the conductive film 45 is viewed from the wafer W side, the conductive film 45 hides the dielectric layer 21, so that, for example, the dielectric layer 21 made of ceramic which is a high resistance material is formed on the wafer W. I can't see it from the side. As a result, the high-frequency current from the second high-frequency power supply 29 positively flows through the conductive film 45 instead of the wafer W above the dielectric layer 21, and more reliably prevents excessive high-frequency current from flowing through the wafer W. can do.

In the table 12 described above, although not specifically defined for the magnitude relationship between the surface resistivity [rho _s surface resistivity [rho _s and the electrode film 37 of the conductive film 45, preferably, the surface resistivity of the conductive film 45 [rho _s Is preferably smaller than the surface resistivity ρ _s of the electrode film 37. As a result, the high-frequency current from the second high-frequency power supply 29 actively flows through the conductive film 45, and it is possible to more reliably prevent an excessive high-frequency current from flowing through the wafer W.

  Further, in the mounting table 12 described above, the lower electrode 20 and the electrostatic chuck 22 are bonded and bonded to each other, and the conductive film 45 is sandwiched between the lower electrode 20 and the electrostatic chuck 22. The surface resistivity of the conductive film 45 can be measured before the chuck 22 is bonded, and the range of the actual surface resistivity of the conductive film 45 after the mounting table 12 is manufactured can be guaranteed.

  Furthermore, in the mounting table 12 described above, the conductive film 45 is formed on the resin sheet 47, and the resin sheet 47 is attached to the back surface of the base material 22 a in the electrostatic chuck 22. Can be easily attached. The resin sheet 47 may be attached to the upper surface of the lower electrode 20, particularly the upper surface of the dielectric layer 21.

Further, in the mounting table 12 described above, since the conductive film 45 is formed by vapor deposition, it is possible to easily obtain the conductive film 45 having a uniform film thickness, and thus to easily manage ρ _s of the conductive film 45. be able to.

  In the mounting table 12 described above, the conductive film 45 is sandwiched between the electrostatic chuck 22 and the lower electrode 20, but the conductive film 45 only needs to function as a current path for a high-frequency current from the second high-frequency power source 29. There is no need to limit the location of the film 45, and the conductive film 45 may be disposed at least between the wafer W electrostatically attracted to the electrostatic chuck 22 and the dielectric layer 21.

  In the mounting table 12 described above, the conductive film 45 is attached to the electrostatic chuck 22 via the resin sheet 47, but the method of attaching the conductive film 45 to the mounting table 12 is not limited thereto.

  For example, as shown in FIG. 8A, the conductive film 45 may be directly formed on the back surface of the base material 22a by vapor deposition. Accordingly, the conductive film 45 can be attached to the mounting table 12 simply by bonding the lower electrode 20 and the electrostatic chuck 22 to each other, and thus the mounting table 12 can be more easily manufactured. The conductive film 45 may be formed by vapor deposition on the upper surface of the lower electrode 20, particularly on the upper surface of the dielectric layer 21.

  Further, before bonding the lower electrode 20 and the electrostatic chuck 22, an insulating adhesive 48 is applied to the upper surface of the lower electrode 20, and a thin film formed in advance on the applied insulating adhesive 48. The conductive film 45 may be placed, and an insulating adhesive 48 may be further applied on the conductive film 45, and then the lower electrode 20 and the electrostatic chuck 22 may be bonded by the insulating adhesive 48. Thereby, the conductive film 45 floats in the insulating adhesive 48 (FIG. 8B) and does not come into contact with the electrostatic chuck 22 or the lower electrode 20 which is a rigid body. Trouble can be prevented.

Furthermore, as shown in FIG. 8C, instead of providing the conductive film 45, the lower electrode 20 and the electrostatic chuck 22 are formed using an adhesive layer 51 made of an adhesive having a predetermined magnetic permeability and specific resistance. It may be glued. At this time, the thickness and surface resistivity of the adhesive layer 51 are set so that the adhesive layer 51 satisfies the condition “δ / z ≧ 85” and the condition “ρ _s ≦ 2.67 × 10 ⁵ Ω / □”. Coordinated and managed. Thus, the adhesive layer 51 can be transmitted through in the thickness direction and flow deeply into the dielectric layer 21 without flowing most of the high-frequency current from the first high-frequency power supply 28 through the adhesive layer 51. In addition, a high-frequency current from the second high-frequency power supply 29 can be actively supplied to the adhesive layer 51.

  Further, as shown in FIG. 8D, a conductive film 45 may be incorporated in the base material 22a when the base material 22a is sintered. Thereby, the conductive film 45 can be reliably attached to the mounting table 12, and the mounting table 12 can be manufactured more easily.

  In the present embodiment described above, the substrate on which RIE or ashing is performed is a semiconductor wafer. However, the substrate on which RIE or ashing is performed is not limited to this, for example, an LCD (Liquid Crystal Display) or the like. The glass substrate for FPD (Flat Panel Display) to include may be sufficient.

W wafer
DESCRIPTION OF SYMBOLS 10 Plasma processing apparatus 11 Chamber 12 Mounting stand 20 Lower electrode 21 Dielectric layer 22 Electrostatic chuck 22a Base material 28 First high frequency power supply 29 Second high frequency power supply 37 Electrode film 42 High voltage direct current power supplies 43, 44, 50 Electric circuit 45 Conductive film 46 Power supply pin 47 Resin sheet 48 Insulating adhesive 51 Adhesive layer

Claims (12)

A mounting table for a plasma etching or ashing apparatus on which a substrate including a semiconductor device having a gate oxide film is mounted,
A conductor member connected to a high-frequency power source for plasma generation and a high-frequency power source for ion attraction;
A dielectric layer embedded in a central portion of the upper surface of the conductor member;
An electrostatic chuck mounted on the dielectric layer;
A conductive film disposed between the substrate and the dielectric layer;
The electrostatic chuck has an electrode film connected to a high-voltage DC power source,
The conductive film satisfies a condition represented by the following formula (1), and the electrode film satisfies a condition represented by the following formula (2).
δ ₁ / z ₁ ≧ 85 and ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ (1)
However, δ ₁ = (ρ _v1 / (μ ₁ πf)) ^1/2
Where z _{1 is} the thickness of the conductive film, δ ₁ is the skin depth of the conductive film with respect to the high-frequency power applied from the high-frequency power source for generating plasma, and f is the high-frequency applied from the high-frequency power source for generating plasma. Frequency of power, π: circularity, μ ₁ : permeability of the conductive film, ρ _v1 : specific resistance of the conductive film, ρ _s1 : surface resistivity of the conductive film δ ₂ / z ₂ ≧ 85 (2) )
However, δ ₂ = (ρ _v2 / (μ ₂ πf)) ^1/2
Where z _{2 is} the thickness of the electrode film, δ ₂ is the skin depth of the electrode film with respect to the high-frequency power applied from the high-frequency power source for generating plasma, μ _{2 is} the magnetic permeability of the electrode film, and ρ _{v2 is the} above-mentioned. Specific resistance of electrode film A mounting table for a plasma etching or ashing apparatus on which a substrate including a semiconductor device having a gate oxide film is mounted,
A conductor member connected to a high-frequency power source for plasma generation and a high-frequency power source for ion attraction;
A dielectric layer embedded in a central portion of the upper surface of the conductor member;
An electrostatic chuck mounted on the dielectric layer;
A conductive film disposed between the substrate and the dielectric layer;
The electrostatic chuck has an electrode film connected to a high-voltage DC power source,
The conductive film satisfies a condition represented by the following formula (3), and the electrode film satisfies a condition represented by the following formula (4).
115 Ω / □ ≦ ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ (3)
However, ρ _s1 : surface resistivity of the conductive film 115Ω / □ ≦ ρ _s2 (4)
Where ρ _s2 : surface resistivity of the electrode film The mounting table for a plasma etching or ashing apparatus according to claim 1 or 2, wherein the conductive film has a surface resistivity ρ _s1 of 304 Ω / □ or less. The mounting table for a plasma etching or ashing apparatus according to claim 1, wherein the conductive film hides the dielectric layer when the conductive film is viewed from the substrate side. 5. The mounting table for plasma etching or ashing apparatus according to claim 1, wherein a surface resistivity ρ _s1 of the conductive film is smaller than a surface resistivity ρ _s2 of the electrode film. 6. The conductive member and the electrostatic chuck are bonded and bonded to each other, and the conductive film is sandwiched between the conductive member and the electrostatic chuck. 2. A mounting table for the plasma etching or ashing apparatus according to 1. 7. The mounting for plasma etching or ashing apparatus according to claim 6, wherein the conductive film is formed on a sheet made of resin, and the sheet is adhered to a surface of the conductive member or the electrostatic chuck. Stand. The mounting table for a plasma etching or ashing apparatus according to claim 6, wherein the conductive film is formed on a surface of the conductor member or the electrostatic chuck. 9. The mounting table for a plasma etching or ashing apparatus according to claim 7, wherein the conductive film is formed by vapor deposition. 6. The mounting table for a plasma etching or ashing apparatus according to claim 1, wherein the conductive film is built in the electrostatic chuck. A mounting table on which a substrate including a semiconductor device having a gate oxide film is mounted;
The mounting table includes a conductive member connected to a high-frequency power source for plasma generation and a high-frequency power source for ion attraction, a dielectric layer embedded in a central portion of the upper surface of the conductive member, and a top surface of the dielectric layer. A plasma etching or ashing apparatus having an electrostatic chuck placed on the substrate and a conductive film disposed between the substrate and the dielectric layer,
The electrostatic chuck has an electrode film connected to a high-voltage DC power source,
The plasma etching or ashing apparatus, wherein the conductive film satisfies a condition represented by the following formula (1), and the electrode film satisfies a condition represented by the following formula (2).
δ ₁ / z ₁ ≧ 85 and ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ (1)
However, δ ₁ = (ρ _v1 / (μ ₁ πf)) ^1/2
Where z _{1 is} the thickness of the conductive film, δ ₁ is the skin depth of the conductive film with respect to the high-frequency power applied from the high-frequency power source for generating plasma, and f is the high-frequency applied from the high-frequency power source for generating plasma. Frequency of power, π: circularity, μ ₁ : permeability of the conductive film, ρ _v1 : specific resistance of the conductive film, ρ _s1 : surface resistivity of the conductive film δ ₂ / z ₂ ≧ 85 (2) )
However, δ ₂ = (ρ _v2 / (μ ₂ πf)) ^1/2
Where z _{2 is} the thickness of the electrode film, δ ₂ is the skin depth of the electrode film with respect to the high-frequency power applied from the high-frequency power source for generating plasma, μ _{2 is} the magnetic permeability of the electrode film, and ρ _{v2 is the} above-mentioned. Specific resistance of electrode film A mounting table on which a substrate including a semiconductor device having a gate oxide film is mounted;
The mounting table includes a conductive member connected to a high-frequency power source for plasma generation and a high-frequency power source for ion attraction, a dielectric layer embedded in a central portion of the upper surface of the conductive member, and a top surface of the dielectric layer. A plasma etching or ashing apparatus having an electrostatic chuck placed on the substrate and a conductive film disposed between the substrate and the dielectric layer,
The electrostatic chuck has an electrode film connected to a high-voltage DC power source,
The plasma etching or ashing apparatus, wherein the conductive film satisfies a condition expressed by the following formula (3), and the electrode film satisfies a condition expressed by the following formula (4).
115 Ω / □ ≦ ρ _s1 ≦ 2.67 × 10 ⁵ Ω / □ (3)
However, ρ _s1 : surface resistivity of the conductive film 115Ω / □ ≦ ρ _s2 (4)
Where ρ _s2 : surface resistivity of the electrode film