JP5233093B2 - Mounting table for plasma processing apparatus and plasma processing apparatus - Google Patents

Description

  The present invention relates to a mounting table for mounting a substrate to be processed such as a semiconductor wafer subjected to plasma processing, and a plasma processing apparatus including the mounting table.

  There are many semiconductor device manufacturing processes for processing a substrate by converting a processing gas into plasma, such as dry etching or ashing. In a plasma processing apparatus that performs such processing, for example, a pair of parallel plate-like electrodes are disposed so as to oppose each other, and high-frequency power is applied between these electrodes, whereby the processing gas introduced into the apparatus is A type of substrate in which a substrate to be processed, such as a semiconductor wafer (hereinafter referred to as a wafer), which has been converted into plasma and placed on the lower electrode, is processed.

  In recent years, in plasma processing, there has been an increase in processing that requires “low energy, high density plasma” in which ion energy in plasma is low and electron density is high. For this reason, the frequency of the high-frequency power for generating plasma may be very high, for example, 100 MHz, compared to the conventional frequency (for example, about ten MH). However, when the frequency of the applied power is increased, the electric field strength tends to increase at the center of the electrode surface, that is, the region corresponding to the center of the wafer, while the electric field strength tends to decrease at the peripheral portion. In this way, when the electric field strength distribution is non-uniform, the electron density of the generated plasma is also non-uniform, and the processing speed and the like vary depending on the position in the wafer. There was a problem that results could not be obtained.

  In order to solve such a problem, Patent Document 1 discloses, for example, that a dielectric having a relative dielectric constant of about 3.5 to 8.5 such as ceramics is embedded in the central portion of the opposing surface of one electrode to determine the electric field strength distribution. A plasma processing apparatus is described which is uniform and improves the in-plane uniformity of the plasma processing.

  This dielectric embedding will be described with reference to FIG. 3B described later. The high-frequency current that has propagated through the surface from the lower part of the conductor member 21 that forms the lower electrode and reached the upper part is expressed as follows. A part of the surface of the dielectric chuck 24 leaks to the electrostatic chuck 23 side and passes through the dielectric 24 constituting the electrostatic chuck 23, and the interface between the dielectric 24 and the conductor member 21 (conductor member). 21 surface) toward the outside. Here, in the part where the dielectric 22 for making the plasma uniform is provided, the high-frequency current is deeper than the other part and causes TM mode cavity cylindrical resonance to occur, and as a result, the plasma is generated from above the wafer W surface. The electric field in the central portion supplied to the wafer W can be lowered, and the electric field in the wafer W surface becomes uniform. This discussion is made on the assumption that the specific resistance of the electrode film 25 for electrostatic chuck is large.

However, the high-frequency current that has propagated from the bottom of the conductor member 21 to the top and reached the top, the dielectric 24 of the electrostatic chuck 23, and the dielectric 22 embedded in order to make the plasma uniform return from below the wafer. A part of the high-frequency current reaching the peripheral edge of W escapes to the outside of the wafer W. For this reason, the potential of the plasma above the peripheral portion of the wafer W becomes low, and the etching rate of the peripheral portion of the wafer W becomes slower than that of the central portion, which causes a non-uniform etching in-plane.
JP 2004-363552 A: page 15, paragraphs 84 to 85

  The present invention has been made based on such circumstances, and the object thereof is to increase the plasma processing speed at the peripheral edge of the substrate to be processed, thereby improving the in-plane uniformity of the plasma processing. Another object of the present invention is to provide a mounting table for a plasma processing apparatus and a plasma processing apparatus including the mounting table.

A mounting table for a plasma processing apparatus according to the present invention is a mounting table for a plasma processing apparatus for mounting a substrate to be processed on a mounting surface,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to suppress the high-frequency current propagated on the surface of the conductor member from escaping to the outside of the substrate to be processed and to generate the TM mode cavity cylinder resonance more efficiently, the upper surface side is at least the periphery of the substrate to be processed. The lower surface side is provided in contact with the peripheral portion of the conductive member not covered with the first dielectric layer, and the relative dielectric constant is higher than that of the first dielectric layer, and A second dielectric layer having a value of 100 or more ,
The outer edge of the first dielectric layer is located inside the outer edge of the substrate to be processed .
Another invention is a mounting table for a plasma processing apparatus for mounting a substrate to be processed on a mounting surface,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to prevent the high-frequency current propagated on the surface of the conductor member from escaping to the outside of the substrate to be processed, the upper surface side is in contact with at least the peripheral portion of the substrate to be processed, while the lower surface side is the first dielectric layer. A second dielectric layer provided so as to be in contact with a peripheral edge of the conductive member that is not covered by the first dielectric layer, and having a relative dielectric constant higher than that of the first dielectric layer,
The ratio of the lateral size of the first dielectric layer to the lateral size of the substrate to be processed is greater than 0 and not more than 0.96.

At this time, the second dielectric layer is provided from a position corresponding to the central portion of the substrate to be processed to a position corresponding to the peripheral portion, and the second dielectric layer satisfies the following conditions. It is preferable that an electrode film for an electrostatic chuck is embedded.
δ / t ≧ 1,000
However, δ = (2 / ωμσ) ^1/2 , ω = 2πf, σ = 1 / ρ
Where t is the thickness of the electrode film for the electrostatic chuck, δ is the skin depth of the electrode film for the electrostatic chuck with respect to the high-frequency power supplied from the high-frequency power supply, f is the frequency of the high-frequency power supplied from the high-frequency power supply, π: Circumferential ratio, μ: Magnetic permeability of electrode for electrostatic chuck, ρ: Specific resistance of electrode for electrostatic chuck Still another invention is a plasma treatment for mounting a substrate to be processed on a mounting surface. A mounting table for the device,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to prevent the high-frequency current that has propagated through the surface of the conductor member from escaping to the outside of the substrate to be processed, it is provided on the conductor member so as to be in contact with at least the peripheral edge of the substrate to be processed, and the relative dielectric constant is 100 or more second dielectric layers,
A dielectric layer for electrostatic chuck is provided on the first dielectric layer, and the second dielectric layer is provided so as to surround the dielectric layer for electrostatic chuck ,
The outer edge of the first dielectric layer is located inside the outer edge of the substrate to be processed .
Here, it is preferable that the first dielectric layer is formed in a columnar shape to generate a TM mode hollow cylindrical resonance, or the thickness thereof is smaller in the peripheral portion than in the central portion. . The frequency of the high frequency power supplied from the high frequency power source is preferably 13 MHz or more.

  According to the mounting table for a plasma processing apparatus according to the present invention, the first dielectric is embedded in the central portion, thereby generating a TM mode hollow cylindrical resonance inside the first dielectric, and the electric field in the region. By reducing the strength, the region having a large electric field strength in the mountain-shaped electric field strength distribution is flattened. In addition, a second dielectric layer having a high relative dielectric constant, which serves as a high-frequency current path, is provided at least at a position corresponding to the peripheral edge of the substrate to be processed, so that the high-frequency current is outward from the peripheral edge of the substrate to be processed. By relaxing the phenomenon of emission, TM mode cavity cylinder resonance is efficiently generated. As a result, the potential of the central portion supplied to the plasma from the surface of the substrate to be processed can be lowered, and the electric field in the surface of the substrate to be processed becomes uniform. Can be improved.

  An embodiment in which a mounting table according to the present invention is applied to a plasma processing apparatus as an etching apparatus will be described with reference to FIG. FIG. 1 shows an example of a RIE (Reactive Ion Etching) plasma processing apparatus 1. The plasma processing apparatus 1 includes, for example, a processing container 11 formed of a vacuum chamber whose inside is a sealed space, a mounting table 2 disposed in the center of the bottom surface in the processing container 11, and the mounting table 2 above the mounting table 2. An upper electrode 41 provided to face the mounting table 2 is provided.

  The processing container 11 includes a small-diameter cylindrical upper chamber 11a and a large-diameter cylindrical lower chamber 11b. The upper chamber 11a and the lower chamber 11b communicate with each other, and the entire processing container 11 is configured to be airtight. In the upper chamber 11a, the mounting table 2, the upper electrode 41, and the like are stored, and in the lower chamber 11b, the mounting table 2 is supported and a support plate 17 that stores piping and the like is stored. An exhaust device 14 is connected to the exhaust port 12 on the bottom surface of the lower chamber 11b through an exhaust pipe 13. A pressure adjusting unit (not shown) is connected to the exhaust device 14, and the pressure adjusting unit is configured to evacuate the entire processing container 11 by a signal from a control unit (not shown) to maintain a desired degree of vacuum. Has been. On the other hand, a loading / unloading port 15 for a wafer W, which is a substrate to be processed, is provided on the side surface of the upper chamber 11a. The loading / unloading port 15 can be opened and closed by a gate valve 16. The processing container 11 is made of a conductive member such as aluminum and is grounded.

  The mounting table 2 includes a lower electrode 21 for plasma generation, which is a conductor member made of, for example, aluminum, a dielectric 22 embedded so as to cover the center of the upper surface of the lower electrode 21 in order to uniformly adjust the electric field, The electrostatic chuck 23 for fixing the wafer W is stacked in this order from below. The lower electrode 21 is fixed to a support base 21 a installed on the support plate 17 via an insulating member 31, and is in a state of being sufficiently electrically floated with respect to the processing container 11.

  A coolant channel 32 for allowing a coolant to flow therethrough is formed in the lower electrode 21, and the coolant flows through the coolant channel 32, whereby the lower electrode 21 is cooled, and the mounting surface on the upper surface of the electrostatic chuck 23. The wafer W placed on the substrate is cooled to a desired temperature.

  Further, the electrostatic chuck 23 is provided with a through hole 33 for releasing a heat conductive backside gas for enhancing heat transfer between the mounting surface and the back surface of the wafer W. The through-hole 33 communicates with a gas flow path 34 formed in the lower electrode 21 and the like, and a back side such as helium (He) supplied from a gas supply unit (not shown) through the gas flow path 34. Gas is released.

  The lower electrode 21 has a first high-frequency power source 51a that supplies, for example, a high-frequency power having a frequency of 100 MHz, and a second high-frequency power that has a frequency lower than that of the first high-frequency power source 51a, for example. A high-frequency power source 51b is connected via matching units 52a and 52b, respectively. The high-frequency power supplied from the first high-frequency power source 51a plays a role of converting a processing gas, which will be described later, into plasma, and the high-frequency power supplied from the second high-frequency power source 51b applies bias power to the wafer W. It plays a role of drawing ions in the plasma to the surface of the wafer W.

  A focus ring 35 is disposed on the outer periphery of the upper surface of the lower electrode 21 so as to surround the electrostatic chuck 23. The focus ring 35 plays a role of adjusting the plasma state in the outer region of the peripheral portion of the wafer W, for example, spreading the plasma more than the wafer W and improving the uniformity of the etching rate within the wafer surface.

  A baffle plate 18 is provided outside the lower side of the support base 21a so as to surround the support base 21a. The baffle plate 18 rectifies the flow of the processing gas by flowing the processing gas in the upper chamber 11a to the lower chamber 11b through a gap formed between the baffle plate 18 and the wall of the upper chamber 11a. Play a role as a board.

  The upper electrode 41 is formed in a hollow shape, and a gas shower head is formed by, for example, uniformly distributing a large number of gas supply holes 42 for supplying the processing gas into the processing container 11 on the lower surface thereof. Is configured. A gas introduction pipe 43 is provided at the center of the upper surface of the upper electrode 41, and the gas introduction pipe 43 passes through the center of the upper surface of the processing vessel 11 and is connected upstream to the processing gas supply source 45. The processing gas supply source 45 has a processing gas supply amount control mechanism (not shown), and can control supply / disconnection and increase / decrease of the processing gas supply amount to the plasma processing apparatus 1. ing. Further, a conductive path is formed between the upper electrode 41 and the processing container 11 by fixing the upper electrode 41 to the wall portion of the upper chamber 11a.

  Furthermore, around the upper chamber 11a, two multipole ring magnets 56a and 56b are arranged above and below the loading / unloading port 15. The multi-pole ring magnets 56a and 56b are arranged such that a plurality of anisotropic segment columnar magnets are attached to a ring-shaped magnetic body casing, and the adjacent segment columnar magnets are opposite to each other. Has been. As a result, magnetic lines of force are formed between adjacent segment columnar magnets, a magnetic field is formed in the peripheral portion of the processing space between the upper electrode 41 and the lower electrode 21, and plasma can be confined in the processing space. In addition, it is good also as an apparatus structure which does not have the multipole ring magnets 56a and 56b.

  With the above apparatus configuration, a pair of parallel plate electrodes including the lower electrode 21 and the upper electrode 41 are formed in the processing vessel 11 (upper chamber 11a) of the plasma processing apparatus 1. After the inside of the processing vessel 11 is adjusted to a vacuum pressure, the processing gas is converted into plasma by introducing the processing gas and supplying high frequency power from the high frequency power sources 51a and 51b, and the high frequency current is changed from the lower electrode 21 to the plasma to the upper electrode 41. → The wall of the processing vessel 11 → flows through a path consisting of ground. By such an action of the plasma processing apparatus 1, the wafer W fixed on the mounting table 2 is etched by plasma.

  Next, the mounting table 2 according to the present embodiment will be described in detail with reference to FIG. In addition, in the longitudinal side view of the mounting table 2 shown in FIG. 2, descriptions of the refrigerant flow path 32 and the backside gas through-hole 33 are omitted.

A lower dielectric layer 22 which is a first dielectric layer is embedded in the center of the upper surface of the lower electrode 21 as shown in FIG. The lower dielectric layer 22 has a function of weakening the electric field strength in the region where the dielectric layer 22 is embedded. The lower dielectric layer 22 is made of ceramics having a relative dielectric constant (ε ₂₂ ) whose main component is alumina (Al ₂ O ₃ ), for example. The lower dielectric layer 22 has, for example, a cylindrical shape with a thickness of 5 mm and a diameter Φ ₂₂ = 288 mm.

Next, the electrostatic chuck 23 will be described. The electrostatic chuck 23 has, for example, a disk shape with a diameter approximately the same as that of the upper surface portion of the lower electrode 21 and a thickness of 1 mm, and second dielectric layers on the upper surface side and the lower surface side. For example, an electrode film 25 having a thickness of about 0.3 mm is sandwiched between (hereinafter referred to as the upper dielectric layer 24). The upper dielectric layer 24 is composed of a high dielectric material having a dielectric constant (ε ₂₄ ) of 100 or more. The electrode film 25 is made of an electrode material in which 35 wt% of molybdenum carbide (MoC) is contained in alumina (Al ₂ O ₃ ), for example, and has a thickness of 15 μm and a specific resistance of 30 Ωcm. Here, the electrode film 25 is configured to satisfy the following conditions so that the high frequency current cannot pass through the electrode film 25 and the effect of embedding the lower dielectric layer 22 cannot be exhibited. Yes.
δ / t ≧ 1,000
However, δ = (2 / ωμσ) ^1/2 , ω = 2πf, σ = 1 / ρ
Where t: thickness [m] of the electrode film 25, δ: skin depth [m] of the electrode film 25 with respect to the high frequency power supplied from the high frequency power supply 51a, f: frequency of the high frequency power supplied from the high frequency power supply 51a, π; circumference, μ; permeability of electrode film 25 [H / m], ρ; specific resistance of electrode film 25 [Ωm]
The electrode film 25 is connected to a high-voltage DC power supply 55 via a switch 53 and a resistor 54, and when high-voltage DC power is applied to the electrode film 25 from the high-voltage DC power supply 55, the upper dielectric layer of the electrostatic chuck 23. The wafer W is electrostatically attracted to the upper surface of the electrostatic chuck 23 which is a mounting surface by the Coulomb force generated on the surface 24.

Further, the upper dielectric layer 24 serves as a component of the electrostatic chuck 23 described above, and in addition to the function of fixing the wafer W on the mounting surface, the high frequency power between the lower electrode 21 and the peripheral portion of the wafer W. It also has a function to make it easier to pass through. That is, as shown in FIG. 2B, when the wafer W is placed, the lower electrode 21 and the peripheral portion of the wafer W sandwich the upper dielectric layer 24. Since the impedance in this portion is determined by the capacitance of the upper dielectric layer 24, if the capacitance of the upper dielectric layer 24 is C ₂₄ and the angular frequency of the high frequency power is ω, the impedance between the lower electrode 21 and the peripheral edge of the wafer W is set. The impedance value is represented by Z ₂₄ = j (−1 / ωC ₂₄ ). Here, the capacitance of the upper dielectric layer 24 is C ₂₄ = ε ₀ ε ₂₄ (S / d) (ε ₀ : dielectric constant of vacuum, S: area of the upper dielectric layer 24 at the peripheral portion, d: upper dielectric layer 24), the upper dielectric layer 24 is formed using a high dielectric material having a relative dielectric constant ε ₂₄ of 100 or more as described above, whereby the lower electrode 21 and the peripheral portion of the wafer W are formed. the impedance value Z ₂₄ between the high-frequency current is likely to flow is smaller than the other regions. Since the high-frequency current easily flows, the phenomenon that the high-frequency current escapes to the outside of the wafer W is suppressed, and the electric field strength in that region is increased as compared with the case where the upper dielectric layer 24 is not provided.

  By configuring the mounting table 2 according to the embodiment as described above, the in-plane uniformity of plasma processing on the wafer W can be improved. The possible reasons are described below. A part of the high-frequency current supplied from the first high-frequency power source 51 a and propagated through the surface of the lower electrode 21 from the surface of the wafer W is shown in FIG. 3A, and the upper dielectric layer 24 of the electrostatic chuck 23. And flows to the surface of the upper electrode 21 via, and leaks toward the center of the wafer W while leaking. Since the lower dielectric layer 22 is embedded in the central portion, the high frequency current propagating along the surface of the wafer W passes through the lower dielectric layer 22 and passes through the interface between the lower dielectric layer 22 and the upper electrode 21. Propagate to the outside. Here, the electrode film 25 of the electrostatic chuck 23 has a high specific resistance and uses a material satisfying the condition of δ / t ≧ 1,000 with respect to the high-frequency current. It can penetrate the membrane 25. In other words, even if the electrode film 25 is present, the lower dielectric 22 can be seen from the plasma, so that the plasma potential lowering action caused by the high-frequency current passing through the lower dielectric 22 at the center of the wafer W is impaired. There is nothing.

  In this embodiment, since the upper dielectric layer 24 having a high dielectric constant constituting the electrostatic chuck 23 is provided over the periphery of the wafer W, the upper electrode 21 and the wafer W are viewed from the high frequency power. Are in a state where they are short-circuited by the upper dielectric layer 24. As a result, the high-frequency current that has propagated from the bottom of the lower electrode 21 to the top and reached the top, and the high-frequency current that has returned from below the top dielectric layer 24 and the bottom dielectric layer 22 to the peripheral edge of the wafer W are The RF power supplied directly to the plasma without passing through the wafer W from the lower electrode 21 so as to go to the center of the wafer W can be reduced. As a result, RF power is supplied through the upper peripheral edge of the wafer W, so that in-plane uniformity of the electron density in the plasma can be enhanced in combination with the lower dielectric layer 22. Therefore, for example, in-plane uniformity can be improved for plasma processing such as etching processing. On the other hand, when the upper dielectric layer 24 having a high relative dielectric constant does not exist, as described with reference to FIG. , The density of the plasma above it becomes low, and the in-plane uniformity of the plasma treatment cannot be improved.

  In addition, since the high dielectric constant member also exhibits ferroelectricity, the conventional electrostatic attraction force can be exerted on the wafer W even if the high-voltage DC power applied to the electrostatic chuck 23 is reduced. Efficiency is improved.

  The configurations of the lower dielectric layer 22 and the upper dielectric layer 24 are not limited to those shown in the embodiment. For example, as shown in FIG. 4, an annular upper dielectric layer 24 may be provided in a region in contact with the peripheral edge of the wafer W, and only the upper dielectric layer 24 may be made of a high dielectric material. In this case, the dielectric 26 constituting the electrostatic chuck 23 may be configured to have a dielectric constant comparable to that of the lower dielectric layer 22, and further, the lower dielectric layer 22, the electrostatic chuck 23, May be integrated. Further, the mounting table 2 shown in the embodiment of FIG. 2 and the modification of FIG. 4 is not limited to the case where it has an electrostatic chuck function. For example, a type in which the wafer W is mechanically fixed by a mechanical chuck. It can also be applied to the mounting table.

  Further, the lower dielectric layer 22 is not limited to the cylindrical shape shown in the embodiment. For example, the lower dielectric layer 22 has a dome shape as shown in FIG. 5A or a conical shape as shown in FIG. It may be what constitutes. Thus, by making the thickness of the lower dielectric layer 22 smaller in the peripheral portion than in the central portion, the electric field intensity in the central portion is weakened more than in the peripheral portion, so that the distribution is more flat. be able to.

In addition, since the general linear expansion coefficient of ceramics used as the dielectric layer is 2 × 10 ⁻⁶ / ° C. to 11 × 10 ⁻⁶ / ° C., the linear expansion coefficient of the conductor member serving as an electrode is also in this range. It is preferable to use a material close to.

(simulation)
A parallel plate type plasma processing apparatus as shown in FIG. 1 was modeled, and a simulation was performed to estimate the electric field intensity distribution on the wafer.

A. Simulation conditions
Specific resistance of electrode film 25: 0.20 Ωm
Specific resistance of wafer W: 0.05Ωm
Plasma resistivity: 1.5Ωm
Relative dielectric constant ε ₂₂ of the lower dielectric layer ₂₂ : 8
The relative dielectric constant epsilon ₂₄ of the upper dielectric layer 24: each of the embodiments, applied by the setting conditions of Comparative Example Power: 2 kW (frequency 40 MHz, 2 conditions 100 MHz)
Here, the thickness of the upper dielectric layer 24 (electrostatic chuck 23) was 1 mm, the thickness of the electrode film 25 was 0.3 mm, and the thickness of the lower dielectric layer 22 was 5 mm. In addition, a simulation was performed for three conditions in which the diameter of the lower dielectric layer 22 was 278 mm, 288 mm, and 296 mm.

Under the above conditions, the electric field strength distribution in the radial direction of the wafer W placed on the placement surface of the placement table 2 according to each of the following examples and comparative examples was simulated.
Example 1
The relative dielectric constant of the upper dielectric layer 24 was set to ε ₂₄ = 100.
(Example 2)
The relative dielectric constant of the upper dielectric layer 24 was set to ε ₂₄ = 900.
(Comparative Example 1)
The relative dielectric constant of the upper dielectric layer 24 was set to ε ₂₄ = 12.

B. Simulation Results FIG. 6 and FIG. 7 show the simulation results of the electric field intensity distribution in each example and comparative example. FIG. 6 shows each simulation result when the frequency of the applied high frequency power is 40 MHz. 6A shows the results when the diameter of the lower dielectric layer 22 is 278 mm, and FIGS. 6B and 6C show the same results when the diameter of the lower dielectric layer 22 is 288 mm and 296 mm. The results are shown respectively. The horizontal axis of each graph indicates the distance [mm] from the center in the radial direction when the center of the wafer W is “0”. The vertical axis represents “specific electric field strength (= electric field strength E at each position obtained as a result of simulation / maximum value Emax of simulation results at all positions)”. In each simulation result, Example 1 is plotted with a circle (●), Example 2 is plotted with a triangle (▲), and Comparative Example 1 is plotted with a square (■).

According to simulation results, when the relative dielectric constant epsilon ₂₄ of the upper dielectric layer 24 is high, 100, 900, the wafer W without being affected with varying diameter of the lower dielectric layer 22 of the peripheral portion The electric field strength can be increased in the region ((●) and (▲) in FIGS. 6A to 6C). In contrast, when the dielectric constant epsilon ₂₄ of the upper dielectric layer 24 is 12 and if you can enhance the electric field intensity in the region of the periphery of the wafer W by the diameter of the lower dielectric layer 22 (FIG. 6 It can be seen that (a), (■) in FIG. 6 (b), and the electric field strength can hardly be increased ((■) in FIG. 6 (c)). It can also be seen that even if the electric field strength can be increased, the effect is small compared to the case where a high dielectric material is used.

  FIG. 7 shows each simulation result when the frequency of the applied high-frequency power is 100 MHz. FIG. 7A shows the results when the diameter of the lower dielectric layer 22 is 278 mm, and FIGS. 7B and 7C show the same results when the diameter of the lower dielectric layer 22 is 288 mm and 296 mm. The results are shown respectively. Moreover, the simulation result of each Example and a comparative example is plotted with the same symbol as FIG.

According to simulation results, when the relative dielectric constant epsilon ₂₄ of the upper dielectric layer 24 is high, 100, 900, as well as the results frequency is 40 MHz, the effect of changing the diameter of the lower dielectric layer 22 Without receiving, the electric field strength can be increased in the peripheral area of the wafer W ((●), (▲) in FIGS. 7A to 7C). In contrast, enhance the electric field intensity in the region of the peripheral portion of the wafer W in 2 cases between the diameter of the lower dielectric layer 22 is 288mm and 296mm when the relative dielectric constant epsilon ₂₄ of the upper dielectric layer 24 is 12 (Fig. 7 (b), Fig. 7 (c) (■)). In particular, when the diameter of the upper dielectric layer 24 is 296 mm, the electric field strength in the peripheral region of the wafer W is weakened contrary to the purpose ((■) in FIG. 7C). It can also be seen that even when the electric field strength can be increased, the effect is small compared to the case where a high dielectric material is used ((■) in FIG. 7A). The use of the upper dielectric layer 24 having a high relative permittivity ε ₂₄ can increase the electric field strength in the peripheral region of the wafer W when high-frequency power having the frequency illustrated in the simulation is applied. It is not limited. For example, the same effect can be obtained even when high frequency power having a frequency of 13 MHz or 27 MHz is applied.

It is a vertical side view which shows an example of the plasma processing apparatus provided with the mounting base which concerns on embodiment. It is a vertical side view which shows an example of the mounting base which concerns on embodiment. It is explanatory drawing for demonstrating the effect | action of the said mounting stand. It is a vertical side view which shows the modification of the mounting base which concerns on embodiment. It is a vertical side view which shows the other modification of the mounting base which concerns on embodiment. It is a characteristic view which shows the result of the Example performed in order to confirm the effect of this invention. It is a characteristic view which shows the result of the Example performed in order to confirm the effect of this invention.

Explanation of symbols

W Wafer 1 Plasma processing apparatus 2 Mounting table 11 Processing vessel 11a Upper chamber 11b Lower chamber 12 Exhaust port 13 Exhaust pipe 14 Exhaust device 15 Carry-in / out port 16 Gate valve 17 Support plate 18 Baffle plate 21 Lower electrode 21a Support table 22 Lower dielectric layer (Dielectric)
23 Electrostatic chuck 24 Upper dielectric layer (dielectric)
25 Electrode film 26 Dielectric 31 Insulating member 32 Refrigerant flow path 33 Through hole 34 Gas flow path 35 Focus ring 41 Upper electrode 42 Gas supply hole 43 Gas introduction pipe 45 Process gas supply source 51a High frequency power supply (first high frequency power supply)
51b High frequency power supply (second high frequency power supply)
52a, 52b Matching device 53 Switch 54 Resistance 55 High-voltage DC power supply 56a, 56b Multipole ring magnet

Claims (8)

A mounting table for a plasma processing apparatus for mounting a substrate to be processed on a mounting surface,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to prevent the high-frequency current propagated on the surface of the conductor member from escaping to the outside of the substrate to be processed, the upper surface side is in contact with at least the peripheral portion of the substrate to be processed, while the lower surface side is the first dielectric layer. A second dielectric layer that is provided so as to be in contact with the peripheral edge of the conductive member that is not covered by the first dielectric layer, has a relative dielectric constant higher than that of the first dielectric layer, and has a value of 100 or more; equipped with a,
A mounting table for a plasma processing apparatus , wherein an outer edge of the first dielectric layer is located inside an outer edge of the substrate to be processed . A mounting table for a plasma processing apparatus for mounting a substrate to be processed on a mounting surface,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to prevent the high-frequency current propagated on the surface of the conductor member from escaping to the outside of the substrate to be processed, the upper surface side is in contact with at least the peripheral portion of the substrate to be processed, while the lower surface side is the first dielectric layer. A second dielectric layer provided so as to be in contact with a peripheral edge of the conductive member that is not covered by the first dielectric layer, and having a relative dielectric constant higher than that of the first dielectric layer,
A mounting table for a plasma processing apparatus, wherein a ratio of a horizontal size of the first dielectric layer to a horizontal size of the substrate to be processed is greater than 0 and 0.96 or less. The second dielectric layer is provided from a position corresponding to the central portion of the substrate to be processed to a position corresponding to the peripheral portion, and the second dielectric layer has an electrostatic chuck that satisfies the following conditions: The mounting table for a plasma processing apparatus according to claim 1, wherein an electrode film is embedded.
δ / t ≧ 1,000
However, δ = (2 / ωμσ) ^1/2 , ω = 2πf, σ = 1 / ρ
Where t is the thickness of the electrode film for the electrostatic chuck, δ is the skin depth of the electrode film for the electrostatic chuck with respect to the high-frequency power supplied from the high-frequency power supply, f is the frequency of the high-frequency power supplied from the high-frequency power supply, π: Circumference ratio, μ: Magnetic permeability of electrode for electrostatic chuck, ρ: Specific resistance of electrode for electrostatic chuck A mounting table for a plasma processing apparatus for mounting a substrate to be processed on a mounting surface,
A conductor member connected to a high-frequency power source and serving also as an electrode for plasma generation or ion attraction in plasma;
A first dielectric layer that is provided so as to cover the central portion of the upper surface of the conductor member and uniformizes a high-frequency electric field applied to the plasma through the substrate to be processed;
In order to prevent the high-frequency current that has propagated through the surface of the conductor member from escaping to the outside of the substrate to be processed, it is provided on the conductor member so as to be in contact with at least the peripheral edge of the substrate to be processed, and the relative dielectric constant is 100 or more second dielectric layers,
A dielectric layer for electrostatic chuck is provided on the first dielectric layer, and the second dielectric layer is provided so as to surround the dielectric layer for electrostatic chuck ,
A mounting table for a plasma processing apparatus , wherein an outer edge of the first dielectric layer is located inside an outer edge of the substrate to be processed .   5. The mounting table for a plasma processing apparatus according to claim 1, wherein the first dielectric layer is formed in a columnar shape.   5. The mounting table for a plasma processing apparatus according to claim 1, wherein a thickness of the first dielectric layer is smaller in a peripheral portion than in a central portion.   The mounting table for a plasma processing apparatus according to claim 1, wherein a frequency of the high-frequency power supplied from the high-frequency power source is 13 MHz or more. A processing container in which plasma processing is performed on a substrate to be processed;
A processing gas introduction section for introducing a processing gas into the processing container;
A mounting table for a plasma processing apparatus according to any one of claims 1 to 7, provided in the processing container;
An upper electrode provided on the upper side of the mounting table so as to face the mounting table;
And a means for evacuating the inside of the processing vessel.

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