KR100923883B1 - Method of manufacturing coreless printed circuit board with stiffness - Google Patents

Method of manufacturing coreless printed circuit board with stiffness Download PDF

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Publication number
KR100923883B1
KR100923883B1 KR1020080038687A KR20080038687A KR100923883B1 KR 100923883 B1 KR100923883 B1 KR 100923883B1 KR 1020080038687 A KR1020080038687 A KR 1020080038687A KR 20080038687 A KR20080038687 A KR 20080038687A KR 100923883 B1 KR100923883 B1 KR 100923883B1
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South Korea
Prior art keywords
carrier
dry film
substrate
circuit board
printed circuit
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KR1020080038687A
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Korean (ko)
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김상진
조원진
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대덕전자 주식회사
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for manufacturing a coreless printed circuit board is provided to obtain sufficient stiffness on a substrate by selectively removing a carrier according to a pattern shape. CONSTITUTION: An insulation layer and a copper layer are stacked on one surface of a carrier(102) used as a core. A pad mounting a copper circuit and a chip is formed according to a circuit pattern by photographing/etching/plating. A dry film is coated on the surface of a carrier. A dry film pattern mask is formed by selectively etching the dry film to expose the pad to mount a semiconductor chip. The exposed carrier is peeled off using the dry film with the pattern as a mask.

Description

강도가 부가된 코어 리스 인쇄회로기판 제조 방법{METHOD OF MANUFACTURING CORELESS PRINTED CIRCUIT BOARD WITH STIFFNESS}Coreless printed circuit board manufacturing method with added strength {METHOD OF MANUFACTURING CORELESS PRINTED CIRCUIT BOARD WITH STIFFNESS}

본 발명은 인쇄회로기판(PCB; Printed Circuit Board) 제조 기술에 관한 것으로, 특히 코어 리스 인쇄회로기판(Coreless PCB) 제조 공법에 관한 것이다. 보다 상세하게는, 본 발명은 코어 리스 패키지 기판(coreless package substrate)의 두께가 너무 얇아서 파손이 발생하는 것을 방지하기 위한 강도 보강 기술에 관한 것이다.The present invention relates to a printed circuit board (PCB) manufacturing technology, and more particularly to a coreless PCB manufacturing method. More specifically, the present invention relates to strength reinforcement techniques to prevent breakage from occurring because the thickness of the coreless package substrate is too thin.

반도체 칩을 기판에 직접 실장하는 플립 칩 기술에 있어서 부품의 크기를 소형화하기 위하여, 캐리어(carrier)를 내층 코어로 하여 적층 프로세스를 진행하여 동박 패드 및 회로를 형성한 후 캐리어를 분리 제거함으로써(이러한 연유에서 "코어 리스 기판"이라 칭한다) 패키지 기판의 두께를 경박화 하는 기술이 통용되고 있다. 도1a 및 도1b는 종래 기술에 따라 제작된 코어 리스 기판의 모습을 나타낸 사진이다. 그런데, 도1a 및 도1b를 참조하면, 종래 기술에 따라 제작된 코어 리스 패키지 기판의 경우 두께가 50 ∼ 80 ㎛로 매우 얇아 도면부호 101로 표시한 가공 중인 기판의 모서리 부분이 휘어져 들려 올려지는 문제가 발생한다. In the flip chip technology in which a semiconductor chip is directly mounted on a substrate, in order to reduce the size of a component, a lamination process is performed using a carrier as an inner layer core to form a copper foil pad and a circuit, and then the carrier is separated and removed (such as A technique for thinning the thickness of a package substrate is commonly used in condensed milk. 1A and 1B are photographs showing a state of a coreless substrate manufactured according to the prior art. However, referring to FIGS. 1A and 1B, in the case of a coreless package substrate manufactured according to the prior art, the thickness of the coreless package substrate is 50 to 80 μm, so that the edge portion of the substrate under processing indicated by reference numeral 101 is bent and lifted up. Occurs.

도2a 및 도2b는 종래 기술에 따라 패키지 기판을 가공하여 최종적으로 캐리어를 제거하는 과정을 나타낸 도면이다. 도2a 및 도2b를 참조하면, 캐리어(102)의 두께는 대략 30 ∼ 120 ㎛ 이고, 실질적으로 분리되어서 패키지 기판으로 사용될 동박 패드와 접속 회로 형성 적층 부위(103)의 두께는 50 ∼ 80 ㎛ 이 된다. 2A and 2B are views illustrating a process of finally removing a carrier by processing a package substrate according to the related art. 2A and 2B, the thickness of the carrier 102 is approximately 30 to 120 μm, and the thickness of the copper foil pad and the connection circuit forming laminated portion 103 to be substantially separated and used as the package substrate is 50 to 80 μm. do.

따라서, 캐리어(102)를 알칼리 에칭 등을 통해 제거 분리하고 나면, 실질적으로 기판의 두께는 50 ∼ 80 ㎛ 으로 매우 얇아 도1a 및 도1b에 도시한 대로 기판이 휘어져서 후 가공이 어려워지거나, 후 가공 중에 파손되는 문제가 발생한다.Therefore, after the carrier 102 is removed and separated through alkali etching or the like, substantially the thickness of the substrate is 50 to 80 µm, so that the substrate is bent as shown in Figs. 1A and 1B, so that post-processing becomes difficult. There is a problem of breakage during processing.

따라서, 본 발명의 목적은 코어 리스 인쇄회로기판에 강도를 부가하여 후처리 가공 시에 파손되는 문제를 방지할 수 있는 제조 공법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a manufacturing method that can add strength to a coreless printed circuit board to prevent the problem of breakage during post-treatment.

상기 목적을 달성하기 위하여, 본 발명은 동박 패드와 주변 동박 회로 형성을 위한 적층 가공 공정 후 캐리어를 분리 제거하는 단계에서 캐리어 전체를 박리 제거하는 대신에 패턴 형성을 통해 캐리어를 선택적으로 식각 에칭함으로써 캐리어 자재를 부분적으로 남겨 두도록 함으로써 기판에 강도를 주는 것을 특징으로 한다. In order to achieve the above object, the present invention provides a carrier by selectively etching the carrier through the pattern formation instead of peeling off the entire carrier in the step of separating and removing the carrier after the lamination process for forming the copper foil pad and the peripheral copper foil circuit It is characterized by giving strength to the substrate by partially leaving the material.

본 발명은 종래 기술과 달리, 캐리어를 중심으로 양면에 적층되어 있는 적층물을 캐리어로부터 분리하여 한 쌍의 기판을 형성하는 과정에서, 일괄 알칼리 에칭 처리하여 캐리어를 박리 제거하는 것이 아니라 선택적으로 캐리어를 패턴 모양에 따라 제거하므로 기판에 남아 있는 캐리어 자재는 기판에 충분한 강도를 제공하게 되어 기판 파손의 위험을 제거하게 된다. The present invention, unlike the prior art, in the process of forming a pair of substrates by separating the laminate stacked on both sides of the carrier from the carrier to form a pair of substrates, instead of carrying out a batch alkali etching to remove the carrier to selectively remove the carrier By removing according to the pattern shape, the carrier material remaining on the substrate provides sufficient strength to the substrate, eliminating the risk of substrate breakage.

본 발명은 반도체 칩을 실장할 동박 패드를 구비한 코어 리스 인쇄회로기판을 제조하는 방법에 있어서, (a) 캐리어를 코어로 하여 상기 캐리어의 일 표면 위에 절연층과 동박층을 적층하고 사진/식각/도금 공정을 진행하여 선정된 회로 패턴에 따라 동박 회로와 칩을 실장할 동박 패드를 형성하는 단계; (b) 상기 캐리어 표면 위에 드라이 필름을 도포하고 상기 반도체 칩이 실장될 동박 패드가 노출되도록 상기 드라이 필름을 선택 식각하여 드라이 필름 패턴 마스크를 형성하는 단계; 및 (c) 상기 패턴 형성된 드라이 필름을 마스크로 하여 노출된 캐리어를 박리 제거하는 단계를 포함하는 인쇄회로기판 제조 방법을 제공한다.The present invention provides a method for manufacturing a coreless printed circuit board having a copper foil pad on which a semiconductor chip is to be mounted, the method comprising: (a) stacking an insulating layer and a copper foil layer on one surface of the carrier using a carrier as a core and photographing / etching; / Performing a plating process to form a copper foil pad to mount the copper foil circuit and the chip according to the selected circuit pattern; (b) applying a dry film on the carrier surface and selectively etching the dry film to expose a copper foil pad on which the semiconductor chip is to be mounted to form a dry film pattern mask; And (c) peeling and removing the exposed carrier using the patterned dry film as a mask.

이하에서는, 첨부 도면 도3 및 도4를 참조하여 본 발명의 양호한 실시예를 상세히 설명한다. Hereinafter, with reference to the accompanying drawings Figures 3 and 4 will be described in detail a preferred embodiment of the present invention.

도3을 참조하면, 본 발명은 종래 기술과 달리 캐리어(102) 전체를 일괄 박리 제거하는 대신에 반도체 칩이 실장될 부분만을 식각 제거하고 나머지 둘레 부위는 그대로 남아 있도록 선택적으로 마스크를 하여 식각한다.Referring to FIG. 3, the present invention, unlike the prior art, instead of collectively removing and removing the entire carrier 102, the mask is etched so that only the portion where the semiconductor chip is mounted is etched away and the remaining peripheral portion remains.

본 발명의 양호한 실시예로서, 캐리어를 선택적으로 식각하기 위하여 캐리어(102) 위에 드라이 필름(D/F)을 도포하고 반도체 칩이 실장될 동박 패드 위의 캐리어 자재가 식각 제거되도록 드라이 필름을 사진, 현상 및 식각하여 마스크 패턴을 형성한 후 에칭을 진행하여 캐리어를 도3과 같이 식각하여 기판에 선택적으로 남길 수 있다. In a preferred embodiment of the present invention, a dry film (D / F) is applied on the carrier 102 to selectively etch the carrier and the dry film is photographed so that the carrier material on the copper foil pad on which the semiconductor chip is to be mounted is etched away. After developing and etching to form a mask pattern, the etching may be performed to etch the carrier as shown in FIG. 3 to selectively remain on the substrate.

도4a 및 도4b는 각각 종래 기술과 본 발명의 경우 캐리어 자재를 식각 제거한 후 기판을 위에서 본 모습을 나타낸 도면이다. 도4a를 참조하면, 종래 기술의 경우 캐리어를 전면 식각 제거하므로 기판에 캐리어가 남아 있지 않게 된다.4A and 4B are views showing the substrate from above after etching away the carrier material in the prior art and the present invention, respectively. Referring to FIG. 4A, in the prior art, the carrier is etched away so that no carrier remains on the substrate.

이에 반하여, 도4b를 참조하면 본 발명의 경우 캐리어 자재를 칩이 실장할 부위(105)만을 선택적으로 식각 제거하므로 나머지 영역(106)에 캐리어 자재가 남아 있게 되어 기판에 강도를 부가하게 된다. 본 발명의 양호한 실시예에 따라, 기판에 남아 있는 캐리어 자재는 칩 실장 등 후처리 공정을 완료한 후에 에칭을 진행하여 일괄 제거할 수 있다. On the contrary, referring to FIG. 4B, the carrier material is selectively etched away from the portion 105 on which the chip is to be mounted so that the carrier material remains in the remaining area 106, thereby adding strength to the substrate. According to a preferred embodiment of the present invention, the carrier material remaining on the substrate can be collectively removed by etching after completing the post-treatment process such as chip mounting.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가 능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

본 발명은 코어 리스 패키지 기판을 제조하는 데 있어서, 칩 실장 이전 단계에서 기판이 너무 얇아서 기판이 파손되는 것을 방지할 수 있어서 플립 칩 공법에 적용하는 경우 기판 운송 또는 칩 실장 과정에 기판이 파손되는 문제점을 해결할 수 있다. According to the present invention, in the manufacture of a coreless package substrate, it is possible to prevent the substrate from being broken because the substrate is too thin in the pre-chip mounting step, so that the substrate is broken during the transportation or chip mounting process when applied to the flip chip method. Can be solved.

도1a 및 도1b는 종래 기술에 따라 제작된 코어 리스 기판의 모습을 나타낸 사진.1A and 1B are photographs showing a state of a coreless substrate manufactured according to the prior art.

도2a 및 도2b는 종래 기술에 따라 패키지 기판을 가공하여 최종적으로 캐리어를 제거하는 과정을 나타낸 도면.2A and 2B illustrate a process of finally removing a carrier by processing a package substrate according to the prior art;

도3은 본 발명에 따라 제품 지지 구조체를 선택적으로 마스크를 하여 식각한 모습을 나타낸 도면.Figure 3 is a view showing an etching by selectively masking the product support structure in accordance with the present invention.

도4a 및 도4b는 각각 종래 기술과 본 발명의 경우 캐리어 자재를 식각 제거한 후 기판을 위에서 본 모습을 나타낸 도면.4A and 4B are views showing the substrate from above after etching away the carrier material in the prior art and the present invention, respectively.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101: 휜 기판 부위101: substrate region

102: 캐리어102: carrier

103: 적층 부위103: lamination site

105: 칩이 실장 할 부위105: chip mounting area

Claims (1)

반도체 칩이 실장될 면에 제품의 휘어짐을 방지해 줄 수 있는 구조물을 구비한 코어 리스 인쇄회로기판을 제조하는 방법에 있어서,In the method for manufacturing a coreless printed circuit board having a structure that can prevent the bending of the product on the surface on which the semiconductor chip is to be mounted, (a) 캐리어를 코어로 하여 상기 캐리어의 일 표면 위에 절연층과 동박층을 적층하고 사진/식각/도금 공정을 진행하여 선정된 회로 패턴에 따라 동박 회로와 칩을 실장할 패드를 형성하는 단계; (a) laminating an insulating layer and a copper foil layer on one surface of the carrier using a carrier as a core, and performing a photo / etching / plating process to form a pad for mounting the copper foil circuit and the chip according to a selected circuit pattern; (b) 상기 캐리어 표면 위에 드라이 필름을 도포하고 상기 반도체 칩이 실장될 패드가 노출되도록 상기 드라이 필름을 선택 식각하여 드라이 필름 패턴 마스크를 형성하는 단계; 및(b) applying a dry film on the carrier surface and selectively etching the dry film to expose a pad on which the semiconductor chip is to be mounted to form a dry film pattern mask; And (c) 상기 패턴 형성된 드라이 필름을 마스크로 하여 노출된 캐리어를 박리 제거하는 단계; (c) peeling off the exposed carrier using the patterned dry film as a mask; 를 포함하는 인쇄회로기판 제조 방법.Printed circuit board manufacturing method comprising a.
KR1020080038687A 2008-04-25 2008-04-25 Method of manufacturing coreless printed circuit board with stiffness KR100923883B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060002086A (en) * 2004-07-01 2006-01-09 대덕전자 주식회사 Method of manufacturing flexible printed circuit board
JP2006332115A (en) 2005-05-23 2006-12-07 Ngk Spark Plug Co Ltd Coreless wiring board and its production process
JP3983146B2 (en) * 2002-09-17 2007-09-26 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of multilayer wiring board
JP2007266136A (en) 2006-03-27 2007-10-11 Fujitsu Ltd Multilayer wiring board, semiconductor device, and solder resist

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3983146B2 (en) * 2002-09-17 2007-09-26 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of multilayer wiring board
KR20060002086A (en) * 2004-07-01 2006-01-09 대덕전자 주식회사 Method of manufacturing flexible printed circuit board
JP2006332115A (en) 2005-05-23 2006-12-07 Ngk Spark Plug Co Ltd Coreless wiring board and its production process
JP2007266136A (en) 2006-03-27 2007-10-11 Fujitsu Ltd Multilayer wiring board, semiconductor device, and solder resist

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