KR100920342B1 - Driving apparatus and method of liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, and more particularly, to a driving apparatus and a driving method for alleviating flicker by changing the inversion driving method.

According to an embodiment of the present invention, an inverted signal selector is disposed between the signal controller and the data driver. The inverted signal selector consists of a T flip-flop and a multiplexer. The T flip-flop receives a signal for determining a period from the signal controller and applies the signal to the multiplexer. The multiplexer receives a plurality of inverted signals and sequentially applies a plurality of inverted signals to the data driver according to the output of the T flip-flop.

In this way, the flicker phenomenon caused by the specific inversion driving in the specific display pattern can be alleviated.

Flicker, Inverter, Signal Controller, Data Driver, Inverter Selector, Flip-Flop, Multiplexer

Description

Driving device and method of liquid crystal display device {DRIVING DEVICE AND METHOD OF LIQUID CRYSTAL DISPLAY}

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a circuit diagram of an inverted signal selector according to an exemplary embodiment of the present invention.

4 is a circuit diagram of an inverted signal selector according to another exemplary embodiment of the present invention.

The present invention relates to a driving device and a driving method of a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit forming a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. At this time, in order to prevent deterioration caused by the application of an electric field in one direction to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or dot.

However, such inversion driving causes an asymmetry in the pixel voltage of the liquid crystal capacitor when the polarity of the data voltage is periodically inverted into the positive and negative polarities, resulting in a flicker phenomenon that is a trembling phenomenon.

For example, this phenomenon is severe when 1 dot inversion driving is performed in a 1 dot pattern or 2 x 1 inversion driving is performed in a 2x1 dot pattern. For example, the 1 dot pattern refers to a display pattern in which odd-numbered pixels are turned on and even-numbered pixels are turned off in a red mode. Here, the application of the white voltage is called turn on, and the application of the black gray voltage is called turn off. The 2 × 1 dot pattern refers to a pair of red pixels that are turned on or off like a 1 dot pattern. When the red pixel turned on in the display pattern is inverted on a frame-by-frame basis, a difference in transmittance occurs due to the asymmetry of the pixel voltages in the positive polarity and the negative polarity described above, thereby making the flicker phenomenon stand out.                         

Accordingly, an object of the present invention is to provide a driving device and method for a liquid crystal display device which prevents a flicker phenomenon.

The driving device of the liquid crystal display device according to an embodiment of the present invention for achieving the technical problem is

A gradation voltage generator for generating a gradation voltage of positive and negative polarity;

A signal controller which supplies a control signal and a plurality of inverted signals,

An inverted signal selector for sequentially outputting the plurality of inverted signals according to the control signal;

And a data driver which has a polarity corresponding to the inversion signal from the inversion signal selector among the gray voltages from the gray voltage generator and selects and applies the gray voltage corresponding to the image data to the pixel as a data signal.

Here, the inversion signal selector,

A selection signal generator for generating a selection signal according to the control signal from the signal controller, and

It is preferable to include an inverted signal output unit for selecting and outputting the plurality of inverted signals according to the selection signal.

The select signal generator may include a first T flip-flop and the inverted signal output unit may include a multiplexer. The first T flip-flop may use the control signal as a clock input and a high signal as a toggle input, and the number of the plurality of inverted signals may be two.

Further, the number of the plurality of inverted signals is four,

The selection signal generator further includes a second T flip-flop having the output of the first T flip-flop as a clock input and a high signal as a toggle input.

Preferably, the output of the first T flip-flop and the output of the second T flip-flop are both applied as a select signal to the multiplexer.

In this case, the control signal is a vertical synchronization start signal or a signal synchronized thereto, or a gate clock signal or a signal synchronized thereto, and the plurality of inverted signals include a 1 dot inversion signal, a 2 × 1 dot inversion signal, a 2 dot inversion signal, It is preferable to include at least two or more of the four-dot inversion signal and the line inversion signal.

According to another aspect of the present invention, a driving method of a liquid crystal display including a plurality of pixels is provided.

Generating a plurality of inverted signals,

Generating a control signal for determining a selection period of the plurality of inverted signals;

Generating one or more selection signals for determining a selection order of the plurality of inverted signals according to the control signal,

Selecting and outputting the plurality of inverted signals according to the selection signal, and

And applying a data voltage having a polarity corresponding to the inverted signal to the pixel.                     

Here, the selection period is one frame or one horizontal period. The plurality of inversion signals may include at least two or more of a 1 dot inversion signal, a 2 × 1 dot inversion signal, a 2 dot inversion signal, a 4 dot inversion signal, and a line inversion signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a driving device and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver And an inverted signal selector 700, a gray voltage generator 800, and a signal controller 600 for controlling them.

As shown in FIG. 2, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 and a liquid crystal layer interposed therebetween, and as shown in FIG. In the view, the display signal lines G ₁ -G _n , D ₁ -D _m , and a plurality of pixels connected thereto and arranged in a substantially matrix form.

The display signal lines G ₁ -G _n and D ₁ -D _m are provided on the lower panel 100 and transmit a plurality of gate lines G ₁ -G _n to transmit a gate signal (also referred to as a “scan signal”). It includes a data line (D ₁ -D _m ) for transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , a liquid crystal capacitor C _lc , and a storage capacitor C _st connected thereto. It includes. The holding capacitor C _st can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _lc and the storage capacitor C _st .

The liquid crystal capacitor C _lc has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270 It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _st is formed by superimposing a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _st may be formed such that the pixel electrode 190 overlaps the front gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode 190 and the common electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The gray voltage generator 800 generates a plurality of gray voltages V + and V− of the positive (+) and the negative (-) related to the luminance of the liquid crystal display.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

The data driver 500 selects the gray voltages V + and V− from the gray voltage generator 800 and applies them to the pixel as data signals.

The signal controller 600 generates control signals for controlling operations of the gate driver 400, the data driver 500, the inverted signal selector 700, and the like, and outputs corresponding control signals to the gate driver 400 and the data. It is provided to the driver 500 and the inverted signal selector 700.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1, a data control signal CONT2, a common voltage V _com , and the like based on the input control signal, and outputs the image signals R, G, and B to the liquid crystal panel assembly ( After appropriately processing according to the operating conditions of 300, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed by the data driver. Export to 500. In addition, a plurality of inverted signals RVS are generated and sent to the inverted signal selector 700.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate-on pulse (the gate-on voltage section of the gate signal), a gate clock signal CPV controlling the output timing of the gate-on pulse, and a gate. An output enable signal OE or the like that limits the width of the on pulse.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The inverted signal selector 700 sequentially selects an inverted signal from the signal controller 600 and supplies the inverted signal to the data driver 500. Next, the data driver 500 selects a polarity of the pixel, stores it in an output buffer, and applies it to the pixel.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G' and B 'are selected by selecting a gray voltage having a polarity corresponding to each of the image data R', G 'and B' from the gray level voltage from 800 and having a polarity according to the inversion signal RVS. ) Is converted into the corresponding data voltage.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 400 assigns each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this way, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data signal to all the pixels.

Next, the structure and operation of the inverted signal selection unit 700 will be described in detail.

3 is a circuit diagram of an inversion signal selection unit 700 according to an embodiment of the present invention.

As shown, the inverted signal selector 700 includes a T flip-flop 710 and a multiplexer 750.

The T flip-flop 710 is connected to the signal controller 600 to receive the vertical synchronization start signal STV from the signal controller 600 to the clock input C and the toggle input T remains high (H). do. The T flip-flop 710 toggles the output according to the clock input C when the toggle input T is high (H). Since the toggle input T always remains high (H), the vertical synchronization start signal The output value changes every one period of (STV). However, since the period of the vertical synchronization start signal STV is one frame, the value of the T flip-flop 710 changes every frame. That is, it keeps low for one frame, and outputs high for the next frame, and repeatedly outputs it to the multiplexer 750.

The multiplexer 750 is connected to the T flip-flop 710 and the signal control unit 600 to receive the output of the T flip-flop 710 as the selection signal SS, and two inverted signals from the signal control unit 600, for example. For example, the 1 dot inversion signal I ₀ and the 2x1 dot inversion signal I ₁ are input. Here, 1 dot inversion is a method of applying data voltages having different polarities to neighboring pixels among pixels of one pixel row, and 2 × 1 dot inversion is applying data voltages of the same polarity to upper and lower pixels of two adjacent pixel rows. However, data voltages having different polarities are applied to pixels adjacent in the row direction.

The multiplexer 750 selects a 1 dot inversion signal I ₀ and a 2 × 1 dot inversion signal I ₁ according to the selection signal SS, and sends the same to the data driver 500. For example, when the selection signal SS is low, the 1 dot inversion signal I ₀ is output, and when the selection signal SS is high, the 2 × 1 dot inversion signal I ₁ is output.

In this way, 1 dot inversion and 2 x 1 dot inversion are alternately performed in units of frames. For example, as shown in Table 1, odd-numbered frames perform one dot inversion and even-numbered frames perform 2x1 dot inversion. Table 1 shows some of the four frames, and the first pixel row of the even-numbered frame with 2x1 dot inversion is one dot inversion.

+ - + - + - + - + - + - + - + - + - + - + - + - +

+ - + - + - - + + - - - + + - + + - - + + + - - +

- + - + - + - + - + - + - + - + - + - + - + - + -

- + - + - + - + - + + - + - + - + - + - - + - + +

In this case, 1 dot inversion or 2 × 1 dot inversion or 2 × 1 dot inversion is performed for each frame irrespective of display patterns such as 1 dot pattern or 2 × 1 dot pattern to change the inversion driving method. It is possible to alleviate the flicker phenomenon which has been a problem in the 2x1 dot inversion driving in one dot pattern.

4 is a block diagram of an inverted signal selector according to another exemplary embodiment of the present invention.

As shown, the inverted signal selector 700 includes two T flip-flops 710 and 730 and a multiplexer 750. The toggle input T of the T flip-flops 710 and 730 is held high (H), and the clock input C of the T flip-flop 710 is a signal for determining a period for changing the inversion scheme. CPV) and vertical sync start signal (STV). The clock input C of the T flip-flop 730 becomes the output signal of the flip-flop 710. In this case, the selection signal SS1 repeats "0, 1, 0, 1", and the selection signal SS2 repeats "0, 0, 1, 1", and the combination of these selects the inverted signal in sequence. Can be.

Four inversion signals are given to the input of the multiplexer 750, and four inversion signals are, for example, a one dot inversion signal, a 2 × 1 dot inversion signal, a four dot inversion signal, a line inversion signal, or the like. There is a number. In the above example, when the vertical synchronization start signal STV is selected as the inversion scheme change period signal, for example, the 4i-3th frame is 1 dot inverted, and the 4i-2th frame is 2 × 1 dot inverted, 4i- The first frame has 4 dot inversion and the 4i frame has line inversion.

On the contrary, when the gate clock signal CPV is clocked in, the gate clock signal becomes an inversion scheme changing cycle and the cycle becomes 1H described above. In addition, in order to group the four pixel rows into one group and to perform the inversion driving of the pixel rows in the group, the 2 × 1 dot inversion signal of the inversion signals is replaced with the two dot inversion signal. Thus, as shown in Table 2, the 4k-3rd pixel row performs 1 dot inversion, the 4k-2nd pixel row performs 2 dot inversion, the 4k-3rd pixel row performs 4 dot inversion, and the 4kth pixel row performs line inversion. Done. Table 2 shows one frame.

+ - + - + - + - + + - - + + - - + + + + - - - - + + + + + + + + - + - + - + - + - - + + - - + + - - - - + + + + - - - - - - - -

In this way, the flicker phenomenon that has been a problem due to the same inversion driving as that of the display pattern in the monochrome display pattern as well as the general display pattern can be solved.

For example, as described above, when one dot inversion is performed in one dot pattern, a specific dot turned on causes a difference in the charging voltages of the positive and negative liquid crystals in a process of repeating only positive and negative polarities sequentially. If flicker occurs due to the difference in transmittance, the order of application of the positive and negative polarities to a specific dot is changed or combined to average the charging voltage of the liquid crystal so that the transmittance is constant, thereby preventing flicker.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the same inversion driving as the specific display pattern is performed, the flicker phenomenon due to the difference in transmittance appears severely.

The inverted signal selector 700 is disposed between the signal controller 600 and the data driver 500, and the plurality of inverted signals are generated by the signal controller 600 and sent to the inverted signal selector 700 to select the inverted signal. By sequentially driving a plurality of inverted signals according to a predetermined period, the flicker phenomenon can be prevented.

Claims (11)

A driving device of a liquid crystal display device including a plurality of pixels, A gradation voltage generator for generating a gradation voltage of positive and negative polarity; A signal controller which supplies a control signal and a plurality of inverted signals, An inverted signal selector for sequentially outputting the plurality of inverted signals according to the control signal; A data driver which selects a gray voltage corresponding to the input image data having a polarity corresponding to the inverted signal from the inverted signal selector among the gray voltages from the gray voltage generator and applies it to the pixel as a data signal. Driving device for a liquid crystal display comprising a. In claim 1, The inversion signal selector, A selection signal generator for generating a selection signal according to the control signal from the signal controller, and An inverted signal output unit for selecting and outputting the plurality of inverted signals according to the selection signal Containing Driving device for liquid crystal display device. In claim 2, And wherein the selection signal generation unit includes a first T flip-flop and the inversion signal output unit includes a multiplexer. In claim 3, And the first T flip-flop drives the control signal as a clock input and a high signal as a toggle input. In claim 4, And a number of the plurality of inverted signals is two. In claim 4, The number of the plurality of inverted signals is four, The selection signal generator further includes a second T flip-flop having the output of the first T flip-flop as a clock input and a high signal as a toggle input. The output of the first T flip-flop and the output of the second T flip-flop are both applied as a select signal to the multiplexer. Driving device for liquid crystal display device. In any one of claims 1 to 6, And the control signal is a vertical synchronizing start signal or a signal synchronizing thereto, or a gate clock signal or a synchronizing signal thereto. In any one of claims 1 to 6, The plurality of inversion signals may include at least two or more of a 1 dot inversion signal, a 2 × 1 dot inversion signal, a 2 dot inversion signal, a 4 dot inversion signal, and a line inversion signal. A driving method of a liquid crystal display device including a plurality of pixels, Generating a plurality of inverted signals, Generating a control signal for determining a selection period of the plurality of inverted signals; Generating one or more selection signals for determining a selection order of the plurality of inverted signals according to the control signal, Selecting and outputting the plurality of inverted signals according to the selection signal, and Applying a data voltage having a polarity corresponding to the inversion signal to the pixel; Method of driving a liquid crystal display comprising a. In claim 9, And the selection period is one frame or one horizontal period. The method of claim 9 or 10, The plurality of inversion signals may include at least two or more of a 1 dot inversion signal, a 2 × 1 dot inversion signal, a 2 dot inversion signal, a 4 dot inversion signal, and a line inversion signal.

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