KR100848094B1 - Liquid crystal display device and a driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display and a driving method thereof.

According to the present invention, a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, and switching are formed in regions where the plurality of data lines and the gate lines intersect, and are connected to the gate lines and the data lines, respectively. In a liquid crystal display device including a plurality of pixels arranged in a matrix form having elements, a data voltage according to an image signal applied to the data line is supplied, and a gate voltage is supplied to the gate line, so that the data voltage is converted into a pixel. To be authorized. In particular, when the data voltage is applied to each pixel connected to one gate line, the polarity of the pixels on one screen is inverted in an irregular pattern according to an irregularly inverted control signal.

According to the present invention, as the polarity of each pixel is irregularly inverted on one screen of the liquid crystal display device which is inverted and driven, the display quality can be improved by removing flicker even when the warped pattern is displayed.

LCD, Reverse Drive, Flicker Removal

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND A DRIVING METHOD THEREOF}

1 is an exemplary diagram illustrating a luminance change caused by a worst pattern in a conventional liquid crystal display.

2 is a structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a circuit diagram of an inverted signal generator according to an embodiment of the present invention.

4 is an operation timing diagram of the inverted signal generator shown in FIG. 3.

5 is a polar arrangement arrangement example of the screen according to an embodiment of the present invention.

6 is an operation example of an inverted signal generator according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD) and a driving method thereof, and more particularly, to an apparatus and method for inverting and driving a liquid crystal display.

BACKGROUND ART A liquid crystal display device widely used as a representative flat panel display device these days generally includes two substrates facing each other and a liquid crystal layer therebetween. When voltage is applied to two kinds of electrodes provided on the inner surface of the substrate, an electric field is generated in the liquid crystal layer due to the potential difference between the two electrodes, and the arrangement of the liquid crystal molecules changes according to the intensity of the electric field. The change in the arrangement of the liquid crystal molecules changes the polarization of light passing through the liquid crystal layer, which is represented by a change in the transmittance of light by the polarizer provided on the outer surface of the substrate. Therefore, the transmittance of light passing through the liquid crystal display may be controlled by changing the electric field intensity by adjusting the potential difference between the two electrodes.

The liquid crystal display functionally includes a plurality of pixels arranged in a matrix form and a plurality of signal lines (for example, gate lines for transmitting a scan signal and data lines for transmitting an image signal) for transmitting signals to the pixels. The pixel includes a liquid crystal capacitor consisting of a pixel electrode and a common electrode and a liquid crystal layer between the two, and a switching element (eg, a thin film transistor (TFT)) connected to the pixel electrode. The switching element is also connected to the gate line and the data line to conduct when the gate signal is the gate-on voltage to transfer the image signal from the data line to the liquid crystal capacitor, and to turn off the image signal when the gate signal is the gate-off voltage. Do not.

However, if the electric field in one direction is continuously applied to the liquid crystal layer, the electrical and physical characteristics of the liquid crystal layer deteriorate, so it is necessary to constantly change the direction of the electric field. To change the direction of the electric field, the polarity of the voltage of the other electrode (ie, the pixel electrode) with respect to the voltage of one electrode (ie, the common electrode) must be reversed.

Such an inversion driving method includes a frame inversion for inverting polarity in units of frames, a line inversion for inverting polarities in units of lines, and a dot inversion for inverting polarities in units of pixels, among which line inversion or dot inversion is mainly used.

The frame inversion driving method inverts the charging polarity of the liquid crystal capacitor (the electric field between the pixel electrode and the common electrode) in units of frames with respect to one pixel. However, when all the pixels have the same charging polarity in one frame, the liquid crystal between two frames is inverted. The difference in transmittance is easily recognized, and flickering of the screen increases.

In order to improve the flicker characteristics of the frame inversion driving method, the number of pixels having a polarity of + and the number of pixels having a polarity of − are the same in one screen such as a line inversion driving method, a dot inversion driving method, and a column inversion driving method. The way to do it is mainly used.

However, liquid crystal displays have been frequently used for graphic displays (eg, MS-window), resulting in displaying a lot of wobbly patterns.

For example, when certain pixels having the same polarity are displayed in black, a difference in luminance from the pixels having the remaining polarity may occur, thereby causing flicker.

In other words, if a line having + polarity is marked in black in the line inversion driving method, flicker that flickers on a line-by-line basis occurs due to a large difference in luminance from a line having a polarity, and has a positive polarity in the column inversion driving method. If one column is displayed in black, the difference in luminance from that of the polar column is so great that flicker occurs.

In addition, when the liquid crystal display is driven by a conventional inversion driving method, vertical crosstalk occurs. That is, as the resolution of the liquid crystal display device gradually increases in resolution, the pixel electrode and the data line become closer to each other, thereby causing a crosstalk phenomenon in which the pixel potential is coupled to the data voltage.

An example of crosstalk generation is shown in FIG. For example, if the background displays the same gray level with the same polarity on one screen, as shown above, when a box or the like is displayed in a specific area of the screen, due to the data voltage applied to display the box, The mean potentials of the pixels of the upper and lower background parts are changed around the box.

Therefore, the technical problem to be achieved by the present invention is to solve the problems caused during the inversion driving in the conventional liquid crystal display device, and to improve the flicker and crosstalk characteristics.

 In accordance with an aspect of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, and an area in which the plurality of data lines and the gate lines cross each other. A liquid crystal panel including a plurality of pixels formed in a matrix and having a switching element connected to the gate line and the data line, respectively; A scan driver supplying a gate voltage to the gate line; And a data driver for supplying a data voltage corresponding to the image signal applied to the data line, wherein the polarity of each pixel in the liquid crystal panel is inverted into an irregular pattern.

The liquid crystal display may further include an inversion signal generator configured to generate an inversion control signal for inverting the polarity of the data voltage applied to the data driver. Here, the inversion control signal is varied at irregular intervals when the data voltage is applied to each pixel connected to one gate line, and the data driver inverts the polarity of the data voltage according to the inversion control signal.

On the other hand, the inverted signal generator includes a shift register including a plurality of flip-flops for shifting the input signal in accordance with the applied clock signal; It may include an operation unit including at least one operator for generating an inversion control signal by performing an exclusive OR operation on the signals output from two flip-flops of the plurality of flip-flops of the shift register.

In this case, the clock signal is preferably 1H cycles or more.

를 만족하도록 플립플롭의 개수를 설정하는 것이 바람직하다. If the period of the clock signal is referred to as P (H), the number of flip-flops in the shift register is referred to as N, and the vertical resolution of the liquid crystal display is referred to as VD,

It is preferable to set the number of flip-flops to satisfy.

In addition, a method of driving a liquid crystal display according to another aspect of the present invention may include a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, and a region in which the plurality of data lines and the gate lines intersect. A driving method of a liquid crystal display device comprising a plurality of pixels formed in a matrix form and having a switching element connected to the gate line and the data line, respectively, and supplying a data voltage according to an image signal applied to the data line. Doing; And supplying a gate voltage to the gate line so that the data voltage is applied to the pixel, and when applying the data voltage to each pixel connected to one gate line, a screen according to an irregularly inverted control signal. The polarity of the pixel at is reversed in an irregular pattern.

In the liquid crystal display device and the driving method thereof of the present invention having such a feature, the number of pixels having a positive polarity (+) and the number of pixels having a negative polarity (−) are the same on one screen.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram schematically illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 1, a gate driver 2, a data driver 3, a driving voltage generator 4, and a timing controller 5. ) And the gray voltage generator 6.

The liquid crystal panel 1 includes two substrates (eg, a TFT substrate and a color filter substrate), and a plurality of data lines and a plurality of gate lines cross each other on one substrate, and one gate line and one data line. Pixels are formed in each of these intersecting regions. Each gate electrode, source electrode, and drain electrode each include a TFT which is a switching element connected to a gate line, a data line, and a pixel electrode.

The timing controller 5 is an R (red), G (green), B (blue) data signal, a vertical synchronization signal (Vsync) that is a frame discrimination signal, and a row discrimination signal from a graphic controller (not shown) outside the LCD module. The digital synchronization signal Hsync and the main clock signal CLK are received to output a digital signal for driving the gate driver 2 and the data driver 3.

The timing signal output from the timing controller 5 to the gate driver 2 includes a vertical start signal Vstart for instructing the gate on voltage to be applied to the gate line, and the gate on voltage. There are a gate clock signal (hereinafter referred to as a "CPV signal") for sequentially applying to each gate line, and a gate on enable signal OE that enables the output of the gate driver 2.

In the timing signal output from the timing controller 5 to the data driver 3, digital data signals R (0: N), G (0: N), and B (0: N), which are passed from the graphic controller, are data. The horizontal start signal Hstart for inputting to the driver 3, the signal LOAD for commanding to apply the analog data signal converted in the data driver 3 to the panel, and the data shift in the data driver 3. There is a horizontal clock signal HCLK for.

In particular, in the exemplary embodiment of the present invention, a reverse signal (RVS) is generated to control the data driver 3 to be inverted and provided to the data driver 3. The inversion control signal RVS is an output polarity selection signal of the data driver 3 and is driven for at least 1H, with a minimum period of 2H.

The data driver 3 is also called a source driver and serves to lower the voltage value transmitted to each pixel in the liquid crystal panel 1 by one line. More specifically, the data driver 3 stores digital data from the timing controller 5 in a shift register in the data driver 5 and then, when a signal (LOAD signal) comes to command the data to be delivered to the liquid crystal panel 1, respectively. It selects a voltage corresponding to the data of and serves to transfer this voltage into the liquid crystal panel (1). In particular, in the exemplary embodiment of the present invention, the data driver 3 inverts the polarity of the data voltage according to the inversion control signal RVS provided from the timing controller 2 and provides the pixel in the liquid crystal panel 1.

The gate driver 2 is also called a scan driver, and serves to open a way for data from the data driver 3 to be transferred to the pixel. Each pixel of the liquid crystal panel 1 is turned on or off by a TFT serving as a switch, and the TFT is turned on or off by applying a constant voltage (Von, Voff) to a gate.

The gate driver 2 receives a CPV signal and an 0E signal output from the timing controller 5, and applies gate-on voltages G1, G2,..., Gm synchronized with the two signals CPV, OE to the gate line. Apply sequentially.

The gray voltage generator 6 generates a gray voltage equally divided according to the number of bits of RGB data provided from the graphic controller and provides the gray voltage to the data driver 3. The data driver 3 is driven by a signal output from the timing controller 5 to apply the data voltages D1, D2,..., Dn to all data lines in synchronization with the driving of the gate driver 2. Assuming that the data voltages D1, D2, ..., Dn are not significantly affected by the delay of the data lines, during the period in which the data voltages D1, D2, ..., Dn are synchronized with the high period of the gate-on voltages G1, G2, ..., Gm. The pixel is charged.

On the other hand, the Von voltage for turning on the gate of the TFT and the Voff voltage for turning off the gate are generated by the driving voltage generator 4. The driving voltage generator 4 generates not only the above-mentioned Von and Voff voltages but also a Vcom voltage which is a reference for the data voltage difference in the TFT, and the Vcom voltage is provided to the common electrode of each pixel.

In the liquid crystal display according to the exemplary embodiment of the present invention having such a structure, in order to prevent deterioration of image quality such as flicker and crosstalk generated by a conventional inversion driving method, pixels are arranged on a screen in units of lines, columns, and frames. Alternatively, an inversion control signal is generated to be inverted into an irregular pattern instead of being inverted into a regular pattern such as a pixel unit.

More specifically, the inversion control signal RVS is driven for at least 1H as the output polarity selection signal of the data driver 3, and the minimum period is 2H. The data driver 3 generally includes two types of line inverting ICs in which adjacent output voltages have the same polarity and column inverting ICs in which the adjacent output voltages have different polarities. When the inversion control signal RVS is provided to the data driver, which is a line inversion IC, at a period of 2H, the line inversion driving is performed. When the inversion control signal RVS is provided to the 2V period, the frame inversion driving is performed. On the other hand, when the inversion control signal RVS of the 2H period is provided to the data driver, which is a column inversion IC, the dot inversion driving is performed, and when the inversion control signal RVS of the 2V period is provided, the column inversion driving is performed.

In this way, the data driver, which is a line inversion IC or a column inversion IC, is inverted and outputted according to the inversion control signal RVS applied in a 2H cycle or a 2V cycle, thereby outputting a line unit or a column unit. Alternatively, the inversion is performed in a regular pattern such as a dot unit or a frame unit.

However, in the exemplary embodiment of the present invention, the inversion control signal RVS is generated such that the data voltage applied to each pixel is inverted irregularly in polarity.

3 illustrates the structure of an inversion control signal generator 51 according to an embodiment of the present invention for irregular polarity inversion of such pixels.

As shown in FIG. 3, the inversion control signal generator 51 according to the embodiment of the present invention provides a shift register 511 composed of a plurality of D-flip flops and an output of an arbitrary D-flip flop of the shift register. The operation unit 522 generates a reversal control signal RVS by performing a logical operation. Here, the output of the calculating section 522 is fed back to the shift register 511.

The shift register 511 is connected to the main clock signal CLK (herein, a signal of at least 1H period or more) to which the clock terminal CLK is applied from the outside, and the input terminal D is an output terminal of the D flip-flop at the front end ( A plurality of D flip-flops F1 to F12 connected to Q), and an input terminal of the first D flip-flop F1 is connected to an output terminal of the calculator 522. High-level signals are input to the preset terminal (/ PRE) and the clear terminal (/ CLR) of each D-flip-flop, so that signals input through the input terminal D are output through the output terminal Q. It is output as is.

The calculation unit 522 may include an exclusive OR gate (XOR) (hereinafter referred to as an XOR gate) and an XOR gate (XOR) that perform an exclusive OR operation on the output of the D-flip flop at two predetermined positions. Inverter I for outputting the inverted output signal is included.

In this embodiment, the shift register 511 includes twelve D-flip flops F1 to F12, and the XOR-gate XOR is the output of the fifth D-flip flop F5 and the last 12th D-. The logical operation of the output of the flip-flop (F12), but the present invention is not limited thereto.

Meanwhile, the inversion signal generator 51 according to the exemplary embodiment of the present invention is implemented as being included in the timing controller 5, but is not limited thereto and may be implemented separately from the timing controller.

4 shows the operation timing of the inverted signal generator according to the embodiment of the present invention having such a structure.

In the inverted signal generator 51 according to the embodiment of the present invention, the D-flip flops F1 to F12 of the shift register 511 are sequentially operated according to the clock signal CLK input from the outside. As shown in FIG. 4, when there is no signal input to the first first D-flip flop F1, the fifth D-flip flop F5 and the twelfth D-flip flop F12 located at two predetermined positions. ) Outputs a low level signal. Accordingly, the XOR gate XOR of the operation unit 522 outputs a high level signal by performing an exclusive OR on two low level signals. The signal output from the XOR gate XOR is inverted by the inverter I and output as a high level inversion control signal RVS.

The high level inversion control signal RVS is fed back to the shift register 511 while being output to the data driver 3, and the input signal is shifted according to the main clock signal CLK. Therefore, when the high level signal shifted according to the main clock signal CLK is input to the fifth D-flip flop F5 or is output, the high level signal is shifted to the twelfth D-flip flop F12. When input and output, the XOR gate XOR outputs a high level signal to generate a low level inversion control signal RVS.

In this way, the inversion control signal is output at a high level or a low level according to the output signal levels of two arbitrarily selected fifth D-flip flops F5 and the output signal levels of the twelfth D-flip flops F12. Since the inversion control signal is fed back to the shift register 511 and shifted according to the main clock signal CLK, as shown in FIG. 4, an inversion control signal RVS having an irregular high or low level can be obtained. have.

Meanwhile, a random inversion control signal may be generated by adjusting the number of D flip-flops used in the inverted signal generator operating in such a structure.

In an embodiment of the present invention, in order to generate a random inversion control signal (RVS) for an entire screen area, assuming that the number of D-flip flops is N in a liquid crystal panel having a vertical resolution of VD,

> VD

> VD

It is desirable to satisfy. In this case, the period of the main clock signal CLK is a 1H period. However, it is also possible to set the period of the main clock signal CLK to 1H or more. That is, a random inversion control signal RVS can be generated every line as a signal of 1H period, and a random inversion control signal RVS can be generated every two lines as a signal of 2H period.

Therefore, assuming that the period of the main clock signal CLK is "P",

Relationship is established.

Therefore, increasing the period of the main clock signal CLK can further reduce the number of D-flip flops for randomly generating the inversion control signal RVS.

An example of screen polarity arrangement in the case where an inversion control signal generated as described above in FIG. 5 is provided to the data driver 3 which is an IC for column inversion is shown.

As shown in (a) of FIG. 5, irregular patterns (line unit, dot unit, column unit, frame unit, etc.) are regularly performed according to the inversion control signal RVS in which the polarity of each pixel is irregularly operated in one screen. It is seen that the polarity is not reversed pattern).

Therefore, even when a warp pattern of a dot pattern or a horizontal or vertical stripe pattern is conventionally displayed (b to d), the number of positive polarity pixels (N (+ Since the number of pixels (N (−)) of-) and -polarity can be made substantially the same, the flicker characteristic is improved.

Meanwhile, one or more inversion control signals may be generated by the inversion signal generator and provided to the data driver.

For example, when one or more data drivers are used, one inversion control signal may be generated by the inversion signal generator and supplied to all data drivers, but one or more inversion controls may be used to alleviate the regularity of pixel charging polarity for each data driver. The signal may be generated and supplied to the corresponding data driver.

To this end, an output signal of two D-flip flops among a plurality of D-flip flops is selected to perform an exclusive OR operation as described above to generate one inverted control signal, and the A plurality of inversion control signals are generated by selecting an output signal and performing an exclusive OR operation to generate another inversion control signal.

In FIG. 6, an example in which five data drivers are provided and the inverted signal generator generates five inverted control signals is provided to each data driver.

As such, the data driving units can be controlled to control the pixel charging polarity of the pixel driving polarity due to the output regularity of the data driving unit in the horizontal direction, thereby obtaining more irregular charging polarity arrangement on one screen. This can be an effective countermeasure against conventional image quality defects.                     

The invention is susceptible to various modifications and implementations without departing from the scope of the following claims.

As described above, as the polarity of each pixel is irregularly inverted on one screen in the inverted driving liquid crystal, flicker may be removed to improve display quality even when a warped pattern is displayed.

Further, crosstalk generated at the vertical boundary of the image displayed on the screen can be eliminated.

Claims (7)

A plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, and a switching element formed in an area where the plurality of data lines and the gate lines intersect, and connected to the gate lines and the data lines, respectively. A liquid crystal panel including a plurality of pixels arranged in a matrix form; A scan driver supplying a gate voltage to the gate line; A data driver supplying a data voltage corresponding to an image signal applied to the data line; An inversion signal generator for generating an inversion control signal for inverting the polarity of the data voltage applied to the pixel to the data driver; The inversion control signal is varied at irregular intervals when the data voltage is applied to each pixel connected to one gate line, and the data driver inverts the polarity of the data voltage according to the inversion control signal. The method of claim 1, And inverting the polarity of each pixel in an irregular pattern in the liquid crystal panel. The method of claim 2, The inversion signal generator A shift register including a plurality of flip-flops for shifting an input signal in accordance with an applied clock signal; An operation unit including at least one calculator configured to generate an inversion control signal by performing an exclusive OR operation on signals output from two flip flops among the plurality of flip flops of the shift register Liquid crystal display comprising a. The method of claim 3, The clock signal has a 1H cycle or more. The method of claim 3, The period of the clock signal is referred to as P (H), the number of flip-flops in the shift register is referred to as N, and when the vertical resolution of the liquid crystal display is referred to as VD, the following conditions are satisfied.

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