KR100912592B1 - High electron mobility transistor and method for manufacturing thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility transistor and a method of manufacturing the same. More particularly, in the manufacture of a nitride semiconductor device having a recess structure, the source-drain recesses are made larger than the gate recesses so that the contact resistances of the source and drain regions are increased. The present invention relates to a high electron mobility transistor and a method of manufacturing the same, which can reduce the voltage, secure a normally off characteristic or improve an operating speed through a gate recess.

The high electron mobility transistor of the present invention is a transition layer, a gallium nitride buffer layer on the substrate; A 2DEG layer over the gallium nitride buffer layer; A barrier layer over the 2DEG layer; Source and drain electrodes present at portions of the barrier layer etched; A gate electrode in an etched portion such that the barrier layer remains thicker than a portion in contact with the sword and drain electrode; And an insulating layer covering the barrier layer in a region where the source, drain, and gate electrodes are not present.

High electron mobility transistor (HEMT), gallium nitride, recess, barrier layer, contact resistance

Description

High electron mobility transistor and method for manufacturing thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility transistor and a method of manufacturing the same. More particularly, in the manufacture of a nitride semiconductor device having a recess structure, the source-drain recesses are made larger than the gate recesses so that the contact resistances of the source and drain regions are increased. The present invention relates to a high electron mobility transistor and a method of manufacturing the same, which can lower the voltage, secure a normally off characteristic through a gate recess, or improve an operation speed.

Generally, semiconductor materials such as Si and GaAs are semiconductors such as Field Effect Transistors (FETs) and High Electron Mobility Transistors (HEMTs) for application to low power and low frequencies (in the case of Si). Widely used in devices.

In the case of Si, the electron mobility is low resulting in high source resistance, which severely degrades the high performance gain, and GaAs can operate at higher frequencies because of its higher electron mobility and lower source resistance than Si. However, GaAs has a relatively narrow bandgap and a relatively low breakdown voltage, so that GaAs-based HEMTs cannot provide high power at high frequencies.

Therefore, in high power and high frequency applications, attention has been paid to nitrides of group III elements, that is, wide bandgap semiconductor materials such as GaN compound semiconductors. These materials have higher breakdown voltages and electron saturation rates and are thermally / chemically stable compared to Si and GaAs. As such, GaN-based compound semiconductors have superior physical properties compared to other semiconductor materials. Thus, GaN-based compound semiconductors may be used as conventional semiconductor materials such as next-generation wireless and satellite communication systems requiring high power and high frequency characteristics, and engine control systems requiring high temperature and heat resistance. The scope of application is expanding to areas with limitations.

1 and 2 are cross-sectional views of a high electron mobility transistor having a conventional recess structure.

1 illustrates a substrate 100, a transition layer 110, a gallium nitride (GaN) layer 120, a 2DEG layer 130, an n-AlGaN layer 140, and an n + -AlGaN layer 150. In the high electron mobility transistor, the lower portion of the gate electrode 170c is lowered through the gate recess 160. However, in the case of the transistor as shown in FIG. 1, the contact resistance of the source and the drain is high.

2 shows the source 100 and the drain 100 after the substrate 100, the transition layer 110, the gallium nitride (GaN) layer 120, the 2DEG layer 130, the AlGaN layer 240, and the insulating layer 250 are formed. In order to reduce the contact resistance of the source and drain electrodes 270a and 270b, the contact portions of the structures are shown. However, in the case of the high electron mobility transistor as shown in FIG. 2, the resistance can be lowered by using the surface roughness through the source-drain recess, but since the depletion layer exists in the gate portion along the depletion layer of the surface, thereby preventing modulation by the gate. There is a disadvantage in reducing the operating speed.

The above and the related arts have disadvantages of high source and drain contact resistance or slow operation speed. The contact resistance is decreased through the source and drain recesses, and the normally off characteristics are satisfied or the operation speed is improved through the gate recesses. It is an object of the present invention to provide a high electron mobility transistor and a method of manufacturing the same.

The object of the present invention is a transition layer, a gallium nitride buffer layer on the substrate; A 2DEG layer over the gallium nitride buffer layer; A barrier layer over the 2DEG layer; Source and drain electrodes present at portions of the barrier layer etched; A gate electrode in an etched portion such that the barrier layer remains thicker than a portion in contact with the sword and drain electrode; And an insulating layer covering a barrier layer in a region where the source, drain, and gate electrodes are not present.

Another object of the present invention is to form a gallium nitride buffer layer on the substrate; Forming a barrier layer on the gallium nitride buffer layer; Etching a portion of the barrier layer to form a source-drain recess; Forming source and drain electrodes in the source-drain recesses; Heat treating the substrate; Forming and patterning an insulating layer on the substrate; Etching a portion of the barrier layer to form a gate recess thicker than the barrier layer thickness of the source-drain recess; And forming a gate electrode in the gate recess.

The present invention can reduce the contact resistance through the source-drain recess, improve the normally off characteristic or the operation speed through the gate recess, and the barrier layer surface roughness after the source-drain recess is the barrier layer surface roughness after the gate recess. By making it larger or equal, the ohmic contact characteristics of the source and drain electrodes due to the increase of the surface area are improved, thereby producing a high quality high electron mobility transistor having excellent electrical characteristics.

The terms or words used in this specification and claims are not to be construed as being limited to their ordinary or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a high electron mobility transistor according to the present invention.

First, as shown in FIG. 3A, a transition layer 310, a high resistance layer buffer layer 320, a 2DEG (2 Dimensional Electron Gas) layer 330, and a barrier layer 340 are formed on the substrate 300. ).

The substrate 300 may include a substrate such as silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), and the like, and the silicon substrate may be a silicon 100 substrate, a silicon 111 substrate, and silicon carbide. Substrates can be 3C, 4H, 6H and 15R polytypes and the like.

The buffer layer 320 is preferably formed of gallium nitride (GaN), and the formation of the gallium nitride buffer layer 320 may be an epitaxial growth method. For example, an epitaxial layer of gallium nitride is grown by using trimethylgalluim (TMG) and ammonia as sources of Ga and N and hydrogen as a carrier gas at temperatures of 800 to 1200 ° C.

The barrier layer 340 is formed to generate a 2DEG layer 330. The barrier layer 340 is a material having a bandgap larger than that of the buffer layer 320, and Al _x Ga _{1- x} N (0 <x ≦ 1) is preferable, and the value of x is 0.3 or more, preferably 0.3 to 0.9. Is selected from the range. Since the polarization of Al _x Ga _{1 - x} N is proportional to the concentration of Al, when the Al _x Ga _{1 - x} N layer is recessed when Al _x Ga _{1 - x} N with _x is less than 0.3, This is because no 2DEG is formed.

Al _x Ga _{1 - x} N has a larger bandgap than gallium nitride and this discontinuity in the energy bandgap results in free charge transfer from the larger bandgap to the smaller bandgap material. The charge builds up at the interface between these layers, creating a two-dimensional electron gas 2DEG that allows current to flow between the source and drain.

The Al _x Ga _{1 - x} N barrier layer 340 may be based on an epitaxial growth method. For example, it may be made by MOCVD using TMG (Trimethylgallium), TMA (Trimethylalluminium), and ammonia as sources of Ga, Al, and N at a temperature of 900 ° C. or higher, but is not limited thereto.

Next, as shown in FIG. 3B, after forming an etch stop layer and patterning the same, a barrier layer 340 is etched using the etch stop layer as a mask to form a source-drain recess 400.

Examples of the etch stop layer include silicon oxide films (SiO ₂ , SiO _x, etc.), silicon nitride films (Si _x N _y ), and other metal oxide films such as Hf, Al, Ti, and Zr, but silicon oxide films, silicon nitride films, or photoresist films may be used. desirable.

Although it can be etched by dry etching, wet etching, or a mixture of both, dry etching is preferable. Dry etching can be used for plasma etching, reactive ion etching and sputter ion etching, and the etching gas can be a gas containing Cl, such as BCl ₃ , CH ₂ Cl ₂ , and wet etching using KOH, NaOH, NH. ₄ may be a basic solution, such as OH solution.

The thickness T _SD of the barrier layer for lowering the contact resistance between the source and drain electrodes to form the ohmic junction is 10 nm or less, preferably less than the thickness of the barrier layer after the gate recess (FIGS. 3E and T _G ). Is between 0.1 and 10 nm.

Next, as illustrated in FIG. 3C, the source and drain electrodes 360a and 360b may be formed, and heat treatment may be performed to complete the ohmic junction after the source and drain electrodes are formed. The heat treatment may be performed at 600 to 1200 ° C. and may be performed by a rapid thermal process (RTP) to shorten the process time.

Next, as shown in FIG. 3D, a gate recess 410 is formed after depositing and patterning the insulating layer 350. The insulating layer may include a silicon oxide film (SiO ₂ , SiO _x, etc.), a silicon nitride film (Si _x N _y ), a gallium nitride film (GaN), an aluminum nitride film (AlN), or a material including at least one of them. Preferred and not limited thereto, and an oxide film, a nitride film, or the like of other metals may be used.

Patterning and gate recessing after the deposition of an insulating layer may cause plasma particles to damage or be embedded in the surface when the gate recess is performed by dry etching, and to act as a charge, and the polarity of the nitride itself. The charges on the surface induced by may form a depletion layer to prevent this.

The etching method for forming the gate recess may be etched by dry etching, wet etching, or a mixture thereof, but a method of mixing dry etching and wet etching is preferable. Dry etching can be used for plasma etching, reactive ion etching and sputter ion etching, and the etching gas can be a gas containing Cl, such as BCl ₃ , CH ₂ Cl ₂ , and wet etching using KOH, NaOH, NH. ₄ may be a basic solution, such as OH solution.

The roughness of the barrier layer surface (FIGS. 3B, 400a) after the source-drain recesses is preferably greater than or equal to the roughness of the barrier layer surface 410a after the gate recesses. This is because the electrode characteristics are improved by increasing the area, but when the gate recess has a rough surface, excessive leakage current occurs to deteriorate device characteristics. To this end, the gate recess is preferably etched by a dry and wet mixing method, and the source-drain recess is preferably dry etched.

The gate recess is less than the source-drain recess, which improves the transistor's normally off characteristics and speed. The normally off characteristic is the range where the 2DEG can disappear through the gate recess (occurs when the barrier layer thickness is reduced to the level of 10 nm), and the improvement in operating speed consists of the reduction of the parasitic resistance caused by the recess and the slight gate Recess can also reduce parasitic resistance. For this reason, the barrier layer thickness T _G of the portion where the final gate electrode is formed after the recess is preferably formed in a range of 10 to 100 nm.

Thereafter, as illustrated in FIG. 3E, a gate electrode 360c is formed in the gate recess 410. As the gate electrode material, a material capable of Schottky contact with a nitride semiconductor material, for example, nickel (Ni), platinum (Pt), tungsten (W), palladium (Pd), chromium (Cr), and copper (Cu) Metals, metal silicides, alloys thereof, and the like can be used.

FIG. 3F shows another embodiment of the present invention, and shows a Γ-type gate electrode 360c with the gate electrode hanging down toward the drain. This type can be expected to reduce the electric field at the gate edge (edge) to eliminate the current reduction phenomenon and increase the breakdown voltage. In addition to type Γ, T-type and field plate structures are also available.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

1 and 2 are cross-sectional views of a high electron mobility transistor having a conventional recess structure.

3A to 3F are cross-sectional views illustrating a method of manufacturing a high electron mobility transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

300 substrate 310 transition layer

320 gallium nitride layer 330 2DEG layer

340: barrier layer 350: insulating layer

360a, 360b, 360c: source, drain and gate electrodes

400: source-drain recess 410: gate recess

Claims (17)

A transition layer on the substrate, a gallium nitride buffer layer; A 2DEG layer over the gallium nitride buffer layer; A barrier layer over the 2DEG layer; Source and drain electrodes present at portions of the barrier layer etched; A gate electrode in an etched portion such that the barrier layer remains thicker than a portion in contact with the source and drain electrodes; And An insulating layer covering the barrier layer in a region where the source, drain, and gate electrodes do not exist A high electron mobility transistor comprising a. The method of claim 1, And the surface roughness of the lower layer of the source and drain electrodes is greater than or equal to the surface roughness of the lower layer of the gate electrode. The method of claim 1, A high electron mobility transistor having a barrier layer thickness of 0.1 to 10 nm in a portion where the source and drain electrodes contact each other. The method of claim 1, A high electron mobility transistor having a barrier layer thickness of 10 to 100nm at the portion where the gate electrode contacts. The method of claim 1, And the barrier layer is Al _x Ga _{1- x} N (0 <x ≦ 1). The method of claim 5, The composition ratio of Al _x Ga _{1 - x} N is a high electron mobility transistor having a range of x 0.3 to 0.9. The method of claim 1, The insulating layer may include a silicon nitride film, a silicon oxide film, a gallium nitride film (GaN), an aluminum or nitride film (AlN), or at least any one of them. Forming a gallium nitride buffer layer on the substrate; Forming a barrier layer on the gallium nitride buffer layer; Etching a portion of the barrier layer to form a source-drain recess; Forming source and drain electrodes in the source-drain recesses; Heat treating the substrate; Forming and patterning an insulating layer on the substrate; Etching a portion of the barrier layer to form a gate recess thicker than the barrier layer thickness of the source-drain recess; And Forming a gate electrode in the gate recess Method of manufacturing a high electron mobility transistor comprising a. The method of claim 8, And the barrier layer is Al _x Ga _{1- x} N (0 <x ≦ 1). The method of claim 9, The composition ratio of Al _x Ga _{1- x} N (0 <x ≦ 1) has a range of x from 0.3 to 0.9. The method of claim 8, And the source-drain recess is a dry etching method. The method of claim 8, And a barrier layer thickness of the source-drain recess is 0.1 to 10 nm. The method of claim 8, And a barrier layer thickness of the gate recess is between 10 and 100 nm. The method of claim 8, The insulating layer may include a silicon nitride film, a silicon oxide film, a gallium nitride film (GaN), an aluminum nitride film (AlN), or at least one of the above. The method of claim 8, The gate recess is a method of manufacturing a high electron mobility transistor formed by a method of mixing dry and wet etching. The method of claim 15, The dry etching is BCl ₃ Or an etching gas of CH ₂ Cl ₂ and wet etching using a KOH, NaOH or NH ₄ OH solution. The method of claim 8, And said barrier layer surface roughness after said source-drain recess is greater than or equal to the barrier layer surface roughness after gate recess.

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