KR100895376B1 - The method for manufacturing semiconductor device - Google Patents

The method for manufacturing semiconductor device Download PDF

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KR100895376B1
KR100895376B1 KR1020070110740A KR20070110740A KR100895376B1 KR 100895376 B1 KR100895376 B1 KR 100895376B1 KR 1020070110740 A KR1020070110740 A KR 1020070110740A KR 20070110740 A KR20070110740 A KR 20070110740A KR 100895376 B1 KR100895376 B1 KR 100895376B1
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South Korea
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interlayer insulating
layer
lower electrode
insulating layer
forming
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KR1020070110740A
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Korean (ko)
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김승완
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to improve short between wirings by preventing bunker diffusion in a lower region of a lower electrode. A gate(220) is formed in an upper part of a semiconductor substrate(200) including a dummy cell region(2000a) and a peripheral circuit region(2000b). A first interlayer insulating layer(210) is formed in the whole surface including the gate. A landing plug(230) is reclaimed in a contact hole passing through the first interlayer insulating layer. A second interlayer insulating layer(240) is formed on the first interlayer insulating layer including the landing plug. A bit line pattern(250) is formed in the second interlayer insulating layer. A lower layer(260) is formed in a side wall of the bit line pattern of the dummy cell region. A third interlayer insulating layer(270) is formed in the whole surface including the lower layer. A lower electrode contact hole exposing the landing plug is formed by etching the third interlayer insulating layer of the dummy cell region. A lower electrode contact plug(290) is formed by reclaiming a conductive layer in the lower electrode contact hole. An etch stop layer(280) is formed in the whole surface including the lower electrode contact plug. A side wall layer(292) connected the lower layer is formed by etching the etch stop layer of the dummy cell region and the third interlayer insulating layer.

Description

반도체 소자의 형성 방법{The Method for Manufacturing Semiconductor Device}The method for manufacturing a semiconductor device

도 1은 종래 기술에 따른 반도체 소자의 형성 방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

100, 200: 반도체 기판 110, 210: 제 1 층간 절연막100, 200: semiconductor substrate 110, 210: first interlayer insulating film

120, 220: 게이트 130, 230: 랜딩 플러그120, 220: gate 130, 230: landing plug

140, 240: 제 2 층간 절연막 150, 250: 비트 라인 패턴140 and 240: second interlayer insulating film 150 and 250: bit line pattern

260: 하부 레이어 170, 270: 제 3 층간 절연막 180, 280: 식각 정지막 185, 285: 하부 전극 콘택 홀260: lower layers 170 and 270: third interlayer insulating layer 180 and 280: etch stop layer 185 and 285: lower electrode contact hole

190, 290: 하부 전극 콘택 플러그 191: 희생 절연막 190 and 290: lower electrode contact plug 191: sacrificial insulating film

192: 하부 전극 193: 벙커(Bunker) 192: lower electrode 193: bunker

291: 감광막 패턴 292: 측벽 레이어 291 photoresist pattern 292 sidewall layer

1000a, 2000a: 더미 셀 영역 1000b, 2000b: 주변 회로 영역 1000a, 2000a: dummy cell area 1000b, 2000b: peripheral circuit area

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 하부 전극 형성 시 발생하는 벙커(Bunker) 형성을 방지할 수 있는 방법을 제공하기 위한 것으로, 벙커(Bunker) 방지를 위한 더미 셀(Dummy Cell) 영역과 주변 회로 영역 사이에 질화막 장벽을 제 3 층간 절연막 내의 하부와 측벽에 형성하는 것으로서, 하부 전극의 하부 영역에 벙커 확산을 방지하고, 배선 간의 쇼트(Short) 불량을 개선하여 반도체 소자의 특성을 향상시키는 기술을 개시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and to provide a method for preventing bunker formation occurring when forming a lower electrode, and including a dummy cell region for preventing bunkers. Forming a nitride film barrier between the peripheral circuit region on the lower side and the sidewall in the third interlayer insulating film, preventing bunker diffusion in the lower region of the lower electrode, improving short characteristics between wirings, and improving the characteristics of the semiconductor device. Discuss the technique.

도 1은 종래 기술에 따른 반도체 소자의 형성 방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of forming a semiconductor device according to the prior art.

도 1을 참조하면, 더미 셀 영역과 주변회로 영역이 구비된 반도체 기판(100) 상에 게이트(120)를 형성한 후, 상기 게이트(120)을 포함한 전체 표면상에 제 1 층간 절연막(110)을 형성한다. 제 1 층간 절연막(110)을 관통하는 콘택 홀을 형성하고, 이 콘택 홀에 도전층을 매립하여 랜딩 플러그(130)를 형성한다.Referring to FIG. 1, after a gate 120 is formed on a semiconductor substrate 100 having a dummy cell region and a peripheral circuit region, a first interlayer insulating layer 110 is formed on the entire surface including the gate 120. To form. A contact hole penetrating through the first interlayer insulating film 110 is formed, and a landing layer 130 is formed by filling a conductive layer in the contact hole.

다음으로, 랜딩플러그(130)를 포함한 제 1 층간 절연막(110) 상에 제 2 층간 절연막(140)을 형성한 후, 제 2 층간 절연막(140) 상에 비트라인 배선막과 비트라인 하드 마스크가 적층으로 된 비트라인 패턴(150)을 형성한다.Next, after the second interlayer insulating layer 140 is formed on the first interlayer insulating layer 110 including the landing plug 130, a bit line wiring layer and a bit line hard mask are formed on the second interlayer insulating layer 140. A stacked bit line pattern 150 is formed.

그 다음으로, 비트라인 패턴(150)을 포함한 전체 표면상에 제 3 층간 절연막(170)을 형성한다. 더미 셀 영역(1000a)의 제 3 층간 절연막(170)을 식각하여 랜딩 플러그(130)를 노출시키는 하부 전극 콘택홀(미도시)을 형성한다. 이후, 하부 전극 콘택홀에 도전층을 매립하여 하부 전극 콘택 플러그(190)를 형성한다. Next, a third interlayer insulating film 170 is formed on the entire surface including the bit line pattern 150. The third interlayer insulating layer 170 of the dummy cell region 1000a is etched to form a lower electrode contact hole (not shown) that exposes the landing plug 130. Thereafter, the conductive layer is embedded in the lower electrode contact hole to form the lower electrode contact plug 190.

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다음으로, 전체 표면 상부에 식각 정지막(180) 및 희생 절연막(191)을 형성한 후, 희생 절연막(191) 상에 감광막을 형성하고, 하부 전극 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(미도시)을 형성한다. Next, after the etch stop layer 180 and the sacrificial insulating film 191 is formed on the entire surface, a photoresist film is formed on the sacrificial insulating film 191, and the photoresist pattern is exposed through an exposure and development process using a lower electrode mask. Form a).

감광막 패턴을 마스크로 희생 절연막(191) 및 식각 정지막(180)을 식각하여 하부 전극 콘택 플러그(190)를 노출시키는 하부 전극(192)을 형성한다.The sacrificial insulating layer 191 and the etch stop layer 180 are etched using the photoresist pattern as a mask to form a lower electrode 192 exposing the lower electrode contact plug 190.

여기서, 커패시터의 용량 증대를 위해 희생 절연막(191)의 높이의 증가로 인해 하부 전극 형성 시 종횡비가 커진다. 하부 전극(192)이 하부의 하부 전극 콘택 플러그(190)와 오정렬(Mis-Align)이 발생하게 되면, 하부 전극 콘택 플러그(190) 주변의 제 3 층간 절연막(170)이 노출된다.Here, the aspect ratio increases when the lower electrode is formed due to an increase in the height of the sacrificial insulating layer 191 to increase the capacitance of the capacitor. When the lower electrode 192 is misaligned with the lower electrode contact plug 190, the third interlayer insulating layer 170 around the lower electrode contact plug 190 is exposed.

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이와 같이, 하부 전극 아래에 제 3 층간 절연막(170)이 노출되면, 후속 희생 절연막(191)의 습식 딥 아웃(Wet Dip-Out) 공정 시 노출된 제 3 층간 절연막(170) 방향으로 습식 용액이 침투하여 어택(Attack)을 발생시킨다. 이때, 습식 용액이 하부 전극(192)과 식각 정지막(180)의 경계 부분을 따라 제 3 층간 절연막(170) 방향으로 침투하여 벙커(Bunker, 193)를 발생시킨다. 이러한 벙커(193)는 일종의 보이드(Void)로서 소자의 오류를 발생시키는 원인으로 작용한다.As such, when the third interlayer insulating layer 170 is exposed under the lower electrode, the wet solution is directed toward the third interlayer insulating layer 170 exposed during the wet dip-out process of the subsequent sacrificial insulating layer 191. Infiltrate to create an attack. In this case, the wet solution penetrates toward the third interlayer insulating layer 170 along the boundary between the lower electrode 192 and the etch stop layer 180 to generate a bunker 193. The bunker 193 acts as a cause of device error as a kind of void.

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이러한 하부 전극 형성 공정 중, 하부 전극의 에치 백 공정과 오버레이 불량 등이 발생할 경우 하부 전극 저변부의 TIN 등의 전극이 소실되어 절연막이 노출되고, 딥 아웃 공정 시 노출된 층간 절연막이 더욱 소실되어 벙커(Bunker)가 발생하게 된다.During the lower electrode forming process, when the etch back process and the overlay failure of the lower electrode occur, the electrode such as TIN of the lower electrode bottom part is lost and the insulating film is exposed, and the exposed interlayer insulating film is further lost during the dip-out process and the bunker ( Bunker) will occur.

본 발명은 하부 전극 형성 시 발생하는 벙커(Bunker) 형성을 방지할 수 있는 방법을 제공하기 위한 것으로, 벙커(Bunker) 방지를 위한 더미 셀(Dummy Cell) 영역과 주변 회로 영역 사이에 질화막 장벽을 3 층간 절연막 내의 하부와 측벽에 형성하는 것으로서, 하부 전극의 하부 영역에 벙커 확산을 방지하고, 배선 간의 쇼트(Short) 불량을 개선하여 반도체 소자의 특성을 향상시키는 반도체 소자의 형성 방법을 제공하는 것을 목적으로 한다.The present invention is to provide a method for preventing the formation of bunkers (Bunker) occurs when forming the lower electrode, and the nitride film barrier between the dummy cell region and the peripheral circuit region to prevent the bunker (3) An object of the present invention is to provide a method of forming a semiconductor device, which is formed on the lower and sidewalls of an interlayer insulating film, which prevents bunker diffusion in the lower region of the lower electrode, improves short circuit between wirings, and improves the characteristics of the semiconductor device. It is done.

본 발명은 반도체 기판상에 비트라인 패턴을 형성하는 단계, 상기 비트라인 패턴을 포함한 전체 표면에 질화막을 형성하는 단계, 상기 질화막을 식각하여 더미 셀 영역의 비트라인 측벽에 하부 레이어를 형성하는 단계, 상기 하부 레이어를 포함한 전체 표면상에 층간 절연막을 형성하는 단계, 상기 층간 절연막을 식각하여 하부의 랜딩 플러그를 노출하는 하부 전극 콘택 플러그를 형성하는 단계, 상기 하부 전극 콘택 플러그를 포함한 전체 표면에 식각 정지막 및 감광막 패턴을 형성하는 단계 및 상기 감광막 패턴을 마스크로 더미 셀 영역의 식각 정지막 및 층간 절연막을 식각하여 하부 레이어에 접속되는 측벽 레이어를 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법을 제공한다. The present invention provides a method for forming a semiconductor device, the method comprising: forming a bit line pattern on a semiconductor substrate, forming a nitride film on the entire surface including the bit line pattern, etching the nitride film to form a lower layer on sidewalls of the bit line of the dummy cell region, Forming an interlayer insulating film on the entire surface including the lower layer, etching the interlayer insulating film to form a lower electrode contact plug that exposes a lower landing plug, and etch stops on the entire surface including the lower electrode contact plug A method of forming a semiconductor device comprising forming a film and a photoresist pattern, and forming a sidewall layer connected to the lower layer by etching the etch stop layer and the interlayer insulating layer of the dummy cell region using the photoresist pattern as a mask. .

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여기서, 상기 식각 정지막은 질화막으로 형성하는 것을 특징으로 한다.The etch stop layer may be formed of a nitride film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부한 도면을 참조하여 설명한다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장 된 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급된 경우에 그것은 다른 층 또는 기판상에 직접 형성될 수 있거나, 또는 그들 사이에 제 3의 층이 개재될 수도 있다. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween.

또한, 명세서 전체에 걸쳐서 동일한 참조 번호가 표시된 부분은 동일한 구성요소들을 나타낸다.Also, the same reference numerals throughout the specification represent the same components.

도 2a 내지 도 2d는 본 발명에 따라 형성된 반도체 소자를 도시한 단면도이다.2A through 2D are cross-sectional views illustrating semiconductor devices formed in accordance with the present invention.

도 2a를 참조하면, 더미 셀(Dummy Cell) 영역(2000a)과 주변회로 영역(2000b)이 구비된 반도체 기판(200) 상부에 게이트(220)를 형성한다. 상기 게이트(220)를 포함한 전체 표면상에 제 1 층간 절연막(210)을 형성한다.Referring to FIG. 2A, a gate 220 is formed on a semiconductor substrate 200 having a dummy cell region 2000a and a peripheral circuit region 2000b. The first interlayer insulating layer 210 is formed on the entire surface including the gate 220.

제 1 층간 절연막(210)을 관통하는 콘택 홀을 형성하고, 이 콘택 홀에 매립되는 랜딩 플러그(230)를 형성한다.A contact hole penetrating the first interlayer insulating layer 210 is formed, and a landing plug 230 embedded in the contact hole is formed.

다음으로, 랜딩플러그(230)를 포함한 제 1 층간 절연막(210) 상에 제 2 층간 절연막(240)을 형성한다.Next, a second interlayer insulating film 240 is formed on the first interlayer insulating film 210 including the landing plug 230.

제 2 층간 절연막(240) 상에 비트라인 배선막과 비트라인 하드 마스크의 적층으로 된 비트라인 패턴(250)을 형성한다. A bit line pattern 250 including a bit line wiring film and a bit line hard mask is formed on the second interlayer insulating layer 240.

그 다음으로, 비트라인 패턴(250)을 포함한 전체 표면에 질화막(미도시)을 형성한다. 질화막(미도시) 상에 감광막을 형성하고, 주변 회로 영역(2000b)에 인접한 더미 셀 영역(2000a)의 비트 라인 패턴의 측벽을 노출하는 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(미도시)을 형성한다. 감광막 패턴을 마스크로 질화막을 식각하여 더미 셀 영역(2000a)의 비트라인 패턴(250)의 측벽에 하부 레이어(260)을 형성한다. Next, a nitride film (not shown) is formed on the entire surface including the bit line pattern 250. A photoresist pattern is formed on the nitride film (not shown), and the photoresist pattern (not shown) is formed by an exposure and development process using a mask that exposes sidewalls of the bit line pattern of the dummy cell region 2000a adjacent to the peripheral circuit region 2000b. Form. The nitride layer is etched using the photoresist pattern as a mask to form a lower layer 260 on sidewalls of the bit line pattern 250 of the dummy cell region 2000a.

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도 2b를 참조하면, 하부 레이어(260)을 포함한 전체 표면에 제 3 층간 절연막(270)을 형성한다. 더미 셀 영역(2000a)의 제 3 층간 절연막(270)을 식각하여 랜딩 플러그(230)를 노출시키는 하부 전극 콘택홀(미도시)을 형성한다. 이후, 하부 전극 콘택홀에 도전층을 매립하여 하부 전극 콘택 플러그(290)를 형성한다.
이후, 하부 전극 콘택 플러그(290)를 포함한 전체 표면상에 식각 정지막(280)을 형성한다.Referring to FIG. 2B, a third interlayer insulating layer 270 is formed on the entire surface including the lower layer 260. The third interlayer insulating layer 270 of the dummy cell region 2000a is etched to form a lower electrode contact hole (not shown) that exposes the landing plug 230. Thereafter, a conductive layer is embedded in the lower electrode contact hole to form a lower electrode contact plug 290.
Thereafter, an etch stop layer 280 is formed on the entire surface including the lower electrode contact plug 290.

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도 2c 및 도 2d를 참조하면, 식각 정지막(280)을 포함한 전체 표면에 감광막을 형성한다. 하부 레이어(260)를 노출하기 위한 측벽 레이어 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(291)을 형성한다. 감광막 패턴(291)을 마스크로 더미 셀 영역(2000a)의 식각 정지막(280) 및 제 3 층간 절연막(270)을 식각하여 하부 레이어(260)와 접속되는 측벽 레이어(292)를 형성한다. 이때, 측벽 레이어(292)는 질화막 또는 절연막을 매립하여 벙커(Bunker)로 인한 불량을 방지하기 위한 장벽층이다.2C and 2D, a photosensitive film is formed on the entire surface including the etch stop film 280. The photosensitive film pattern 291 is formed by an exposure and development process using a sidewall layer mask for exposing the lower layer 260. The etch stop layer 280 and the third interlayer insulating layer 270 of the dummy cell region 2000a are etched using the photoresist pattern 291 as a mask to form sidewall layers 292 connected to the lower layer 260. In this case, the sidewall layer 292 is a barrier layer for preventing defects caused by bunkers by filling the nitride film or the insulating film.

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본 발명에 따른 반도체 소자의 형성 방법은 벙커(Bunker) 방지를 위한 더미 셀(Dummy Cell) 영역과 주변 회로 영역 사이에 질화막 장벽을 제 3 층간 절연막 내의 하부와 측벽에 형성하는 것으로서, 하부 전극의 하부 영역에 벙커 확산을 방지하고, 배선 간의 쇼트(Short) 불량을 개선하여 반도체 소자의 특성을 향상시키는 효과를 제공한다.      The method of forming a semiconductor device according to the present invention is to form a nitride barrier on the bottom and sidewalls of the third interlayer insulating film between a dummy cell region and a peripheral circuit region for preventing bunkers. It provides an effect of preventing bunker diffusion in the region and improving short defects between wirings to improve the characteristics of the semiconductor device.

아울러 본 발명의 바람직한 실시 예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.     In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

반도체 기판상에 비트라인 패턴을 형성하는 단계;Forming a bit line pattern on the semiconductor substrate; 상기 비트라인 패턴을 포함한 전체 표면에 질화막을 형성하는 단계;Forming a nitride film on the entire surface including the bit line pattern; 상기 질화막을 식각하여 더미 셀 영역의 비트라인 측벽에 하부 레이어를 형성하는 단계;Etching the nitride layer to form a lower layer on sidewalls of the bit lines of the dummy cell region; 상기 하부 레이어를 포함한 전체 표면상에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface including the lower layer; 상기 층간 절연막을 식각하여 하부의 랜딩 플러그를 노출하는 하부 전극 콘택 플러그를 형성하는 단계;Etching the interlayer insulating film to form a lower electrode contact plug exposing a lower landing plug; 상기 하부 전극 콘택 플러그를 포함한 전체 표면에 식각 정지막 및 감광막 패턴을 형성하는 단계; 및Forming an etch stop layer and a photoresist pattern on the entire surface including the lower electrode contact plug; And 상기 감광막 패턴을 마스크로 더미 셀 영역의 식각 정지막 및 층간 절연막을 식각하여 하부 레이어에 접속되는 측벽 레이어를 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법. Forming a sidewall layer connected to the lower layer by etching the etch stop film and the interlayer insulating film of the dummy cell region using the photosensitive film pattern as a mask. 제 1 항에 있어서,The method of claim 1, 상기 식각 정지막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The etching stop film is a method of forming a semiconductor device, characterized in that formed by the nitride film.
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KR20060031991A (en) * 2004-10-11 2006-04-14 주식회사 하이닉스반도체 Method for manufacturing capacitor in semiconductor device

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