KR100883157B1 - Semiconductor device employing dynamic circuit - Google Patents

Abstract

The present invention provides a semiconductor device including a plurality of function blocks and a selection signal generation circuit for supplying a selection signal to a function block for operating among the plurality of function blocks. The clock generation unit in the functional block is supplied with a selection signal and a system clock, generates a control clock based on the system clock in a period during which the selection signal is supplied, and generates the control clock in a period during which the selection signal is not supplied. Stop. The dynamic circuit installed inside the functional block does not operate because no control clock is given unless the selection signal is received. When the selection signal is received, a control clock is provided, and the precharge and discharge are repeated for each clock cycle to perform a predetermined function to consume power.

Description

Semiconductor device using dynamic circuits {SEMICONDUCTOR DEVICE EMPLOYING DYNAMIC CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a dynamic circuit, and more particularly to a semiconductor device for realizing power saving of a dynamic circuit.

In recent years, the power consumption of a semiconductor device is increasing with the integration of a semiconductor device. Therefore, power saving of a semiconductor device is demanded. As a circuit which suppresses power consumption, there are examples of a circuit described in Patent Document 1, for example. However, the technique described in Patent Document 1 relates to power saving of flip-flop circuits, and is not applicable to dynamic circuits in general.

The static circuit among the CM0S circuits, which can save power in nature, is formed by combining an n-type MOS transistor and a p-type MOS transistor according to the number of inputs. However, it is preferable that the p-type MOS transistor is slower in operation than the n-type MOS transistor, and is not connected in series as much as possible to speed up the circuit.

Fig. 1 is a diagram showing an eight input OR circuit realized by a static circuit. The eight input terminals a0 to a7 of the OR circuit of FIG. 1 are connected to the gates of the eight p-type MOS transistors 410 to 417 and the eight n-type MOS transistors 420 to 427, respectively. An inverter 430 is connected to the node 440 between the p-type MOS transistors 410 to 417 connected in series and the n-type MOS transistors 420 to 427 connected in parallel, and the output thereof is OR. It becomes the output terminal of the circuit.

In this OR circuit, when all 8 inputs a0 to a7 are at the low level (hereinafter referred to as L level), all the p-type MOS transistors 410 to 417 are turned on, and the node 440 is at the high level (hereinafter referred to as H level). . The L level inverted by the inverter 430 is output to the output z. In this case, since all eight p-type MOS transistors 417 to 410 must be conducted, the delay time becomes large. When the OR circuit with a large number of inputs is configured as a static circuit, since the p-type MOS transistors are connected in series, the operation speed becomes slow, which causes the operation speed of the entire apparatus to be slowed. Alternatively, since the number of logic stages must be increased to reduce the number of series of the p-type MOS transistors, the delay time for one stage is improved, but the improvement effect is small for the total delay time.

Here, a dynamic circuit has been proposed to improve the delay of the operation due to the p-type MOS transistor. Here, for simplicity, the dynamic circuit is described as an 8 input OR circuit as an example.

2 is a configuration diagram in which an eight-input OR circuit is realized by a dynamic circuit. Eight n-type transistors 510 to 517 connected in parallel are configured between the p-type MOS transistor 520 and the n-type MOS transistor 550 to which the clock CK is input. The input terminals b0 to b7 of the eight input OR circuit are connected to the gates of the n-type transistors 510 to 517, respectively. An inverter 540 is connected to a node 560 between eight n-type transistors 510 to 517 connected in parallel with the p-type MOS transistor 520, and its output is connected to an eight-input OR circuit. Is the output. The p-type MOS transistor 530 is provided for latching the H level of the node 560, and the output of the inverter 540 is also input to this gate.

In this circuit, when the clock CK becomes L level, the p-type MOS transistor 520 is turned on, the n-type MOS transistor 550 is turned off, and the node 560 is precharged. ) Becomes L level regardless of the values of the inputs a0 to a7 (precharge mode). When the clock CK becomes H level, the n-type MOS transistor 550 is turned on to output the calculation result (evolution mode). When the eight inputs b0 to b7 are all at the L level, the output z is at the L level because the node 560 is precharged by the p-type MOS transistor 530. In this case, the output z reset to the L level when the clock CK is at the L level is in the L level even after switching the clock CK to the H level. In other words, the delay time in this case is zero. On the other hand, when any one of the eight inputs b0 to b7 is at the H level, the node 560 is discharged when the H level is input to the clock CK, so that the output z is at the H level. The delay time in this case is only one inverter and two n-type MOS transistors in the path from ground to the output terminal.

In the case of the dynamic circuit, the delay time can be reduced compared to the static circuit.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-232339

Disclosure of the Invention

[Problem to Solve Invention]

However, in the static circuit, charging and discharging are performed only when there is a change in the output z in response to a change in the input, and power is not consumed when the input does not change and there is no change in the output z. In contrast, in the dynamic circuit, when any one of the inputs b0 to b7 is at the H level, precharge and discharge are performed for each clock CK cycle. Therefore, power consumption is generated even if there is no change in the inputs b0 to b7. In other words, the delay time can be reduced in the case of the dynamic circuit than in the static circuit, but the power consumption is larger than that in the static circuit.

It is therefore an object of the present invention to provide a semiconductor device which uses a dynamic circuit capable of high speed operation and which can reduce power consumption.

[Means for solving the problem]

In order to solve the above problems, according to the first aspect of the present invention, there is provided a semiconductor device including a plurality of functional blocks and a selection signal generation circuit for supplying a selection signal to a functional block to be operated among the plurality of functional blocks. And the plurality of functional blocks generate a control clock based on the system clock when the selection signal and the system clock are supplied and the selection signal is supplied, and control when the selection signal is not supplied. A p-type transistor to which the control clock is supplied to the gate and an n-type transistor to which an input signal is supplied to the gate are provided in series between the clock generation unit for stopping the generation of the clock, the power supply and ground, and the p-type transistor. And a node between and the n-type transistor is precharged in response to the supply of the control clock and the input It characterized in that it comprises a dynamic circuit in which up display according to a call.

In a first aspect of the invention, in a preferred embodiment, the clock generation unit is supplied with the selection signal and the system clock, starts generating the control clock enable signal in response to the supply of the selection signal, and the system clock. A clock control section for terminating the generation of the control clock enable signal in response to the end of one cycle of the cycle, the control clock enable signal and the system clock being supplied, and the system while the control clock enable signal is being supplied. And a clock generator for generating the control clock based on a clock and stopping the generation of the control clock while the control clock enable signal is not being supplied.

Further, in the first aspect of the present invention, in the preferred embodiment, when the power saving mode signal is supplied, generation of the control clock enable signal is started in response to the supply of the selection signal, and Generating the control clock enable signal upon completion of one cycle, and generating the control clock enable signal regardless of input of the selection signal when the power saving mode signal is not supplied. It characterized in that it comprises a control unit.

According to a second aspect of the present invention, there is provided a semiconductor memory including a plurality of memory blocks and an address free decoder for supplying a block selection signal to a memory block for reading or writing among the plurality of memory blocks. The plurality of memory blocks are supplied with the block selection signal and a system clock, and generate a control clock based on the system clock when the block selection signal is supplied, and when the block selection signal is not supplied. A clock generation unit for stopping generation of the control clock, a memory cell group for holding data, a row decoder for selecting word lines of data of the memory cells, a row driver for driving the word lines selected by the row decoder, and A column decoder for selecting a column of memory cells, and a line decoder in the column decoder A column driver for supplying a column selection signal CSL to the selected column, and an output circuit group for inputting the bit line of the memory cell group and outputting read data, wherein the row decoder, the row driver, and the column decoder And the column driver and the output circuit group, a p-type transistor in which the control clock is supplied to the gate and an n-type transistor in which an input signal is supplied to the gate are provided in series between the power supply and the ground. And a node between the n-type transistor and the node is precharged in response to the supply of the control clock and discharged according to the input signal.

In a second aspect of the invention, in a preferred embodiment the clock generation unit is supplied with the block select signal and a system clock, and starts generating a control clock enable signal in response to the supply of the block select signal, In response to the end of one cycle of the system clock, a clock control section for terminating generation of the control clock enable signal, the control clock enable signal and the system clock are supplied, and the control clock enable signal is supplied. And a clock generator for generating the control clock based on the system clock and stopping the generation of the control clock while the control clock enable signal is not being supplied.

Further, in the second aspect of the invention, in the preferred embodiment, the clock generation unit starts generating the control clock enable signal in response to the supply of the block selection signal when the power saving mode signal is being supplied. The generation of the control clock enable signal is terminated at the end of one cycle of the system clock, and when the power saving mode signal is not supplied, the control clock in regardless of the input of the block selection signal. And the clock controller generating the enable signal.

1 is a circuit diagram of an eight input OR circuit realized by a static circuit.

Fig. 2 is a circuit diagram of an eight input OR circuit realized by a dynamic circuit.

3 is a configuration diagram of a semiconductor device in accordance with the first embodiment of the present invention.

4 is a configuration diagram of a semiconductor device in accordance with a second embodiment of the present invention.

5 is a circuit diagram of a clock control unit installed in a clock generation unit.

6 is a circuit diagram of a clock generation unit installed in the clock generation unit.

7 is a timing chart according to a second embodiment of the present invention.

8 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention.

Fig. 9 is a circuit diagram of a clock control unit in the third embodiment of the present invention.

10 is a dynamic circuit system for power saving of a RAM memory system.

Fig. 11 is a timing chart of operations of the clock control unit and clock generation units 111 to 114 in the RAM system of this embodiment.

12 is a circuit diagram of a row decoder and a row driver.

13 shows a low-definition front end circuit.

14 is an operation explanatory diagram of an OR circuit in a read operation;

Fig. 15 is a table showing the degree of improvement in cycle time, access time, and power consumption of the RAM system of this embodiment.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described according to drawing. However, the technical scope of the present invention is not limited to these embodiments and extends to the matters described in the claims and their equivalents.

3 is a configuration diagram of a semiconductor device according to the first embodiment of the present invention. In the first embodiment, a plurality of functional blocks from 1 to N and a selection signal generation circuit 200 are provided outside the semiconductor device using the dynamic circuit. The system clock SCK is supplied to each functional block.

The selection signal generation circuit 200 selects the functional block by supplying the selection signal SLT to any one of the clock generation units 212 to 2N2 in the functional block to be selected. Hereinafter, the functional block 3 will be described as selected. When the function block 3 is selected, the selection signal generation circuit 200 supplies the selection signal SLT to the clock generation unit 232 in the function block 3. When the selection signal SLT is supplied, the clock generation unit 232 generates a control clock CCK based on the supplied system clock SCK. The control clock CCK includes a clock which delays the supplied system clock SCK, a clock having an L level of a short pulse width at the timing of the rising edge of the system clock SCK, and the like. The generated control clock CCK is supplied to the dynamic circuit group 233 in the function block 3. When the selection signal SLT is not supplied, the clock generation unit 232 does not generate the control clock CCK.

The dynamic circuit is a circuit as shown in Fig. 2, in which a p-type MOS transistor in which a control clock CCK is supplied to a gate is supplied between a power supply and ground, and an n-type MOS transistor in which an input signal b is supplied to a gate in series. The circuit between the p-type MOS transistor and the n-type MOS transistor is precharged in response to the supply of the control clock CCK, and discharged in accordance with the input signal b. However, the present invention is not limited to the OR circuit, but may be a simple inverter or an AND circuit. The dynamic circuit group 233 in the selected function block 3 is supplied with a control clock CCK to perform an operation of executing a predetermined function. At that time, precharging and discharging are repeated in response to the control clock CCK, and power is consumed. However, since the control clock CCK is not supplied to the dynamic circuit group in the non-selected functional block, no operation for executing a predetermined function is performed and power is not consumed.

In this manner, the semiconductor device according to the present embodiment selects a dynamic circuit to operate and limits the dynamic circuit for precharging and discharging, thereby reducing power consumption. Therefore, it is possible to realize a semiconductor device which uses a dynamic circuit capable of high speed operation and which can reduce power consumption.

4 is a configuration diagram of a semiconductor device in accordance with the second embodiment of the present invention. In the second embodiment, clock control units 211A to 2N1A and clock generation units 211B to 2N1B are provided in the clock generation units 211 to 2N1. The clock controllers 211A to 2N1A generate the control clock enable signal CCEN. The clock generators 211B to 2N1B generate the control clock CCK. In the functional blocks 1 to N, pulse clock generation circuits 218 to 2N8 are provided to generate the pulse clock PCK in synchronization with the system clock SCK.

5 is a circuit diagram of clock control units 211A to 2N1A provided in clock generation units 211 to 2N1 according to the present embodiment. The p-type MOS transistor 310 and the n-type MOS transistors 390 and 340 are connected in series, and a pulse clock PCK is supplied to the gates of the p-type MOS transistor 310 and the n-type MOS transistor 340. The select signal SLT is supplied to the gate of the n-type MOS transistor 390. An inverter 380 is connected to the node 370 between the p-type MOS transistor 310 and the n-type MOS transistor 390, and its output becomes a control clock enable signal CCEN. An inverter 360 for latching the control clock enable signal CCEN is also connected, the input of which is connected to the output of the inverter 380, and the output of which is connected to the input of the inverter 380.

6 is a circuit diagram of clock generation units 211B to 2N1B provided in clock generation units 211 to 2N1 according to the present embodiment. The system clock SCK inverted by the inverter 610 is input to the NAND gate 620 together with the control clock enable signal CCEN. The NAND gate 620 outputs a control clock CCK supplied to the dynamic circuit group.

7 is a timing chart in the present embodiment. Phase PH1 and phase PH2 are timing charts when selected, and phase PH3 and phase PH4 are timing charts when not selected.

The operation when the selection signal SLT is supplied will be described using the phase PH1 and the phase PH2 of FIG. Hereafter, it is assumed that the functional block 3 is similarly selected. In synchronization with the rising edge of the system clock SCK, the pulse clock generation circuit 238 generates a pulse clock PCK having an L level of short pulse width. The L level of the short pulse width is input to the gate of the p-type MOS transistor 310 of the clock control unit 231A (see Fig. 5). As a result, the p-type MOS transistor 310 is turned on, the node 370 is precharged, and the control clock enable signal CCEN is reset to the L level. Subsequently, the voltage is switched to the H level of the pulse clock PCK, and the n-type MOS transistors 390 and 340 are turned on by supplying the selection signal SLT having the H level. The p-type MOS transistor 310 becomes non-conductive, whereby the node 370 is discharged, and the control clock enable signal CCEN becomes H level. Thereafter, by the input of the L level of the pulse clock PCK of the phase PH2, the control clock enable signal CCEN is reset again to the L level.

The control clock enable signal CCEN is input to the NAND gate 620 of the clock generator 231B together with the inverted system clock SCK (see FIG. 6). Therefore, when the control clock enable signal CCEN is at the H level, the system clock SCK delayed by the inverter 610 and the NAND gate 620 is output as the control clock CCK.

In this way, the control clock CCK is used to control the dynamic circuit by repeating the H level and the L level when the selection signal SLT is supplied.

On the contrary, the operation when the selection signal SLT is not supplied will be described using the phase PH3 and the phase PH4 of FIG. Hereinafter, the functional block 1 will be described as an unselected functional block. By the L level of the pulse clock PCK of short pulse width, the control clock CCEN is reset to the L level. Thereafter, the pulse clock PCK is switched to the H level, but the selection signal SLT is not supplied in the phase PH3. Therefore, the n-type MOS transistor 390 does not conduct, and the node 370 is not discharged. For this reason, the control clock enable signal CCEN does not become H level but is maintained at L level.

The control clock enable signal CCEN is input to the NAND gate 620 of the clock generator 211B together with the inverted system clock SCK (see FIG. 6). Therefore, when the control clock enable signal CCEN is at the L level, the control clock CCK is maintained at the H level regardless of the state of the system clock SCK.

In this way, when the selection signal SLT is not supplied, the control clock CCK is held at the H level to be in a stopped state.

The dynamic circuit group 233 of the selected function block 3 is supplied with a control clock CCK to perform an operation of executing a predetermined function. At that time, precharge and discharge are repeatedly consumed. However, since the control clock CCK is not supplied to the dynamic circuit group 213 of the unselected functional blocks 1, no operation for executing a predetermined function is performed and power is not consumed.

In this manner, the semiconductor device according to the present embodiment selects a dynamic circuit to operate and limits the dynamic circuit for precharging and discharging, thereby reducing power consumption. Therefore, it is possible to realize a semiconductor device using a dynamic circuit capable of high speed operation and further reducing power consumption.

In this embodiment, by using the clock control unit, the control clock enable signal CCEN is reset to the L level at the beginning of each cycle in synchronization with the system clock SCK, and the selection signal SLT within each cycle. ) Becomes H level, the control clock enable signal CCEN is set to H level, the H clock level is maintained regardless of the selected signal during the cycle, and the clock generator 231B is activated to control the clock CCK. Can be generated.

The control clock enable signal CCEN is generated for one clock cycle. By generating the control clock CCK while the control clock enable signal CCEN is being supplied, the same semiconductor device can be realized from the selection signal SLT supplied only for a predetermined period of one clock cycle.

8 is a configuration diagram of a semiconductor device in accordance with the third embodiment of the present invention. In this embodiment, the power saving mode signal PSM is supplied to the clock control units 211A to 2N1A in the clock generation units 211 to 2N1. When this signal is supplied, the clock control units 211A to 2N1A function similarly to the clock control unit in the second embodiment of the present invention, and function blocks 1 to N only when the selection signal SLT is supplied. The dynamic circuit groups 213 to 2N3 within operate to consume power. On the other hand, when the power saving mode signal PSM is not supplied, the clock control sections 211A to 2N1A enable the control clock regardless of whether or not the selection signal SLT is supplied from the selection signal generation circuit 200. Output the signal CCEN.

By providing such a signal PSM, when the power saving function is to be stopped, the clock control units 211A to 2N1A can be stopped and the semiconductor device can be operated.

9 is a circuit diagram of a clock control unit in the present embodiment. The p-type MOS transistor 310 and the n-type MOS transistors 320, 390, and 340 are connected in series, and a pulse clock PCK is supplied to the gates of the p-type MOS transistor 310 and the n-type MOS transistor 340. do. The selection signal SLT is supplied to the gate of the n-type MOS transistor 390, and the power saving mode signal PSM is supplied to the gate of the n-type MOS transistor 320. The NAND gate 350 is connected to the node 370 between the p-type MOS transistor 310 and the n-type MOS transistor 320, and the power saving mode signal PSM is supplied to the other input. The output of the NAND gate 350 becomes a control clock enable signal CCEN. In addition, an inverter 360 for latching the control clock enable signal CCEN is connected, the input of which is connected to the output of the NAND gate 350, and the output of which is connected to the node 370.

When the power saving mode signal PSM is supplied, the H level is supplied to one input of the NAND gate 350, and the NAND gate 350 becomes the same as the inverter. In addition, the H level is also supplied to the gate of the n-type MOS transistor 320, the n-type MOS transistor 320 is turned on, and the clock control unit in this embodiment is the second embodiment shown in FIG. It becomes the same as a clock control part.

On the other hand, when the power saving mode signal PSM is not being supplied, the node 370 cannot be discharged because the n-type MOS transistor 320 is not conducting. In addition, one input of the NAND gate 350 is at the L level, and the control clock enable signal CCEN as the output is at the H level.

As described above, in the present embodiment, when the power saving mode signal PSM is supplied, the semiconductor device operates similarly to the second embodiment. When the power saving mode signal PSM is not supplied, the control clock enable signal CCEN is output and the control clock CCK is generated regardless of whether the selection signal SLT is supplied.

In this way, when the power saving function is to be stopped, the clock control units 211A to 2N1A are stopped to operate the semiconductor device. When the semiconductor device performs an unstable operation, by stopping the clock control unit to operate the semiconductor device, it is possible to investigate whether the problem is in the clock control unit or in a part other than the semiconductor device.

10 is a dynamic circuit system for power saving of a RAM memory system. This RAM memory system is composed of an address free decoder 100, a plurality of memory blocks (000 to 022), and an OR circuit 143. For example, the pulse block generator 180, the clock controller 110, the clock generators 111 to 114, and the memory cell group 150 are provided in the memory block 011. The clock control unit 110 has the same configuration as the clock control unit of FIG. 9. The clock generators 111 to 114 have the same configuration as that of the clock generator of FIG. 6 or control clocks C1 to C4 that are generated by adding a delay circuit to the front end of the output terminal of the clock generator of FIG. 6. ) Is to shift the timing. In addition, the memory block includes a row decoder 121, a row driver 122, a column decoder 131, a column driver 132, and an OR circuit group for data output for writing and reading data to the memory cell group 150. 141, an OR circuit 142 for selecting a column is provided. The row decoder 121, the row driver 122, the column decoder 131, the column driver 132, the OR circuit group 141, and the OR circuit 142 are all composed of dynamic circuits.

11 is a timing chart in the present embodiment. Phase PH1 and phase PH2 represent timing charts when selected, and phase PH3 and phase PH4 represent timing charts when selected.

The operation when the block selection signal SLT is supplied will be described using the phase PH1 and the phase PH2 of FIG. By the L level of the pulse clock PCK of short pulse width, the control clock enable signal CCEN is reset to the L level. Thereafter, the control clock enable signal CCEN becomes H level by switching the pulse clock PCK to the H level and supplying the block select signal SLT. And the control clock CCEN is reset to L level by input of the L level of the pulse clock PCK of phase PH2 again.

The control clock enable signal CCEN is input to the NAND gates 620 of the clock generators 111 to 114 together with the inverted system clock SCK (see FIG. 6). Therefore, when the control clock enable signal CCEN is at the H level, the system clock SCK delayed by the inverter 610 and the NAND gate 620 is output as the control clock C1. The control clocks C2 to C4 further delay the control clock C1.

On the contrary, the operation when the block selection signal SLT is not supplied will be described using the phase PH3 and the phase PH4 of FIG. The control clock enable signal CCEN is reset to the L level by the L level of the pulse clock PCK having a short pulse width. Thereafter, the pulse clock PCK is switched to the H level, but the block select signal SLT is not supplied. For this reason, the control clock enable signal CCEN does not become H level but is maintained at L level.

The control clock enable signal CCEN is input to the NAND gates 620 of the clock generators 111 to 114 together with the inverted system clock SCK (see FIG. 6). Therefore, when the control clock enable signal CCEN is at the L level, the control clock C1 is maintained at the H level regardless of the state of the system clock SCK. Since the control clocks C2 to C4 delay the control clock C1 further, they are maintained at the H level.

In this way, the control clocks C1 to C4 are maintained at the H level when the block selection signal SLT is not supplied, and the control clocks C1 to C4 are stopped.

The dynamic circuit group of the selected memory block is supplied with the control clocks C1 to C4 to perform an operation of executing a predetermined function. At that time, precharge and discharge are repeatedly consumed. However, since the control clocks C1 to C4 are not supplied to the dynamic circuit group in the unselected memory block, no operation for executing a predetermined function is performed and power is not consumed.

12 is a circuit diagram of the row decoder 121 and the row driver 122. FIG. 13 is a diagram showing a low-definition front end circuit. In the selected memory block, the row decoder 121 operates in synchronization with the control clock C1 generated by the clock generator 111 and selects the word line WL of the memory cell to be read. A predecoder composed of an inverter and an AND circuit shown in FIG. 13 generates a predecode signal with respect to an address signal of two bits of the eight-bit address signal A. FIG. In Fig. 13, predecode signals PD76 [3] to PD76 [0] are generated from address signals A [7] and A [6], and address signals A [5] and A [4], A [3] and Similarly, the predecode signals PD54 [3] to PD54 [0], PD32 [3] to PD32 [0], and PD10 [3] to PD10 [0] from A [2], A [1] and A [0]. Is generated. These predecode signals are input to the n-type MOS transistors 810 to 813 of each row decoder. When the input signals are all at the H level, the word line WL connected to the row decoder is selected. 12, the node 850 is precharged by the input of the L level of the control clock C1, and the output z of the row decoder 121 is reset to the L level. After that, when all of the n-type MOS transistors 810 to 813 of the row decoder 121 receive the H level signal, the node 850 is discharged. As a result, the output z of the row decoder 121 becomes H level. On the other hand, the row driver 122 is reset by the input of the L level pulse of the control clock C2 delayed from the control clock C1, and then in response to the input of the output z H level of the row decoder 121. The n-type MOS transistor 920 conducts, and the node 950 is discharged. As a result, the word line WL is driven to the H level.

At this time, the control clocks C1 and C2 are not supplied to the row decoder 121 and the row driver 122 in the unselected memory block. Therefore, the row decoder 121 and the row driver 122 of the dynamic circuit do not precharge and suppress power consumption.

The column decoder 131 and the column driver 132 also have the same configuration as in FIG. 12. The column decoder 131 operates in synchronization with the control clock C1 generated by the clock generator 111 and selects a column of a memory cell to be read. The column driver 132 operates in synchronization with the control clock C2 generated by the clock generator 112, and supplies the column select signal CSL to the column selected by the column decoder 131.

At this time, the control clocks C1 and C2 are not supplied to the column decoder 131 and the column driver 132 in the unselected memory block. Therefore, the column decoder 131 and the column driver 132 do not precharge and suppress power consumption.

FIG. 14 is a diagram showing an output unit configuration of the memory system according to the fourth embodiment. In FIG. 14, one column CL1 of the memory cell group 150, an OR circuit group 141, and an OR circuit 142 corresponding to the column CL1 are shown.

Here, an explanation will be given taking an example of an SRAM of one RW type which writes or reads once per cycle. However, it is also adapted to multiport (SRAM) to register files such as 2 RW for writing and reading twice in one cycle, 2R2W for writing and reading twice in one cycle, and also to memory systems such as DRAM and FRAM. It is possible. The column CL1 of the memory cell group includes the memory cells MC00 to MC15 having the inverters connected to each other at the intersections of the bit line pairs BLx and BLy and the word lines WL00 to WL15. The memory cell MC00 includes p-type transistors p1 and p2, n-type transistors n3 and n4 constituting an inverter, and n-type gate transistors n5 and n6 opened by the word line WL00. Other memory cells have the same configuration. The bit line pairs BLx and BLy are divided into memory cell sets SET0 and SET1 consisting of eight memory cells MC00 to MC07 and MC08 to MC15. One bit line BLy is connected to the OR circuit 721 of the OR circuit group 141.

This OR circuit 721 has a reset transistor p21 controlled by the control clock C2, an inverter 731, and a latch transistor p22, like the dynamic circuit described above, and is connected to it. Together with transistors n4, n6, n14, n16 constitute a dynamic OR circuit. That is, the OR circuit 721 constitutes an OR circuit together with the cell transistors of the memory cell sets SET0 and SET1, and the OR circuits 722 and 72N respectively OR together with the cell transistors of two memory cell sets not shown. Configure the circuit.

In this OR circuit 721, the node N21 is reset to the H level in response to the L level pulse of the control clock C2. The node N21 becomes L level or is maintained at H level according to the state of the memory cell corresponding to the selected word line. Here, the read operation will be described as an example. In this case, if the word line WL00 is temporarily selected and the transistor n6 conducts, the transistor n4 of the memory cell MC00 is connected to the OR circuit 721, and the node in the memory cell MC00 is connected. It becomes an OR circuit which takes (N1) as an input. At that time, since all other word lines are at the L level, the gate transistor does not conduct, and there is no influence on the discharge operation of the node N21 of the OR circuit 721. When the node N1 is temporarily set to the L level, the transistor n4 is in a non-conductive state, so the node N21 in the OR circuit 721 maintains the H level. On the other hand, when the node N1 is at the H level, the transistor n4 is in a conductive state, the node N21 of the OR circuit 721 is at the L level, and the OR circuit 721 is at the H level output ( z1) is output. Further, the OR circuits 722 and 72N connected to the bit lines of the same column CL1 are in the state where the corresponding word lines are at the L level, and therefore, these outputs z2 to zN are all in the L level state.

As described above, the OR circuit group 141 forms an OR circuit together with the transistors of the memory cell, and outputs the state of the selected memory cell to the outputs z1 to zN at high speed.

Next, in addition to the control clock C2, the OR circuit 142 is supplied with the outputs z1 to zN and the column select signal CSL from the OR circuit group 141 in the previous stage. The column select signal CSL1 is supplied to the transistors n31, n33 and n35, and the outputs z1 to zN of the OR circuit group 141 at the front end are supplied to the transistors n32, n34 and n36. Similarly, the OR circuit 142 has transistors n41 to n46 to which the same signal from another column is supplied. The transistor group supplied with the H level column select signal CSL operates as an OR circuit. The OR circuit 142 is also reset by the L level pulse of the control clock C2, and the node 31 is controlled in accordance with the output of the OR circuit group in the previous stage.

If the column CL1 is temporarily selected, the column select signal CSL1 becomes H level, the transistors n31, n33, n35 become conductive, and the column select signal CSL2 becomes L level, The transistors n41, n43, n45 are in a non-conductive state. As a result, the OR circuit 142 constitutes an OR circuit which takes in the outputs z1 to zN from the OR circuit group 141. And when any one of the outputs z1-zN is H level, the node N31 will become L level, and the output z10 will be H level. As described above, according to the state of the memory cell corresponding to the selected word line, any one of the outputs z1 to zN becomes H level or L level, and the outputs z1 to zN corresponding to the unselected word lines are Since both are at the L level, the OR circuit 142 outputs as its output z10 the states of the memory cells corresponding to the selected word line and the selected column.

In this manner, the OR circuit 142 has a function of obtaining an output logic OR of the OR circuit group 141 in the previous stage in addition to the column selection function. An OR circuit 143 similar to the OR circuit 142 is provided at the rear end of the OR circuit 142, and the final output data z is output therefrom. The OR circuit 143 of the last stage obtains a logical OR of output data of the plurality of memory blocks, and outputs data of selected memory cells in the selected memory block.

In addition, since the OR circuit group 141 and the OR circuit 142 are constituted by dynamic circuits, high-speed operation is possible. The OR circuit group 141 and the OR circuit 142 in the selected memory block operate in synchronization with the control clock C2, repeat precharge and discharge, and consume power. However, in the unselected memory block, the control clock C2 is not supplied to the OR circuit group 141 and the OR circuit 142. Therefore, the OR circuit group 141 and the OR circuit 142 do not precharge and suppress power consumption.

In this manner, the RAM memory system according to the present embodiment selects a memory block to be read or written, and operates only to the dynamic circuit therein to limit the dynamic circuit for precharging and discharging, thereby reducing power consumption. Can be. Therefore, it is possible to provide a semiconductor device which uses a dynamic circuit capable of high speed operation and which can reduce power consumption.

FIG. 15 is a chart showing improvement in cycle time, access time, and power consumption of the memory system of the fourth embodiment. This table shows the cycle time, access time and power consumption corresponding to memory system A composed of static circuits and memory systems B and C composed of dynamic circuits described above. Memory system B is when the power saving mode signal (PSM) disables the power saving function of the dynamic circuit by the L level, and memory system C is the power saving mode signal (PSM) by the H level. Is enabled.

When the cycle time, access time and power consumption of the memory system A by the static circuit are set to "1", the cycle time and access time of the memory systems B and C are all improved to "0.74" and "0.80". On the other hand, the power consumption increases to "1.37" because the memory system B operates all the dynamic circuits, but the power consumption is greatly improved to "0.64" because the memory system C only partially operates the dynamic circuits. That is, in the memory system C corresponding to the present embodiment, both the operation speed and the power consumption are improved.

[Effects of the Invention]

The semiconductor device of the present invention can suppress the power consumption of the semiconductor device using the dynamic circuit by selecting a dynamic circuit for operating at a certain clock cycle and defining a dynamic circuit for precharging and discharging.

According to the present invention, power consumption of a semiconductor device using a dynamic circuit can be suppressed. As a result, a dynamic circuit is applied to the semiconductor device realized by the static circuit, thereby enabling high speed. In addition, in a semiconductor device to which a dynamic circuit has already been applied, there is an advantage that it is possible to avoid an increase in the capacity of a battery to be mounted.

Claims (6)

A selection signal generation circuit for supplying a selection signal to a plurality of functional blocks and a functional block to be operated among the plurality of functional blocks; The plurality of functional blocks, A clock for supplying the selection signal and a system clock, generating a control clock based on the system clock when the selection signal is being supplied, and stopping generation of the control clock when the selection signal is not being supplied; Generating unit, Between a power supply and ground, a p-type transistor in which the control clock is supplied to the gate and an n-type transistor in which an input signal is supplied to the gate are provided in series, and a node between the p-type transistor and the n-type transistor is controlled. A dynamic circuit precharged in response to the supply of the clock and discharged in accordance with the input signal, The clock generation unit, The selection signal and the system clock are supplied, start generation of a control clock enable signal in response to the supply of the selection signal, and end generation of the control clock enable signal in response to the end of one cycle of the system clock. A clock control unit While the control clock enable signal and the system clock are supplied and the control clock enable signal is being supplied, the control clock based on the system clock is generated, while the control clock enable signal is not being supplied. And a clock generator for stopping generation of the control clock. delete The method of claim 1, The clock generation unit, When the power saving mode is being supplied, generation of the control clock enable signal is started in response to the supply of the selection signal, and generation of the control clock enable signal is terminated at the end of one cycle of the system clock. And the clock control unit which generates the control clock enable signal regardless of the input of the selection signal when the power saving mode is not supplied. A plurality of memory blocks and an address-free decoder for supplying a block selection signal to a memory block for reading or writing among the plurality of memory blocks; The plurality of memory blocks, The control signal is generated based on the system clock when the block selection signal and the system clock are supplied, and when the block selection signal is not supplied. A clock generation unit that stops A memory cell group that holds data; A row decoder for selecting word lines of data of the memory cells; A row driver for driving the word line selected by the row decoder; A column decoder for selecting a column of the memory cell; A column driver for supplying a column selection signal (CSL) to the column selected by the column decoder; An output circuit group for inputting the bit line of the memory cell group and outputting read data; The row decoder, the row driver, the column decoder, the column driver, and the output circuit group include a p-type transistor to which the control clock is supplied to a gate between a power supply and ground, and an n-type to which an input signal is supplied to the gate. And a transistor is provided in series, and a node between the p-type transistor and the n-type transistor is configured as a dynamic circuit which is precharged in response to the supply of the control clock and discharged according to the input signal. Memory. The method of claim 4, wherein The clock generation unit, The block select signal and the system clock are supplied and start generation of a control clock enable signal in response to the supply of the block select signal, and in response to the end of one cycle of the system clock. A clock control unit which terminates generation; While the control clock enable signal and the system clock are supplied and the control clock enable signal is being supplied, the control clock based on the system clock is generated, while the control clock enable signal is not being supplied. And a clock generator for stopping the generation of the control clock. The method of claim 5, The clock generation unit, When the power saving mode signal is being supplied, generation of the control clock enable signal is initiated in response to the supply of the block selection signal, and generation of the control clock enable signal upon completion of one cycle of the system clock. And the clock control unit for generating the control clock enable signal regardless of the input of the block selection signal when the power saving mode signal is not supplied.

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