KR20020034219A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided, which reduces current consumption, by preventing a swing of a data bus line and a bit line. CONSTITUTION: The semiconductor memory device has a power supply voltage of a wide bandwidth. A read and write operation at a low power supply voltage is performed by generating an equalize signal by a signal detecting an input of an address and data and then generating a signal activating a word line by the equalize signal. A read operation at a high voltage is performed according as whether a write enable signal is inputted after a fixed time, after an address or a chip enable signal is inputted. A write operation at the high power supply voltage is performed after data is inputted from a data input buffer, after a delay for a constant time after a write enable signal is inputted.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and in particular, by delaying a write time after a data input time, thereby preventing the data bus lines and bit lines from swinging before the write data is input, thereby preventing unnecessary current. A semiconductor memory device with reduced consumption.

1 is a block diagram illustrating a configuration of a general semiconductor memory device.

As shown, an address buffer 10 for inputting an address, an address transition detection circuit 20 for inputting an output signal of the address buffer 10 to output an address transition detection signal ATD; The pulse selector buffer 50 that receives the chip selector signal / CS, the address shift detection signal ATD, and the output signal of the chip selector buffer 50 as inputs, and then a pulse equalization signal PEQ. A pulse equalization signal generation circuit 30 for generating a signal, a data buffer 60 for inputting a data signal, and an output signal of the data buffer 60 for inputting a data transition detection signal DTD. An output data transition detection circuit 70, an upper buffer 80 for inputting an upper signal / UB, a write enable buffer 90 for inputting a write enable signal / WE, and The data transition detection signal DTD and the upper buffer A data equalization signal generation circuit 100 for generating a data equalization signal DEQ by inputting the output signal PUBB of 80 and the output signal PWEB of the write enable buffer 90 as input signals, and the pulses; A pulse word line signal generation circuit 40 is shown for inputting an equalizing signal PEQ and a data equalizing signal DEQ to generate a pulse word line signal PWLT.

First, when an address add is input, an address transition (ATD) signal is generated by the address transition detection circuit 20 by the output signal of the address buffer 10, and accordingly an address transition (ATD) signal is input. The pulse equalization signal generation circuit 30 generates a pulse equalization (PEQ) signal. In addition, the pulse word line signal generation circuit 40 generates a pulse word line signal PWLT by using the pulse equalization signal PEQ to perform a read operation. The same applies to the case where the chip enable signal / CS is input and the pulse chip selector signal PCSB is input to generate the pulse equalization signal PEQ.

After this, when the write enable signal / WE is input, the pulse write enable signal PWEB is generated by the write enable buffer 90, and the pulse write enable signal PWEB and the data transition are detected. A data equalization signal DEQ is generated by the data equalization signal generation circuit 100 that receives the signal DTD. Accordingly, a pulse wordline signal generation circuit that receives the data equalization signal DEQ as an input. In operation 40, the pulse word line signal PWLT is generated to perform a write operation. When the data input buffer 60 is input again, the data transition detection signal DTD is generated and received by the data equalization signal generation circuit 100 to generate the data equalization signal DEQ and the pulse word line signal PWLT. ) To write to other data.

In the read operation, a large portion of the current consumes a large amount of current flowing after the word line is turned on by the pulse word line signal PWLT. In the write operation, the data bus line and the bit line are charged to write data to the cell. And the current consumed for discharging is mainly occupied.

Using the data shown in the general SPEC, the worst timing for writing the data is shown in Figs. 3A and 3B. In this case, it can be seen that when the data is actually inputted and the unnecessary operation is performed before the writing, the current is wasted. In FIG. 3B, the unnecessary read operation is 10 ns and the write operation is 20 ms. In this case, the low voltage is excluded because the current consumption is relatively small.

FIG. 2A illustrates a pulse equalization signal generation circuit 30 according to the prior art, in which NAND gates NAND1, NAND2,..., Which respectively receive an address transition detection signal ATD, and the NAND gate ( NOR gates (NOR1, ...) for inputting the output signals of NAND1 and NAND2, ...), NAND gates (NAND3) for inputting the output signals of the NOR gates (NOR1, ...), respectively; And serially connected inverters INV1 and INV2 for inputting the output signal PEQ_N of the NAND gate NAND3 to output the pulse equalization signal PEQ.

FIG. 2B illustrates a data equalization signal generation circuit 100 according to the prior art, wherein the NAND gates NAND4, NAND5,..., Which respectively accept the data transition detection signal DTD, and the NAND gate ( NOR gates (NOR2, ...) for inputting the output signals of NAND4, NAND5, ...), and NAND gates (NAND6) for inputting the output signals of the NOR gates (NOR2, ...). And inverters INV3 and INV4 connected in series to input the output signal DEQ_N of the NAND gate NAND6 to output the data equalization signal DEQ.

The conventional pulse equalization signal generation circuit 30 and the data equalization signal generation circuit 100 generate an address transition signal ADT when the address is input regardless of a low voltage and a high voltage, and combine the pulse equalization signal ( PEQ). When the data is input, the data transition detection signal DTD is input and combined to generate a data equalization signal DEQ. This immediately generates a pulse word line signal PWLT to perform read and write operations. Therefore, at low voltage, current consumption is relatively low, so it is not a big problem. However, at high voltage, the current consumption is increased before actual operation. Swing operation of the bit line in Figure 3b).

That is, at high voltage, the data bus line and the bit line are swinged before data to be actually written onto the data bus line and the bit line causes unnecessary current consumption.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a read operation at a high power voltage in an address memory or chip enable (/ CS) signal in a semiconductor memory device having a wide bandwidth. After is input, it operates according to whether or not the light enable (/ WE) signal is input after a certain time has elapsed, and in the light operation, a delay is applied for a predetermined time after the light enable (/ WE) signal is input. The present invention provides a semiconductor memory device which reduces the current consumption by controlling to operate after a time when data is input from the data input buffer while waiting for a given time.

In order to achieve the above object, the semiconductor memory device of the present invention,

A semiconductor memory device having a wide bandwidth power supply voltage,

The read and write operation at low power supply voltage

Generates an equalization signal by a signal that detects an input of an address and data, and generates and operates a signal that activates a word line by this signal,

The read operation at high power voltage is

After the address or the chip enable signal is input, after a predetermined time has elapsed depending on whether or not the write enable signal is input,

The write operation at high power voltage,

After the write enable signal is input, a delay is given for a predetermined time to wait, and then the control is performed to operate after a time when data is input from the data input buffer.

Another semiconductor memory device of the present invention for achieving the above object,

A logic calculator which inputs an address transition detection signal to generate a first pulse equalization signal;

A first signal delay unit configured to input the first pulse equalized signal and generate a second pulse equalized signal delayed for a predetermined time;

A first switching unit for switching the second pulse equalization signal to a pulse equalization signal when the operation voltage of the semiconductor memory device is a low power supply voltage;

A second signal delay unit configured to input the first pulse equalization signal to generate a pulse signal delayed for a predetermined time;

A second switching unit transferring the output signal of the second signal delay unit to the next stage when a write enable signal is not input;

And an equalization signal generating means comprising a third switching unit for switching the output signal of the second switching unit to a pulse equalizing signal when the operating voltage of the semiconductor memory device is a high power voltage.

1 is a block diagram of a general semiconductor memory device

Figure 2a is a circuit diagram of a pulse equalization signal generation according to the prior art

2b is a circuit diagram of a data equalization signal generation according to the prior art

3A is a simulation result for each signal at a conventional low power supply voltage

Figure 3b is a simulation result for each signal at a conventional high power supply voltage

4A is a pulse equalization signal generation circuit diagram according to the present invention.

4b is a data equalization signal generation circuit diagram according to the present invention;

FIG. 5A is an operational waveform diagram of each signal shown in FIG. 4A

FIG. 5B is an operational waveform diagram of each signal shown in FIG. 4B

Figure 6a is a simulation result for each signal at a low power supply voltage according to the present invention

Figure 6b is a simulation result for each signal at a high power supply voltage according to the present invention

Explanation of symbols on the main parts of the drawings

10: address buffer 20: address transition detection circuit

30: pulse equalization signal generating circuit

40: pulse word line signal generating circuit

50: chip selector buffer 60; Data buffer

70: data transition detection circuit 80: upper buffer

90: light enable buffer

100: data equalization signal generating circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

4A shows a pulse equalization signal EQ generation circuit according to the invention for controlling the input of a read signal.

As shown, a logic operation unit 140 is configured to input an address transition detection signal ADT to generate a first pulse equalization signal PEQ_N, and a first delay time by inputting the first pulse equalization signal PEQ_N. The signal VREF detecting the operating voltage of the semiconductor memory device by inputting the first signal delay unit 150 and the output signal of the first signal delay unit 150 that generate the signal to the node Nd1. By the first switching unit (N1 and P1) for switching the output signal of the first signal delay unit 150 to the pulse equalization signal PEQ when the operating voltage is a low power supply voltage, and the first pulse equalization Input the signal PEQ_N to generate a pulse signal PEQ_C delayed by a predetermined time of the signal, and the output signal PEQ_C of the second signal delay unit 110; To the control signal DEQ_B which detects whether or not the enable signal / WE is present. By the second switching unit 120 for transmitting the output signal (PEQ_C) of the second signal delay unit 110 to the next stage and the detected signal (VREF) of the semiconductor memory device the operating voltage is high power supply voltage In this case, the output signal PEQ_L of the second switching unit 120 is configured as a third switching unit N2 and P2 for switching the pulse equalizing signal PEQ.

The logic operation unit 140 may include NAND gates NAND7, NAND8,... Which input address transition signals ADT, and NOR gates NOR3, which input two output signals of the NAND gate, respectively. ... and NAND gates (NAND9, ...) that input three output signals of the NOR gates (NOR3, ...).

In addition, the first signal delay unit 150 includes two inverters connected in series.

The first switching units N1 and P1 are transfer gates composed of PMOS and NMOS transistors, and are switched by a reference voltage VREF detecting whether an operating voltage of the semiconductor memory device is a high voltage or a low voltage.

The second signal delay unit 110 may invert the inverter INV5 for inverting the first pulse equalization signal and a first delay 112 for delaying a signal for inverting the output signal of the inverter INV5 for a predetermined time. ), The NAND gate NAND11 that inputs the output signal of the inverter INV5 and the output signal of the first delay 112, and the inverted signal of the output signal of the NAND gate NAND11 are delayed for a predetermined time. A second delay 114 to be output, an inverter INV8 for inverting the output signal of the second delay 114, an output signal of the NAND gate NAND11 and an output signal of the inverter INV8 as inputs Is composed of a NOR gate NOR4.

The second switching unit 120 includes an inverter INV3 for inverting a signal DEQ_B for detecting whether a write enable signal is input, an output signal of the inverter INV3, and an output of the NOR gate NOR4. And an inverter INV4 for inverting and outputting the output signal of the NAND gate NAND10.

The third switching units N2 and P2 are transfer gates composed of PMOS and NMOS transistors, and are switched by a reference voltage VREF that detects whether an operating voltage of the semiconductor memory device is a high voltage or a low voltage. Here, the reference voltage Vref may be designed to have a different magnitude of the reference voltage according to the magnitude of the power supply voltage. The equalizing signal generating circuit of the present invention will be described as an example in which the value of the reference voltage Vref is set to 'high' at the low power supply voltage low Vcc.

The operation of the pulse equalization signal EQ generation circuit having the above configuration will be described with reference to the operation timing diagram shown in FIG.

First, the operation at low power supply voltage (low Vcc) will be described.

When the address transition signal ATD is input, the logic operation unit 140 generates a first pulse equalization signal PEQ_N. In this case, since the reference voltage Vref is a low power supply voltage, the reference voltage Vref is input in a 'high' state. The reference voltage Vref turns on the transfer gates N1 and P1 composed of NMOS and PMOS transistors, and turns off the transfer gates N2 and P2 to pulse-equalize the first pulse equalization signal PEQ_N. Make signal PEQ. This is the same as the operation in the conventional pulse equalization circuit.

Meanwhile, in the high power supply state, since the reference voltage Vref has a low state, the transfer gates N1 and P1 are turned off, and the transfer gates N2 and P2 are turned on to turn on the second pulse equalization signal PEQ_L. Will generate a pulse equalization signal (PEQ).

Looking at the generation process of the second pulse equalization signal PEQ_L, the first pulse equalization signal PEQ_N generated through the combination of the address transition circuit ATD is the inverter INV5 of the second signal delay unit 110. And generates an inverted signal PEQ_A. The signal PEQ_A is again inverted through the inverter INV6 and generates a signal D1 having a delay equal to the first delay 112 and input to the NAND gate NAND11. The combination of the output signal PEQ_A of the inverter INV5 and the output signal D1 of the first delay 112 generates a PEQ_B signal whose rear end is extended by the first delay 112 and cut off by the PEQ pulse width. .

The reason why the pulse width of the output signal D1 of the first delay 112 is different from the width of the original PEQ_A signal is that the rear end has more delay if the size of the PMOS and NMOS transistors in the inverter INV6 are different. can do.

The PEQ_B signal is inverted through the inverter INV7, has a delay equal to the second delay 114, and then inverted again and combined with the generated signal D2 to cut the front end of the original PEQ_B signal by the second delay 114. Generates the PEQ_C signal. That is, the circuit on the side of the first delay 112 is a circuit for extending the rear end of the first pulse equalization signal PEQ_N, and the circuit on the side of the second delay 114 is the circuit on the side of the first delay 112. This circuit cuts the leading edge of the increased signal.

The second switch unit 120 determines whether or not to use the PEQ_C signal according to whether the write enable signal / WE is input.

First, if the write enable signal / WE is not inputted, the DEQ_B signal goes low (FIG. 5). The PEQ_C signal passes through the NAND gate NAND10 and generates PEQ_L through the inverter INV4. Allows action to be made.

When the write enable signal / WE is input, the DEQ_B signal is maintained in a 'high' state for a predetermined period so that the read operation is not performed by not passing the PEQ_C signal. In addition, since the reference voltage VREF is 'low', the transfer gates N2 and P2 are turned on so that the second pulse equalization signal PEQ_L generates the pulse equalization signal PEQ.

4B is a circuit diagram illustrating a data equalization signal DEQ generation circuit that controls the input of the write signal.

When the write enable signal (/ WE) is input at the 'high' voltage, the circuit performs a write operation after a delay for a predetermined time, and performs a write operation immediately when data is input, thereby unnecessary operation according to the difference. Do not make this happen.

At low voltage, since the reference voltage VREF is 'high', the transfer gates P3 and N3 are turned off so that the signal delay unit 210 does not operate, and the transfer gates P4 and N4 of the operation voltage switching unit 220 are operated. ) And turn off the transfer gates (P5, N5) to turn off the normal PWEB signal (signal generated at / WE enable), PUBB / PLBB signal (signal generated at / UB, / LB enable). The combination signal DEQ_N generates the signal DEQ_H. In the data equalizing signal DEQ output unit 230, the reference voltage VREF inverted by the inverter INV16 is used to generate the NAND gate NAND13. By disabling and enabling the NAND gate NAND14, the combined signal DEQ_L of the normal data transition detection DTD signal generates the data equalization signal DEQ so that normal write operation is performed.

At high voltages, the reference voltage (Vref) signal is 'low', so the transfer gates P3 and N3 are turned on to pass through the combined signal DEQ_N of the input signal PWEB / PUBB / PLBB to invert through the inverter INV11. Generates the generated signal DEQ_A. The signal DEQ_A is again combined through the inverters INV12 and INV13 to generate a signal D2 whose rear end is extended by the first delay 212 from the original signal. The signal D2 is again inverted through the inverter INV14 to generate a signal D3 delayed by the second delay 214, which is combined with the signal DEQ_A to form a second signal. Generate the signal DEQ_B which is further extended by the delay 214. Therefore, the signal DEQ_B is a signal in which the rear end of the signal DEQ_A is extended by the first delay 212 + the second delay 214 (see also the waveform of FIG. 5B). The reason for this separation is to prevent the malfunction because the original waveform may disappear if the delay is too long.

The generated signal DEQ_B goes to the pulse equalization signal EQ generation circuit to prevent the read operation, and is inverted through the inverter INV15 and has a signal D4 having a delay equal to the third delay 216. Create In this case, the generated signal D4 is combined with the signal DEQ_A and the NAND gate NAND17 to generate the signal DEQ_C. The signal DEQ_C generated as described above is a signal having a pulse width equal to the first delay 212 + the second delay 214 and the third delay 216.

The signal DEQ_C generates a signal equalization signal DEQ by generating a signal DEQ_H through the transfer gates P5 and N5.

Here, the role of the data equalization signal DEQ output unit 230 will be described.

In general, the data input buffer is controlled by the control signals / WE, / LB, / UB. Therefore, even when no data is actually input, a data transition detection (DTD) signal is generated by the control signal when a low signal is applied to the data input buffer. The data equalization signal (DEQ) output unit may serve to separate the data transition detection (DTD) signal generated in this way and the data transition detection (DTD) signal generated by actually applying a signal to the data input buffer. 230).

The data transition detection signal DTD generated by the control signals PWEB, PUBB, and PLBB does not pass by the signal DEQ_B, but is generated by the signal DEQ_H generated by the signal delay unit 210. Only outputs the data equalization signal DEQ. In addition, since the signal DEQ_B is not generated by the control signal when the normal data is input, the data equalization signal DEQ is generated by passing the combination of the data transition detection DTD signals (see FIG. 6B).

As described above, the semiconductor memory device according to the present invention delays the time when it is actually written after the time at which data is input, thereby preventing unnecessary operation before it. Thus, it is helpful to design devices of low power operation. Although the current simulation is not performed, the signal PWLT is enabled to reduce the amount of current flowing in the cell while the word line is turned on. The swing of data bus lines and bit lines can be prevented, thus reducing current consumption.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (10)

A semiconductor memory device having a wide bandwidth power supply voltage, The read and write operation at low power supply voltage Generates an equalization signal by a signal that detects an input of an address and data, and generates and operates a signal that activates a word line by this signal, The read operation at high power voltage is After the address or the chip enable signal is input, after a predetermined time has elapsed depending on whether or not the write enable signal is input, The write operation at high power voltage, And a delay for a predetermined time after the write enable signal is input, to wait for a predetermined time, and to operate after the time at which the data is input from the data input buffer. In a semiconductor memory device, A logic calculating section for inputting an address transition detection signal to generate a first pulse equalization signal; A first signal delay unit configured to input the first pulse equalized signal and generate a second pulse equalized signal delayed for a predetermined time; A first switching unit for switching the second pulse equalization signal to a pulse equalization signal when the operating voltage of the semiconductor memory device is a low power supply voltage; A second signal delay unit configured to input the first pulse equalization signal to generate a pulse signal delayed for a predetermined time; A second switching unit transferring the output signal of the second signal delay unit to the next stage when a write enable signal is not input; And an equalizing signal generating means comprising a third switching unit for switching the output signal of the second switching unit to a pulse equalizing signal when the operating voltage of the semiconductor memory device is a high power voltage. The method of claim 2, wherein the logical operation unit, NAND gates for inputting address transition signals, respectively; NOR gates which input two output signals of the NAND gate; And NAND gates configured to input three output signals of the NOR gate. The method of claim 2, And the first signal delay unit comprises two inverters connected in series. The method of claim 2, And the first switching unit is a transfer gate composed of a PMOS and an NMOS transistor. The method of claim 5, And the transfer gate is controlled by a reference voltage. The method of claim 2, wherein the second signal delay unit, An inverter INV5 for inverting the first pulse equalization signal; A first delay 112 for delaying a signal obtained by inverting the output signal of the inverter INV5 for a predetermined time; A NAND gate NAND11 that receives an output signal of the inverter INV5 and an output signal of the first delay 112; Two inverters INV7 and INV8 and a second delay 114 for delaying an inverted signal of the output signal of the NAND gate NAND11 again after a predetermined time delay, and And a NOR gate (NOR4) for inputting an output signal of the NAND gate (NAND11) and an output signal of the inverter (INV8). The method of claim 7, wherein the second switching unit, An inverter INV3 for inverting the signal DEQ_B for detecting whether the write enable signal is input, and A NAND gate NAND10 for inputting an output signal of the inverter INV3 and an output signal of the NOR gate NOR4; And an inverter (INV4) for inverting and outputting the output signal of the NAND gate (NAND10). The method of claim 8, And the third switching unit is a transfer gate consisting of a PMOS and an NMOS transistor. The method of claim 9, And the transfer gate is controlled by a reference voltage.