JP2006004463A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein reduced power consumption can be realized and high speed of the writing operation can be realized by suppressing an excess timing margin in writing operation with a saved area and suppressing charge and discharge currents of a bit line pair during writing operation to the minimum. <P>SOLUTION: The semiconductor storage device is provided with a dummy wordline DWL and a timing adjusting circuit 5 having delay characteristics nearly equal to usual writing delay characteristics. The timing adjusting circuit 5 is constituted of a dummy cell 6 driven by the dummy wordline DWL and a detection circuit 7 detecting output of the dummy cell 6. Writing operation can be completed based on a detecting signal outputted by detection of the usual writing delay and the excess timing margin in the writing operation can be suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to generation of write and read timings for a semiconductor memory device.

In a semiconductor memory device such as a static random access memory (hereinafter referred to as “SRAM”), a dummy cell is arranged to control the operation timing of data reading / writing, and the operation timing is generated by the operation of the dummy cell. It may be equipped with a function to make it. At this time, in order to control a series of operation end timings in reading / writing, a technique for generating end timings of writing / reading operations based on the output of a dummy memory cell is disclosed (for example, see Patent Document 1). ). In Patent Document 1, dummy memory cells are connected to the same dummy bit line for each word line, and the read delay of the dummy memory cells is detected by an output determiner, whereby the end timing of each read / write operation is detected. Is generated.
JP-A-9-128958 (FIG. 1)

  Usually, in a semiconductor memory device, the time required for the write operation is shorter than the read operation.

  In the configuration in which the write end timing is generated based on the read delay of the dummy cells as in the semiconductor memory device shown in FIG. 1 of Patent Document 1, the write operation includes an excessive timing margin. Therefore, the time required for the write operation increases, which hinders speeding up.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to reduce an excessive timing margin in a write operation and reduce a charge / discharge current of a bit line pair during the write operation with an area-saving configuration. It is to provide a semiconductor memory device capable of realizing low power consumption and high speed writing operation by minimizing the power consumption.

  In order to solve the above problems, a semiconductor memory device of the present invention has the following configuration.

  That is, a semiconductor memory device of the present invention includes a memory cell array including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit line pairs; A row decoder that activates one of a plurality of word lines, a dummy word line that is activated in synchronization with the activated word line, a plurality of dummy memory cells that are connected to the dummy word line, and a dummy word line A dummy cell driven by activation and a write detection circuit that receives the output of the dummy cell are provided, and a write end timing is generated based on an output signal of the write detection circuit.

  In the above configuration, the activated word line and dummy word line are deactivated based on the write end timing.

  In the above configuration, the dummy word line is activated only during the write operation.

  In the above configuration, the dummy cell includes a transistor whose gate is connected to the dummy word line, whose source is grounded, and whose drain is the output.

  In the above configuration, the driving capability of the transistors constituting the dummy cell is equal to the writing driving capability for the memory cell.

  In the above configuration, the detection level of the write detection circuit is equal to the write level of the memory cell.

  In the above configuration, the load on the output signal line of the dummy cell is equivalent to the load on the bit line.

  In the above configuration, the dummy cell is arranged between the row decoder and the memory cell array.

  In the above configuration, a plurality of dummy cells and write detection circuits are arranged, and a means for generating the latest write end timing based on the output results of the plurality of write detection circuits is provided. The word activated by the write end timing The line and the dummy word line are deactivated.

Another semiconductor memory device of the present invention includes a memory cell array including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit line pairs, A row decoder that activates one of the plurality of word lines; a first dummy word line that is activated in synchronization with the activated word line; and a first plurality of lines connected to the first dummy word line A dummy memory cell; a first dummy cell driven by a first dummy word line; a write detection circuit that receives the output of the first dummy cell; and a first activation activated in synchronization with the activated word line. 2 dummy word lines, a second plurality of dummy memory cells connected to the second dummy word line, a second dummy cell driven by the second dummy word line, and an output of the second dummy cell To Includes a look out detection circuit,
At the time of writing, the write end timing is generated based on the output signal of the write detection circuit,
At the time of reading, the read end timing is generated based on the output signal of the read detection circuit.

Another semiconductor memory device of the present invention includes a memory cell array including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit line pairs, A row decoder that activates one of a plurality of word lines, a dummy word line that is activated in synchronization with the activated word line, a plurality of dummy memory cells that are connected to the dummy word line, and a dummy word line The first dummy cell to be driven, the write detection circuit that receives the output of the first dummy cell, the second dummy cell that is driven by the dummy word line, and the read detection circuit that receives the output of the second dummy cell And
At the time of writing, the write end timing is generated based on the output signal of the write detection circuit,
At the time of reading, the read end timing is generated based on the output signal of the read detection circuit.

  In the above configuration, the output signal line of the first dummy cell and the output signal line of the second dummy cell have the same configuration as the bit line pair.

  In the above configuration, the load of the output signal line of the first dummy cell and the output signal line of the second dummy cell is equivalent to the load of the bit line and the inverted bit line of the bit line pair.

  According to the semiconductor memory device of the present invention, the dummy word line, the dummy cell, and the write detection circuit can detect a delay substantially equal to the normal write delay, so that the write end timing based on the normal write delay can be generated. Thus, the writing operation is terminated by the detection signal. As a result, the excessive timing margin in the write operation is suppressed, and the charge / discharge current of the bit line pair during the write operation is minimized, thereby realizing low power consumption and high speed of the write operation. be able to.

  By driving the dummy word line only during the write operation and activating the write detection circuit, the power consumption can be reduced during the read operation, and furthermore, a through current or a malfunction occurs in the write detection circuit during the read operation. Therefore, stable operation is possible.

  By arranging the dummy cell between the row decoder and the memory cell array, it is possible to suppress the propagation delay of the detection signal, which is the detection signal of the end timing of the write operation, and further increase the speed in the write operation. I can plan.

  By disposing a plurality of dummy cells and write detection circuits, variations in write characteristics due to characteristic variations for each memory cell can be absorbed, and more reliable write timing can be generated.

  According to the semiconductor memory device of the present invention, by using the dummy word lines for writing and reading, the dummy cells constituting the timing adjustment circuit, and the detection circuits for writing and reading, the normal writing delay and the reading delay are substantially reduced. Each operation end timing can be output based on the equal delay. As a result, by suppressing excessive timing margin in each operation and minimizing the charge / discharge current of the bit line pair during each operation, it is possible to realize low power consumption and high speed. it can.

  By arranging the dummy bit lines for writing and reading, which constitute the timing adjustment circuit, in the same configuration as the complementary bit line pair in the memory array, the load on the dummy bit line for writing and reading and the dummy bit line is reduced. Since ordinary memory cells can be diverted and shared, it is possible to realize a configuration with a reduced area compared to a case where timing adjustment circuits for writing and reading are individually provided.

  Even when the write and read dummy cells constituting the timing adjustment circuit are driven by a common dummy word line, each operation end timing is output based on a delay substantially equal to the normal write delay and read delay. As a result, it is possible to reduce power consumption by suppressing the excessive timing margin in each operation and minimizing the charge / discharge current of the bit line pair during each operation with a more area-saving configuration. As well as speeding up.

(First embodiment)
FIG. 1 shows a first embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device 100 is constituted by an SRAM, and is a synchronous SRAM that operates in synchronization with the internal clock ICLK.

  The semiconductor memory device 100 is provided with a memory cell array MARR composed of a large number of memory cells, in which m memory cells in the row direction and n memory cells (m, n ≧ 1) are arranged in the column direction. . However, in FIG. 1, only the k (1 ≦ k ≦ m) -th memory cell column is simplified for convenience.

  Here, in FIG. 10, a circuit diagram of the memory cells constituting the memory array MARR is shown.

  The memory cell includes a flip-flop that connects the input and output of the inverters INV1 and INV2, and two transfer transistors T1 and T2. The output node of the inverter INV1 is connected to the bit line BL via the transfer transistor T1, The output node of the inverter INV2 is connected to the inverted bit line NBL via the transfer transistor T2.

The memory cell array MARR has n word lines WL1 to WLn arranged in the column direction for each n memory cell rows.
The memory cell array MARR is provided with m complementary bit line pairs BL1 / NBL1 to BLm / NBLm arranged in the row direction for each memory cell column of m columns (in FIG. 1, k Only the complementary bit line pair BLk / NBLk in the column is shown).

  A column selection gate CGk composed of two N-channel transistors is connected to the complementary bit line pair BLk / NBLk. Complementary bit line pair BLk / NBLk is connected to data line pair DL / NDL via column select transistors 1 and 2 made of n-channel MOS transistors.

  A precharge circuit PTk composed of two p-channel MOS transistors 3 and 4 is connected to the complementary bit line pair BLk / NBLk. A precharge control signal PCS for performing precharge operation control is input to the common gate terminals of the transistors 3 and 4. The drain terminals of the transistors 3 and 4 are connected to one of the bit line pair BLk / NBLk and the source terminal is connected to the power source. When the precharge control signal PCS is activated, both the bit lines BLk and NBLk are connected. Charge to H level.

  The semiconductor memory device 100 has a dummy word line DWL, and loads m dummy memory cells each having the same configuration as a normal memory cell (in FIG. 1, only DMCk which is a dummy memory cell in the k-th column). Are connected) and have a parasitic capacitance equal to that of a normal word line.

  The semiconductor memory device 100 is provided with a row decoder RDC, receives a row address signal RADx (1 ≦ x ≦ n) indicating a memory cell row including a memory cell to be accessed from the outside, and synchronizes with the internal clock ICLK. The corresponding word line is activated.

  The dummy word line DWL is synchronized with the word line activated on the basis of the input of the row address RADx (1 ≦ x ≦ n) corresponding to the memory cell row including the memory cell to be accessed, and the row decoder RDC. Activated by.

  The semiconductor memory device 100 has a write circuit WAMP and a control circuit CTL. During the write operation, the control circuit CTL receives a write control signal WCS from the outside, and outputs a write enable signal WEN based on the input write control signal WCS. The write circuit WAMP is controlled by a write enable signal WEN.

  When the write circuit WAMP is activated by the write enable signal WEN, input data Din input from the outside propagates to the data line pair DL / NDL.

  The semiconductor memory device 100 is provided with a column decoder CDC, which receives a column address signal CADx indicating a memory cell column including a memory cell to be accessed, and is connected to a corresponding complementary bit line pair by a column selection signal CSk. The column selection gate CGk is activated, and the data of the data line pair DL / NDL is propagated to the complementary bit line pair BLk / NBLk via the selected column selection gate CGk.

  FIG. 2 shows a configuration example of the row decoder RDC. The configuration will be described with reference to FIG.

  The row decoder RDC has n address input terminals RADx as many as the number of memory array rows, and the row address input terminals RAD1 to RADn and the word lines WL1 to WLn correspond one-to-one. In the row decoder RDC, n two-input AND gate circuits A1 to An are arranged as input stages for each row address input terminal, and 2 inputs each row address input signal RADx and the internal clock ICLK. Form the input AND output. The 2-input AND outputs are respectively input to the buffer circuits B1 to Bn, and the word lines WL1 to WLn are driven by the connected buffer circuits B1 to Bn, respectively.

  The dummy word line DWL is driven by two stages of buffer circuits DB1 and DB2 that receive the internal clock ICLK.

  The semiconductor memory device 100 includes the above-described dummy word line DWL and a timing adjustment circuit 5 driven by the dummy word line DWL as means for detecting the write end timing. The timing adjustment circuit 5 is arranged on the side facing the row decoder RDC across the memory array MARR.

  The timing adjustment circuit 5 is configured by a circuit having a delay characteristic substantially equal to a write delay characteristic when data is written to a memory cell by the write circuit WAMP in a normal write operation. The timing adjustment circuit 5 detects this delay, and the write enable signal WEN, which is a control signal of the write circuit WAMP, is inactivated based on the detection signal of the detection signal line 8, and the write operation is terminated.

  In a normal memory cell write operation, the write circuit WAMP is activated by the write enable signal WEN, and the activated write circuit WAMP drives the bit line pair BLk / NBLk to input data to the selected memory cell. This is done by writing Din. In the semiconductor memory device 100 according to the present invention, the write end timing is generated at a timing substantially equal to the normal write delay by detecting the delay with respect to the series of write operations using the dummy word line DWL and the timing adjustment circuit 5. Let

  Next, the configuration of the timing adjustment circuit 5 will be described with reference to FIG.

  The timing adjustment circuit 5 includes a dummy cell 6, a dummy bit line DBL, and a write detection circuit 7.

The dummy bit line DBL is connected to a dummy memory cell group L provided as a load in order to give a parasitic capacitance equal to that of a normal memory cell, and for a dummy composed of an N-channel transistor whose gate is fixed at the H level. It is connected to the write detection circuit 7 via the column selection transistor DCG.
A dummy precharge circuit DPT is connected to the dummy bit line DBL. The dummy precharge circuit DPT includes a P channel MOS transistor having a gate to which a precharge control signal PCS is applied, a drain connected to a dummy bit line DBL, and a source connected to a power supply voltage. When the charge control signal PCS is activated and becomes L level, it is turned on and becomes conductive, and charges the dummy bit line DBL to H level.
The dummy cell 6 includes an N-channel transistor 6 having a gate connected to the dummy word line DWL, a drain connected to the dummy bit line DBL, and a source connected to the ground potential. This N-channel transistor is turned on when the dummy word line DWL is activated during the write operation and becomes conductive, and lowers the potential of the dummy bit line DBL charged to the H level by the dummy precharge circuit DPT.

  When the write detection circuit 7 detects the potential drop of the dummy bit line DBL, a detection signal is output to the detection signal line 8 and a write end timing is output.

  Here, the write detection circuit 7 in the present embodiment is configured by an inversion circuit 9 shown in FIG.

  The detection signal of the detection signal line 8 detected by the inverting circuit 9 is input to the row decoder RDC, the column decoder CDC, and the control circuit CTL.

  Based on the detection signal of the detection signal line 8 input to the row decoder RDC, the activated word line and dummy word line DWL are inactivated.

  Based on the detection signal of the detection signal line 8 input to the column decoder CDC, the column selection gate CGk is turned off and becomes non-conductive.

  Based on the detection signal of the detection signal line 8 input to the control circuit CTL, the write operation is ended by disabling the write enable signal WEN, and the precharge control signal PCS is controlled to the enable state. A precharge period is entered in preparation for the cycle.

  Next, an operation at the time of writing of the semiconductor memory device 100 configured as described above will be described.

  Before the write operation (precharge period), since the precharge control signal PCS is controlled to L level by the control circuit CTL, each of the P channel transistors 3 and 4 and the dummy precharge circuit DPT constituting the precharge circuit PTk. Each of the P channel transistors is in a conductive state, and the two pairs of complementary bit lines BLk / NBLk and dummy bit line DBL are connected to the power supply voltage and charged to the H level.

  When a write control signal WCS is input from the outside to the control circuit CTL at the start of access, the control circuit CTL activates the write enable signal WEN based on the input write control signal WCS. The write circuit WAMP is activated by the activated write enable signal WEN.

  Similarly, at the start of access, a row address signal RADx is input from the outside. The row decoder RDC activates any one word line corresponding to the input row address signal RADx among the word lines WL1 to WLn to the H level, and further synchronizes with the selection of the word line, to the dummy word line DWL. Activate. Here, the operation when the word line WLn is selected will be described with reference to FIG. First, when the row address signal terminal RADn corresponding to the word line WLn to be selected changes to H level (the other row address input terminals are L level), and when the internal clock ICLK changes to H level, a two-input AND gate circuit The output of An becomes H level, and the word line WLn is driven to H level via the buffer circuit Bn. As a result, referring to FIG. 10, the memory cells connected to the selected word line WLn are turned on by the transfer transistors T1 and T2, and the storage node of the memory cell becomes the bit line pair. It is electrically connected to BLk / NBLk.

  Further, the internal clock ICLK is also input to the buffer circuit DB1. During operation of the semiconductor memory device 100, the internal clock ICLK changes to H level, whereby the dummy word line DWL is activated to H level via the two-stage buffer circuits DB1 and DB2.

  As described above, the dummy word line DWL is activated based on the input of the internal clock ICLK in the same manner as the normal word lines WL1 to WLn. Therefore, the dummy word line DWL is synchronized with the activation of the word line WLn to be accessed. Will be activated.

  Further, at the start of access, when the column address signal CADx is input from the outside, the column decoder CDC selects the column corresponding to the memory cell column including the memory cell to be accessed according to the input column address signal. Signal CSk is selected and activated to H level. As a result, the column selection gate CGk becomes conductive, the bit line pair BLk / NBLk and the data line pair DL / NDL are electrically connected, and the data Din inputted from the outside at the start of access is also supplied to the column by the write circuit WAMP. Data is written into the memory cell to be accessed through the selection gate CGk.

  On the other hand, the dummy word line DWL activated to the H level in synchronization with the driving of the word line to be accessed is connected to the gate of the n-channel transistor constituting the dummy cell 6, and the N-channel transistor of the dummy cell 6 is connected. To turn on. The dummy bit line DBL is connected to the ground potential via the transistor of the dummy cell 6. As a result, the potential of the dummy bit line DBL that has been charged to the H level by the dummy precharge circuit DPT drops, and the write detection circuit 7 constituted by an inverting circuit detects the potential change of the dummy bit line DBL. When the detection signal of the detection signal line 8 as an output changes from the L level to the H level, the output of the dummy cell 6 is detected.

  The control circuit CTL inactivates the write enable signal WEN based on the detection signal of the detection signal line 8 described above. As a result, the write circuit WAMP is inactivated and the write operation is completed.

  Here, as described above, in the normal write operation, the write circuit WAMP is activated by the write enable signal WEN, and the activated write circuit WAMP drives the bit line pair BLk / NBLk to select the selected memory. This is done by writing the input data Din to the cell. In a normal design, the control circuit CTL and the dummy word line DWL are activated almost simultaneously after the address input so that the signal line of the write enable signal WEN and the dummy word line DWL are activated. Design the row decoder RDC.

  Therefore, the propagation delay of the write enable signal WEN that activates the write circuit WAMP, which is the operation delay in the row direction in the write operation, is substituted with the delay required to drive the dummy word line DWL, and the activation that is the column direction operation delay. The delay required for the write operation to the memory cell by the written write circuit WAMP is replaced with the delay characteristic by the timing adjustment circuit 5 having the same delay characteristic, so that the write end timing based on the actual write operation delay is obtained. Can be detected.

  Next, the reason why each delay can be substituted by the delay of the dummy word line DWL and the write end timing detection circuit 5 will be described. First, the operation delay time in the row direction will be described. The write enable signal WEN is connected to the same number of write circuits WAMP as the number of input / output circuits not shown here, and has a wiring load different from that of the dummy word line DWL. Since both signal lines of the signal WEN are formed of metal wiring, it can be generally considered that there is almost no difference in wiring delay. As a result, the write circuit WAMP and the dummy cell 6 controlled by these signal lines are almost the same. It will be activated at the timing. Therefore, the row direction delay in the write operation can be approximated by the delay required to drive the dummy word line DWL.

  Next, the operation delay time in the column direction will be described.

  A normal write operation is performed when the write circuit WAMP drives the bit line pair BLk / NBLk to write data to the selected memory cell. The timing adjustment circuit 5 substitutes this series of write operations by driving the dummy bit line DBL by the dummy cells 6 and inverting the output state of the write detection circuit 7.

  The dummy bit line DBL included in the write end timing detection circuit 5 has a parasitic capacitance equal to that of a normal bit line, and drives the bit line of the write circuit WAMP with the ability to drive the dummy bit line DBL of the dummy cell 6. Design is made equal to the capability, and further, the inversion level of the write detection circuit 7 is designed to be equal to the write level of the memory cell. As a result, the timing adjustment circuit 5 has a delay substantially equal to the delay time required for writing data to the memory cell by the write circuit WAMP during the normal write operation. Therefore, the column direction delay in the write operation can be approximated by the delay of the timing adjustment circuit 5.

  As described above, the dummy word line DWL and the timing adjustment circuit 5 can generate the write operation end timing substantially equal to the normal write delay.

  The detection signal of the detection signal line 8 is also input to the row decoder RDC and the column decoder CDC in addition to inactivating the write enable signal. Based on the detection signal of the detection signal line 8, the row decoder RDC is deactivated by controlling the selected word line and dummy word line DWL to L level, and the column decoder CDC is selected by the column selection signal CSk. Is controlled to L level, and the column selection gate CGk is turned off. Further, based on the detection signal of the detection signal line 8, the control circuit CTL controls the precharge control signal PCS from the H level to the L level, brings the precharge circuit PTk and the dummy precharge circuit DPT into a conductive state, The write operation is terminated by shifting to the precharge operation for the cycle.

As described above, by using the dummy word line DWL and the timing adjustment circuit 5, a delay substantially equal to the normal write delay can be detected, so that the write end timing based on the normal write delay can be generated. Thus, the write operation is terminated by the detection signal of the detection signal line 8. As a result, the excessive timing margin in the write operation is suppressed, and the charge / discharge current of the bit line pair during the write operation is minimized, thereby realizing low power consumption and high speed of the write operation. be able to.
(Second Embodiment)
A second embodiment of the semiconductor memory device according to the present invention will be described. The semiconductor memory device in the present embodiment is shown in FIG. 1 similarly to the semiconductor memory device in the first embodiment. The semiconductor memory device 100 in the present embodiment is configured by an SRAM, and the timing adjustment circuit 5 has a configuration that can operate only during a write operation, but is different from the semiconductor memory device 100 in the first embodiment described above. In other words, the dummy word line DWL is activated only during the write operation, and the write detection circuit 7 in the timing adjustment circuit 5 is activated only during the write operation.

  Since the configuration is almost the same as that of the first embodiment, only the main part will be described.

  A configuration example of the row decoder RDC in the present embodiment is shown in FIG. The same components as those of the row decoder RDC in the first embodiment shown in FIG. 2 are denoted by the same reference numerals. The difference between the row decoder RDC in the present embodiment and the configuration example in the row decoder RDC in the first embodiment described above is that the dummy word line DWL is driven by the internal clock ICLK and the write control signal WCS. . That is, the internal clock ICLK and the write control signal WCS are input to the 2-input AND gate circuit DA1, and the dummy word line DWL is activated based on the 2-input AND output. Specifically, during the write operation, the internal clock ICLK changes to the H level while the write control signal WCS is set to the H level. As a result, the output of the 2-input ANDDA1 becomes H level, the dummy word line DWL is activated to H level via the buffer circuit DB2, and the timing adjustment circuit 5 is driven.

  In the semiconductor memory device 100 according to the first embodiment of the present invention described above, since the dummy word line DWL is controlled only by the internal clock ICLK, the timing adjustment circuit 5 operates even during the read operation. Although unnecessary power consumption has occurred, the configuration of the row decoder RDC as shown in FIG. 3 described above enables the drive of the dummy word line DWL to be limited only during the write operation. The power consumption during operation can be reduced.

  However, as described above, in the configuration in which the row decoder RDC shown in FIG. 3 is applied and the dummy word line DWL can be driven only during the write operation, the following problems can be considered during the read operation.

  Simultaneously with the start of the read operation period, the precharge control signal PCS changes to the H level, the transistor of the dummy precharge circuit DPT is controlled to be turned off, and the precharge operation is released. However, since the N-channel transistor that is the dummy cell 6 is also in the off state, the dummy bit line DBL that has been charged to the H level until just before becomes a floating state, a potential drop due to a leak current or the like occurs, and the timing adjustment circuit 5 In the inverting circuit 9 constituting the write detection circuit 7, a through current may flow or a malfunction may occur.

  In view of the above problem, the write detection circuit 7 in the timing adjustment circuit 5 is configured as shown in FIG. That is, in FIG. 5, the detection signal is generated on the detection signal line 8 not only when the dummy cell 6 is output but also when the write control signal WCS is activated at the same time. That is, the signal of the dummy bit line DBL, which is the output node of the dummy cell 6, and the inverted signal 11a of the inversion circuit 11 of the write control signal WCS are input to the 2-input NAND gate circuit 10, and as the 2-input NAND output, the write end timing is Detected and a detection signal is generated on the detection signal line 8.

  Specifically, during the write operation, the level of the dummy bit line DBL that is the output of the dummy cell 6 is set while the write control signal WCS is set to the L level and the inverted signal 11 is controlled to the H level. When the level changes from the H level to the L level, the detection signal 8 that is the output signal of the two-input NAND 10 changes to the H level, and it is detected that the write operation is completed.

By using the row decoder RDC and the timing adjustment circuit 5 configured as described above, the dummy word line DWL can be driven only during the write operation, and the write detection circuit can be activated. For this reason, power consumption can be reduced during the read operation, and furthermore, the occurrence of a through current or malfunction in the write detection circuit 7 during the read operation can be avoided, so that stable operation is possible.
(Third embodiment)
FIG. 6 shows a third embodiment of the semiconductor memory device according to the present invention. The same components as those of the semiconductor memory device 100 described above are denoted by the same reference numerals.

  Semiconductor memory device 110 in the present embodiment is configured by SRAM.

  The difference from the semiconductor memory device 100 according to the first or second embodiment of the present invention described above is that the timing adjustment circuit 5 is arranged between the row decoder RDC and the memory cell array MARR. Since the configuration is substantially the same as that of the first or second embodiment, only the main part thereof will be described.

  In the semiconductor memory device 100 according to the first or second embodiment of the present invention, the dummy word line DWL and the timing adjustment circuit are used to detect a delay substantially equal to the normal write delay and output from the timing adjustment circuit 5. The write operation is completed based on the detection signal of the detection signal line 8 to be performed.

  Here, there is a delay time until the detection signal is input to the control circuit CTL. When the timing adjustment circuit 5 is arranged on the side facing the row decoder RDC across the memory cell array MARR, the detection signal line 8 is a long wiring, so the delay time due to the wiring load is the timing in the write operation. It becomes a margin.

  In the semiconductor memory device 110 according to the present embodiment, since the timing adjustment circuit 5 is arranged between the row decoder RDC and the memory cell array MARR, the delay due to the wiring load of the detection signal line 8 at the write end timing can be almost ignored. .

  Therefore, the propagation delay of the detection signal 8 in the first and second embodiments can be compressed.

As described above, by arranging the timing adjustment circuit 5 between the row decoder RDC and the memory cell array MARR, the propagation delay of the detection signal line 8 at the end timing of the write operation can be suppressed, and the write operation can be suppressed. The operation can be further speeded up.
(Fourth embodiment)
FIG. 7 shows a fourth embodiment of the semiconductor memory device according to the present invention. The same components as those of the semiconductor memory device 100 described above are denoted by the same reference numerals. Semiconductor memory device 120 in the present embodiment is configured by SRAM. The difference from the semiconductor memory device 100 according to the first embodiment of the present invention described above is that a plurality of timing adjustment circuits 5 are arranged, and the output signal of the AND gate circuit 12 having the outputs as inputs is detected signals. It passes through the detection signal line 8. In FIG. 7, as an example, two timing adjustment circuits 5 are arranged. Since the rest of the configuration is almost the same as that of the first embodiment, only the main part will be described.

  A large number of memory cells exist in the memory cell array MARR. However, in an actual semiconductor memory device, not all memory cells have the same characteristics, and there is a characteristic variation for each memory cell. Therefore, there is some variation in the time required for writing. Therefore, if the detection signal of the write end detection signal line 8 is generated at the latest timing based on the results of a large number of timing adjustment circuits 5 as in the present embodiment, more reliable writing timing can be generated. It becomes possible.

As described above, by disposing a plurality of timing adjustment circuits 5, it is possible to absorb the variation in the write characteristics due to the characteristic variation for each memory cell and to generate a more reliable write timing.
(Fifth embodiment)
FIG. 8 shows a semiconductor memory device according to a fifth embodiment of the present invention. The same components as those of the semiconductor memory device 100 described above are denoted by the same reference numerals.

  The semiconductor memory device 130 in the present embodiment is constituted by an SRAM, and means for newly detecting the end of the read operation compared to the configuration of the semiconductor memory device 100 in the second embodiment of the present invention described above. Have Here, only the main part will be described.

  The semiconductor memory device 130 in the present embodiment has a control circuit CTL, a sense amplifier SAMP, and a sense amplifier enable signal SAE. During the read operation, the control circuit CTL receives the read control signal RCS from the outside, and activates the sense amplifier enable signal SAE based on the input read control signal RCS. The sense amplifier SAMP is controlled by a sense amplifier enable signal SAE, and when activated, data is output to the outside (Dout).

  The semiconductor memory device 130 in this embodiment has a write operation dummy word line WDWL activated during a write operation and a read operation dummy word line RDWL activated during a read operation.

  The dummy word lines WDWL and RDWL are both connected to m dummy memory cells DMCk, and they have the same configuration as normal memory cells. Therefore, the load of the dummy word lines WDWL and RDWL is equivalent to that of a normal word line.

  The dummy word lines WDWL and RDWL operate in synchronization with a word line activated based on an input of a row address RADx (1 ≦ x ≦ n) indicating a memory cell row including a memory cell to be accessed. Sometimes activated by row decoder RDC.

  In addition, the semiconductor memory device 130 in the present embodiment has a timing adjustment circuit 5 that generates end timings of read and write operations.

  That is, referring to FIG. 8, the timing adjustment circuit 5 according to the present embodiment finishes the read operation having the normal read delay characteristic with respect to the configuration of the timing adjustment circuit 5 according to the first to fourth embodiments. A circuit for detecting timing is added.

  The timing adjustment circuit 5 includes a write operation dummy cell 6 and a read operation dummy cell 13, a write operation dummy bit line WDBL and a read operation dummy bit line RDBL, a read detection circuit 14, and a write detection circuit 7.

  Further, the output signal 8 of the read detection circuit 14 and the write detection circuit 7 is shared.

  The timing adjustment circuit 5 includes a dummy memory cell group L2 as a load for providing the dummy bit lines WDBL and RDBL with a parasitic capacitance equal to that of a normal memory cell.

  Here, the dummy bit lines WDBL and RDBL are arranged in the same configuration as the complementary bit line pair in the memory cell array MARR, and are arranged at the same interval as the normal bit line pair in the memory cell array MARR.

  Therefore, the dummy memory cell group L2 is configured by diverting normal memory cells and connected as a common load for the dummy bit lines WDBL and RDBL, so that the relationship between the dummy bit line and the load element is the bit in the memory cell array MARR. Since it is equivalent to the configuration of the line and the memory cell, it can be easily realized.

Further, the above configuration can be realized with a reduced area compared to the case where the timing adjustment circuits for writing and reading are individually provided.
The timing adjustment circuit 5 has a dummy column selection transistor DCG composed of N-channel transistors 15 and 16 whose gates are fixed at the H level.

  The dummy bit line RDWL is connected to the read detection circuit 14 via the N channel transistor 15, and the dummy bit line WDWL is connected to the write detection circuit 7 via the N channel transistor 16.

  A dummy precharge circuit DPT composed of two P-channel transistors 17 and 18 is connected to the dummy bit lines RDBL and WDBL. The gates of the P-channel transistors 17 and 18 are made common and the precharge control signal PCS is applied. The drain of the P-channel transistor 17 is connected to the dummy bit line RDBL, the drain of the P-channel transistor 18 is connected to the dummy bit line WDBL, and the sources of the P-channel transistors 17 and 18 are connected to the power supply voltage and precharged during the precharge period. When the control signal PCS is activated and becomes L level, it is turned on and becomes conductive, and the dummy bit lines RDBL and WDBL are charged to H level.

The dummy cell 6 for write operation is composed of an n-channel transistor 6 having a gate connected to the dummy word line WDWL, a drain connected to the dummy bit line WDBL, and a source connected to the ground potential. When the dummy word line WDWL is activated during the write operation, the n-channel transistor 6 is turned on and becomes conductive, and lowers the potential of the dummy bit line WDBL charged to the H level by the dummy precharge circuit DPT. .
When the write detection circuit 7 detects this potential drop in the dummy bit line WDBL, the write end timing is detected, and the detection signal 8 is output.

  The configuration of the write detection circuit is shown in FIG. This is the same as the write detection circuit applied in the semiconductor memory device in the second embodiment, and two signals are input to the dummy bit line WDBL which is the output node of the dummy cell 6 and the inverted signal 11a of the write control signal WCS. A detection signal is generated on the detection signal line 8 as a 2-input NAND output that is input to the NAND gate circuit 10.

  The control circuit CTL inactivates the write enable signal WEN based on the detection signal of the detection signal line 8. As a result, the write circuit WAMP is inactivated and the write operation is completed.

Next, the configuration of the dummy cell 13 for read operation is shown in FIG. 10 includes an inverter INV3 having the same configuration as the inverter pair INV1 and INV2 in the normal memory cell shown in FIG. 10 and a transfer transistor T3 connected to its output node 19. Since the input terminal of the inverter INV3 is fixed at the H level and the n-channel transistors constituting the inverter INV3 are always on, the output node 19 of the inverter INV3 is fixed at the L level.
The output node 19 of the inverter INV3 is connected to the dummy bit line RDBL via the transfer transistor T3.

  When the dummy word line RDWL is activated during the read operation and is turned on, the transfer transistor T3 is turned on by the dummy precharge circuit DPT via the transfer transistor T3 and the n-channel transistor T4 constituting the inverter INV3. The potential of the dummy bit line RDBL that has been charged to the H level drops.

  When the read detection circuit 14 detects the potential drop of the dummy bit line RDBL, a detection signal is output to the detection signal line 8.

  FIG. 12 shows a configuration example of the read detection circuit 14. A signal of the dummy bit line RDBL which is an output node of the dummy cell 13 and an inverted signal by the inverting circuit 21 of the read control signal RCS activated at the time of the read operation are input to the 2-input NAND gate circuit 20, and its 2-input NAND output is A detection signal is generated on the detection signal line 8.

  The control circuit CTL inactivates the sense amplifier enable signal SAE based on the detection signal of the detection signal line 8 described above. As a result, the sense amplifier SAMP is inactivated and the read operation is completed.

The detection signals output during the above write operation or read operation are supplied to the row decoder RDC, the column decoder CDC, and the control circuit CTL.
Based on the detection signal of the detection signal line 8 input to the row decoder RDC, the activated word line WL and the dummy word line WDWL or RDWL are inactivated.

  Based on the detection signal of the detection signal line 8 input to the column decoder CDC, the column selection gate CGk is turned off and becomes non-conductive.

  Further, based on the detection signal input to the control circuit CTL, the write operation is terminated by deactivating the write enable signal WEN. During the read operation, reading is performed by deactivating the sense amplifier enable signal SAE. As the operation ends, the precharge control signal PCS is controlled to the enable state and enters a precharge period in preparation for the next cycle.

  Next, the configuration of the row decoder RDC in the semiconductor memory device 130 is shown in FIG. A difference from the row decoder in the first embodiment shown in FIG. 2 is that each circuit element for activating the two dummy word lines RDWL and WDWL provided in the present embodiment is provided. It is.

  Specifically, in the write operation, the internal clock ICLK and the write control signal WCS activated at the time of the write operation are input to the 2-input AND gate circuit DA2, and the 2-input AND output signal is dummy through the buffer circuit DB3. The word line WDWL is activated.

  In the read operation, the internal clock ICLK and the read control signal RCS activated during the read operation are input to the 2-input AND gate circuit DA3, and the 2-input AND output signal is sent to the dummy word line RDWL through the buffer circuit DB4. Activate.

  The operation of the semiconductor memory device 130 configured as described above will be described. Since the write operation is the same as that of the second embodiment, it will be omitted, and only the read operation will be described here.

  Before the read operation (precharge period), since the precharge control signal PCS is controlled to the L level by the control circuit CTL, the P channel transistors 3, 4 constituting the precharge circuit PTk and the dummy precharge circuit DPT are controlled. , 17 and 18 are in a conductive state, and two pairs of complementary bit lines BLk / NBLk and dummy bit lines RDBL and WDBL are connected to the power supply voltage and charged to the H level.

  At the start of access, a row address signal RADx is input from the outside. Referring to FIG. 9, row decoder RDC activates any one word line corresponding to row address signal RADx inputted among word lines WL1 to WLn to H level, and further synchronizes with the word line selection. Then, the dummy word line RDWL is also activated. Here, the operation when the word line WLn is selected is the same as the operation in the row decoder RDC in the first to fourth embodiments. The memory cell connected to the selected word line drives the bit line pair BLk / NBLk.

  Further, when the read control signal RCS activated only during the read operation is set to the H level and the internal clock ICLK changes to the H level, the output of the 2-input AND circuit DA3 becomes the H level, and the buffer circuit DB4. As a result, the dummy word line RDWL is activated to H level, and the timing adjustment circuit 5 is activated.

  As described above, since the dummy word line RDWL is activated based on the input of the internal clock ICLK, like the normal word lines WL1 to WLn, the dummy word line RDWL is activated in synchronization with activation of the word line to be accessed. Will be converted.

  Similarly, when the column address signal CADx is input from the outside, the column decoder selects the column selection signal CSk corresponding to the memory cell column including the memory cell to be accessed according to the input column address signal. The selected column selection signal CSk changes to H level, and the column selection gate CGk becomes conductive. As a result, the bit line pair BLk / NBLk and the data line pair DL / NDL are electrically connected, and the voltage difference between the bit line pair BLk / NBLk driven by the selected memory cell is amplified by the sense amplifier SAMP. It will be output to the outside.

  On the other hand, referring to FIG. 11, dummy word line RDWL activated to H level in synchronization with the word line to be accessed is connected to the gate of transfer transistor T3 constituting dummy cell 13, and the transistor T3 is turned on to make it conductive. The dummy bit line RDBL is connected to the ground potential via the transistors T3 and T4. As a result, the potential of the dummy bit line RDBL charged to the H level by the dummy precharge circuit DPT drops. In the read detection circuit 14 shown in FIG. 12, the potential of the dummy bit line RDBL changes from the H level to the L level in a state where the read control signal RCS activated during the read operation is controlled at the L level. The detection signal of the detection signal line 8 that is the output of the circuit 20 changes from the L level to the H level, and the output of the dummy cell 13 is detected.

  The control circuit CTL inactivates the sense amplifier enable signal SAE based on the detection signal of the detection signal line 8 described above. As a result, the sense amplifier SAMP is inactivated and the read operation is completed.

  Here, the reason why the normal read delay can be approximated by the dummy word line RDWL and the timing adjustment circuit 5 will be described.

  Since the delay time of the read operation in the row direction is the same as that in the write operation in the semiconductor memory device in the first to fourth embodiments, only the delay time of the read operation in the column direction will be described.

  In the normal read operation, the sense amplifier SAMP detects the potential difference between the bit line pair BLk / NBLk, and the read is performed, whereas in the timing adjustment circuit 5 described above, the dummy cell 13 drives the dummy bit line RDBL. The read detection circuit 14 detects the potential fluctuation of the dummy bit line RDBL.

  The dummy bit line RDBL has a parasitic capacitance equal to that of a normal bit line, and the capability of driving the dummy bit line RDBL of the dummy cell 13 is designed to be equal to the capability of a normal memory cell to drive the bit line. The detection level of the read detection circuit 14 is designed to be equal to the detection level of the sense amplifier SAMP. As a result, the timing adjustment circuit 5 has a delay substantially equal to the delay time required to read data from the memory cell by the sense amplifier SAMP during a normal read operation, and the column direction delay in the read operation is the timing adjustment circuit. 5 can be approximated.

  As described above, by using the dummy word line RDWL and the timing adjustment circuit 5, it is possible to generate the read operation end timing substantially equal to the normal read delay, and an excessive timing margin is not required for the read operation. .

  The detection signal of the detection signal line 8 is also supplied to the row decoder RDC and the column decoder CDC. Similar to the write operation in the first to fourth embodiments, the row decoder RDC controls the selected word line and dummy word line RDWL to L level based on the detection signal of the detection signal line 8. And the column decoder controls the selected column selection signal CSk to L level to make the column selection gate CGk nonconductive, and the control circuit CTL controls the precharge control signal PCS from H level to L level. And the precharge transistors 3 and 4 and the dummy precharge transistors 17 and 18 are turned on to shift to a precharge operation for the next cycle.

  As described above, by using the dummy word lines RDWL and WDWL and the timing adjustment circuit 5, it is possible to output the respective operation end timings based on delays substantially equal to normal write delay and read delay. As a result, by suppressing excessive timing margin in each operation and minimizing the charge / discharge current of the bit line pair during each operation, it is possible to realize low power consumption and high speed. it can.

Further, by arranging the dummy bit lines RDBL and WDBL in the timing adjustment circuit 5 in the same configuration as the pair of complementary bit lines in the memory array MARR, the load on the dummy bit lines RDBL and WDBL is diverted to normal memory cells. Therefore, it is possible to realize a configuration with a reduced area compared to the case where the timing adjustment circuits for writing and reading are individually provided.
(Sixth embodiment)
FIG. 13 shows a sixth embodiment of the semiconductor memory device according to the present invention. The same components as those of the semiconductor memory device 130 described above are denoted by the same reference numerals. The semiconductor memory device 140 according to the present embodiment is constituted by an SRAM, and is different from the semiconductor memory device 130 according to the fifth embodiment of the present invention described above in that the dummy word line DWL is used for the purpose of reducing the area. Only one is provided. Since the present embodiment has substantially the same configuration as the fifth embodiment, only the main part will be described. That is, in the semiconductor memory device 130, the dummy word line WDWL for write operation and the dummy word line RDWL for read operation are provided. The dummy word lines WDWL and RWDL are individually connected to the corresponding write operation dummy cell 6 and read operation dummy cell 13 respectively, whereas in the semiconductor memory device 140 in the present embodiment, one dummy word line WDWL and RWDL is provided. Dummy word lines DWL are commonly connected to the dummy cells 6 and 13 and are driven simultaneously. Thereby, one dummy memory cell row can be reduced, and the area can be saved.

  Further, the row decoder RDC in the semiconductor memory device 140 in the present embodiment is configured as shown in FIG. 2 similarly to the semiconductor memory device 100 in the first embodiment, and the semiconductor memory in the fifth embodiment. Compared to the row decoder RDC shown in FIG. 9 provided in the device 130, the circuit portion for driving the dummy word line is reduced, so that the area can be saved.

  Similarly to the semiconductor memory device 130 in the fifth embodiment, the write detection circuit 7 has the configuration shown in FIG. 5 and is activated only during the write operation.

  Similar to the semiconductor memory device 130 in the fifth embodiment, the read detection circuit 14 has the configuration shown in FIG. 12, and is activated only during the read operation.

  Next, the operation of the semiconductor memory device 140 in this embodiment will be briefly described.

  First, referring to FIG. 2, dummy word line DWL is driven when internal clock ICLK is controlled to H level, as in the first embodiment. That is, regardless of the write / read operation, when the internal clock ICLK changes to H level during each operation, the dummy word line DWL is activated to H level via the two-stage buffer circuits DB1 and DB2.

  Next, referring to FIG. 13, when dummy word line DWL is activated to H level, dummy cells 6 and 13 in timing adjustment circuit 5 are both activated, and write operation dummy bit line WDBL and read operation respectively. The dummy bit line RDWL is driven.

  During the write operation, the write detection circuit 7 is activated by the write control signal WCS input from the outside, and the potential change of the dummy bit line WDBL is detected. Based on the detection signal of the detection signal line 8, the write operation is terminated.

  In the read operation, the read detection circuit 14 is activated by a read control signal RCS input from the outside, and detects a potential change of the dummy bit line RDBL. Based on the detection signal of the detection signal line 8, the read operation is terminated.

  Further, similarly to the semiconductor memory device in the fifth embodiment, the detection signal of the detection signal line 8 is also supplied to the row decoder RDC and the column decoder CDC, and based on the detection signal of the detection signal line 8, The row decoder RDC deactivates the selected word line and dummy word line RDWL by controlling them to the L level, and the column decoder CDC controls the selected column selection signal line CSk to the L level to control the column selection gate. The control circuit CTL controls the precharge control signal PCS from the H level to the L level to set the precharge transistors 3 and 4 and the dummy precharge transistors 17 and 18 to the conductive state. Transition to precharge operation for the cycle.

  As described above, even when the dummy cells 6 and 13 in the timing adjustment circuit 5 are driven by the common dummy word line DWL as in the semiconductor memory device 140 in the present embodiment, the semiconductor memory device 130 in the fifth embodiment and Similarly, it is possible to output each operation end timing based on a delay substantially equal to the normal write delay and read delay. As a result, an excessive timing margin in each operation is suppressed, and each operation By minimizing the charge / discharge current of the bit line pair, it is possible to achieve low power consumption and high speed. This can be realized with a configuration with a smaller area compared to the semiconductor memory device 130 in the fifth embodiment.

  The semiconductor memory device according to the present invention achieves low power consumption and suppresses the write operation by suppressing an excessive timing margin in the write operation and minimizing the charge / discharge current of the bit line pair during the write operation. It is useful as a semiconductor memory device or the like. Further, it has a timing adjustment circuit for writing and reading, and is useful as a circuit technology for generating low-power consumption and high-speed writing and reading timing with an area-saving configuration.

It is a block diagram which shows the structure of the semiconductor memory device based on 1st and 2nd embodiment. It is a block diagram which shows the structure of the row decoder provided in the semiconductor memory device concerning 1st and 6th embodiment. It is a block diagram which shows the structure of the row decoder provided in the semiconductor memory device concerning 2nd Embodiment. FIG. 3 is a block diagram illustrating a configuration of a write detection circuit according to the first embodiment. It is a block diagram which shows the structure of the write-in detection circuit in 2nd Embodiment. It is a block diagram which shows the structure of the semiconductor memory device based on 3rd Embodiment. It is a block diagram which shows the structure of the semiconductor memory device which concerns on 4th Embodiment. It is a block diagram which shows the structure of the semiconductor memory device based on 5th Embodiment. It is a block diagram which shows the structure of the row decoder provided in the semiconductor memory device concerning 5th Embodiment. It is a circuit diagram which shows the structure of a normal memory cell. It is a circuit diagram which shows the structure of the dummy cell for reading. It is a block diagram which shows the structure of the read-out detection circuit in 5th and 6th embodiment. It is a block diagram which shows the structure of the semiconductor memory device based on 6th Embodiment.

Explanation of symbols

1, 2 Column selection transistor 3, 4 Precharge transistor 5 Timing adjustment circuit 6, 13 Dummy cell 7 Write detection circuit 8 Detection signal line 9 Inversion circuit 10, 20 2-input NAND gate circuit A1, An, DA 1-3 2-input AND gate Circuit 12 AND gate circuit 14 Read detection circuit 15, 16, DCG Dummy column selection transistor 17, 18 Dummy precharge transistor DPT Dummy precharge circuit MARR Memory array WL1, WLn Word lines DWL, RDWL, WDWL Dummy word line BLk , NBLk Complementary bit line pair DBL, RDBL, WDBL Dummy bit line DL, NDL Data line pair RADx Row address signal CADx Column address signal ICLK Internal clock WCS Write control signal RCS Read Output control signal Din Input data MC1k, MCnk Memory cell DMCk Dummy memory cell L, L2 Dummy memory cell group RDC Row decoder CDC Column decoder CTL Control circuit WAMP Write circuit SAMP Sense amplifier PTk Precharge circuit CGk Column selection gate PCS Precharge control signal CSk Column selection signal WEN Write enable signal SAE Sense amplifier enable signals B1, Bn, DB1-4 Buffer circuits INV1, INV2 Inverter circuit INV3 constituting memory cells Inverter circuits T1-3 constituting read dummy cells Transfer transistors

Claims (13)

  One of the plurality of word lines, the plurality of bit line pairs, the memory cell array including a plurality of memory cells arranged at the intersections of the plurality of word lines and the plurality of bit line pairs, and the plurality of word lines Driven by activation of the dummy word line, a row decoder for activating the dummy word line, a dummy word line activated in synchronization with the activated word line, a plurality of dummy memory cells connected to the dummy word line And a write detection circuit that receives the output of the dummy cell as input, and a write end timing is generated based on an output signal of the write detection circuit.   2. The semiconductor memory device according to claim 1, wherein the activated word line and dummy word line are deactivated based on the write end timing.   3. The semiconductor memory device according to claim 1, wherein the dummy word line is activated only during a write operation.   4. The semiconductor memory device according to claim 1, wherein the dummy cell includes a transistor having a gate connected to a dummy word line, a source grounded, and a drain output.   5. The semiconductor memory device according to claim 4, wherein the drive capability of the transistors constituting the dummy cell is equal to the write drive capability for the memory cell.   6. The semiconductor memory device according to claim 1, wherein a detection level of the write detection circuit is equal to a write level of the memory cell.   7. The semiconductor memory device according to claim 1, wherein a load on the output signal line of the dummy cell is equivalent to a load on the bit line.   The semiconductor memory device according to claim 1, wherein the dummy cell is disposed between the row decoder and the memory cell array.   A plurality of dummy cells and write detection circuits are arranged, and a means for generating the latest write end timing based on the output results of the plurality of write detection circuits is provided. The word line activated by the write end timing 9. The semiconductor memory device according to claim 1, wherein the dummy word line is deactivated. One of the plurality of word lines, the plurality of bit line pairs, the memory cell array including a plurality of memory cells arranged at the intersections of the plurality of word lines and the plurality of bit line pairs, and the plurality of word lines A row decoder that activates, a first dummy word line that is activated in synchronization with the activated word line, a first plurality of dummy memory cells connected to the first dummy word line, A first dummy cell driven by the first dummy word line; a write detection circuit that receives the output of the first dummy cell; and a second that is activated in synchronization with the activated word line. A dummy word line; a second plurality of dummy memory cells connected to the second dummy word line; a second dummy cell driven by the second dummy word line; and an output of the second dummy cell. Comprising a read detecting circuit which receives the,
At the time of writing, the write end timing is generated based on the output signal of the write detection circuit,
At the time of reading, a read end timing is generated based on an output signal of the read detection circuit. One of the plurality of word lines, the plurality of bit line pairs, the memory cell array including a plurality of memory cells arranged at the intersections of the plurality of word lines and the plurality of bit line pairs, and the plurality of word lines , A dummy word line activated in synchronization with the activated word line, a plurality of dummy memory cells connected to the dummy word line, and a first driven by the dummy word line 1 dummy cell, a write detection circuit that receives the output of the first dummy cell, a second dummy cell driven by the dummy word line, and a read detection circuit that receives the output of the second dummy cell With
At the time of writing, the write end timing is generated based on the output signal of the write detection circuit,
At the time of reading, a read end timing is generated based on an output signal of the read detection circuit.   12. The semiconductor memory device according to claim 10, wherein the output signal line of the first dummy cell and the output signal line of the second dummy cell have the same configuration as the bit line pair.   12. The semiconductor memory device according to claim 10, wherein the load of the output signal line of the first dummy cell and the output signal line of the second dummy cell is equivalent to the load of the bit line and the inverted bit line of the bit line pair.

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