JP2010287266A - Sram (static random access memory) and access method to sram - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of an SRAM which performs the reading and writing of data without destructing holding data. <P>SOLUTION: The SRAM includes: a memory cell 1; a column address decoder 14; a precharge control circuit 15; and a precharge circuit 121. The precharge control circuit 15 determines the timing of precharge to a plurality of readout bit line pairs RDT<SB>0</SB>, RDB<SB>0</SB>-RDT<SB>n-1</SB>, RDB<SB>n-1</SB>according to an external clock signal CLK. The precharge circuit 121 precharges a bit line pair for selection readout RDT<SB>i</SB>and RDB<SB>i</SB>without precharging a bit line pair for non-selection readout RDT<SB>j</SB>and RDB<SB>j</SB>. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a synchronous dual port SRAM and a method for accessing a synchronous dual port SRAM.

  In order to improve data reading and writing speeds, a technique for precharging a bit line connected to a memory cell before accessing the memory cell is known. Further, the access speed to the memory cell can be changed by changing the precharge timing. For example, Japanese Patent Laid-Open No. 2001-76489 describes an SRAM that switches between a high-speed operation mode and a low-speed operation mode by changing the precharge timing (see Patent Document 1).

  FIG. 1 is a diagram showing a configuration of a conventional SRAM. Referring to FIG. 1, a conventional SRAM includes a memory cell 20 connected to a bit line 21 and a word line 22, a word line decoder 23 (WLDEC), an equalize decoder 24 (EQDEC), a precharge decoder 25, a sense amplifier. A decoder 26 (SADEC), a sense amplifier 27, and a column selector 28 are provided.

  A selection signal HL_EN for switching between the high speed operation mode and the low speed operation mode is input to each of the word line decoder 25, the equalize decoder 24, the precharge decoder 25, and the sense amplifier decoder 26. The word line decoder 25 controls the selection timing of the word line 5 according to the word line signal. The equalizing decoder 24 controls the switching operation timing of the equalizing transistor 30 connected to the bit line pair 21 according to the EQ signal. The precharge decoder 25 controls the switching operation timing of the precharge transistor 29 connected to the bit line pair 21 according to the precharge signal. The sense amplifier decoder 26 controls the sense timing of the sense amplifier according to the enable signal.

  When the selection signal HL_EN signal indicating the high-speed operation mode is input, the precharge decoder 25 starts precharge for all the columns (Banks 1 to 4). At this time, the word line decoder 25, the equalize decoder 24, and the sense amplifier decoder 26 control various operations at timings corresponding to the high-speed operation mode.

  On the other hand, when the selection signal HL_EN signal indicating the low-speed operation mode is input, the precharge decoder 25 selectively supplies the precharge signal to the read target column (for example, Bank 1), and only the precharge transistor 29 of the column is supplied. The bit line pair 21 is charged (precharged) to the power supply voltage. At this time, the word line decoder 25, the equalize decoder 24, and the sense amplifier decoder 26 control various operations at timings corresponding to the low-speed operation mode.

  Thus, in the low-speed operation mode, precharging is not performed on a column (bank) that is not a data read target, so that charge / discharge current for the column is reduced. That is. In the low-speed operation mode, the access speed is reduced, but since precharge is selectively performed, there is an effect of suppressing power consumption.

JP 2001-76489 A

  Deterioration of SRAM SNM (Static Noise Margin) becomes a problem as the process is miniaturized and the voltage is lowered. In an SRAM with a small SNM, if precharging is not performed on an unselected column, one voltage of the bit line pair may be lowered to the GND level by a read operation by the unselected memory cell itself. At this time, if both of the bit line pairs are pulled down to the GND level, there is a possibility of destructive reading when reading data from a memory cell having a small SNM. However, Patent Document 1 does not consider such a problem.

  In the SRAM described in Patent Document 1, only the selected bit line pair is precharged, and the unselected bit line pair is not precharged and becomes a floating node. In such a state, when data is written and the potential of the selected bit line pair changes drastically due to the input of data, the potential (precharge) of the adjacent bit line pair (unselected bit line pair at the time of reading). Level) may vary greatly due to coupling due to parasitic capacitance between bit lines. Further, since all equalizing transistors are turned off when data is read, the possibility that a difference potential is generated in the unselected bit line pair is increased, and destructive reading is accelerated. In particular, when the bit line arrangement interval is narrowed with the miniaturization of the process, the parasitic capacitance between the bit lines is increased, and the influence of the coupling is increased. For this reason, there is a demand for a technique for reducing power consumption while preventing occurrence of destructive reading even in a miniaturized and low-voltage SRAM.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention] The number / symbol used in [Form] is added. However, the added number / symbol should not be used to limit the technical scope of the invention described in [Claims].

The SRAM according to the present invention includes a memory cell (1), a column address decoder (14), a precharge control circuit (15), and a precharge circuit (121). The memory cell (1) has a plurality of read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ) and intersection regions of the plurality of write bit line pairs (WDT, WDB), respectively. Is provided. The column address decoder (14) includes a first read bit line pair (RDT _i , RDB _i ) connected to the first memory cell from which data is to be read, and another second read bit line pair (RDT _j , RDB _j ) are selected from a plurality of read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ). The precharge control circuit (15) determines precharge timings for a plurality of read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ) according to the external clock signal (CLK). . The precharge circuit (121) precharges the first read bit line pair (RDT _i , RDB _i ) without precharging the second read bit line pair (RDT _j , RDB _j ).

The SRAM access method according to the present invention includes a plurality of read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ) and a plurality of write bit line pairs (WDT, WDB). This is a method of accessing a memory cell (SRAM) provided in each of the areas. The SRAM access method according to the present invention includes a first read bit line pair (RDT _i , RDB _i ) connected to a first memory cell from which data is to be read, and another second read bit line pair ( RDT _j , RDB _j ) are selected from a plurality of read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ), and a plurality of bits are selected according to the external clock signal (CLK). The step of determining the precharge timing for the read bit line pairs (RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 ) and the second read bit line pair (RDT _j , RDB _j ) are precharged. Without precharging the first read bit line pair (RDT _i , RDB _i ).

  In the present invention, when data is read, precharge is not performed on unselected bit lines that are not to be read, so that the charge / discharge current for reading data can be reduced. Further, the selected bit line is precharged only during the read operation, and the precharge voltage is not supplied to the bit line during standby. For this reason, the leakage current to the bit line during standby can be suppressed. Further, since a dual port SRAM is employed, data destruction does not occur even if the bit lines are selectively precharged.

  According to the present invention, it is possible to reduce the power consumption of an SRAM that reads and writes data without destroying retained data.

FIG. 1 is a diagram showing a configuration of a conventional SRAM. FIG. 2 is a diagram showing the configuration of the SRAM according to the present invention. FIG. 3 is a diagram showing an example of the configuration of the memory cell and column selection precharge circuit according to the present invention. FIG. 4 is a diagram showing an example of an operation truth table used in the precharge control circuit according to the present invention. FIG. 5 is a timing chart showing an example of a read operation in the high-speed operation mode of the SRAM according to the present invention. FIG. 6 is a timing chart showing an example of the read operation in the low speed operation mode of the SRAM according to the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals indicate the same, similar, or equivalent components.

(Configuration of SRAM)
The configuration of the SRAM according to the present invention will be described with reference to FIGS. The present invention is preferably applied to a dual port synchronous SRAM. FIG. 2 is a diagram showing the configuration of the SRAM according to the present invention. The SRAM according to the present invention includes a memory cell array 10 connected to a read circuit 100 (Read Port) and a write circuit 200 (Write Port). The memory cell array 10 is connected to a read bit line pair RDT, RDB and word line RWL and a write bit line pair WDT, WDB and word line WWL, and includes a plurality of memory cells 1 arranged in an array. Prepare. The memory cell 1 is provided in an intersection region between the read bit line pair RDT, RDB (write bit line pair WDT, WDB) and the read word line RWL (write word line WWL).

FIG. 3 is a diagram showing an example of the configuration of the memory cell 1 and the column selection precharge circuit 12 according to the present invention. Referring to FIG. 3, in memory cell array 10, for example, a column is formed for each bit line pair. Here, n columns are formed, and each includes a read bit line pair RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−1 and a write bit line pair WDT ₀ , WDB ₀ to WDT. Memory cells 1-0 to 1- (n-1) connected to _n-1 and WDB _n-1 are arranged. For example, the memory cells 1-0 arranged in the column of the 0th column are connected to the read bit line pair RDT ₀ , RDB ₀ and the write bit line pair WDT ₀ , WDB ₀ , and read word line RWL and write Connected to the word line WWL. In the 0th column, memory cells 1 connected to other word lines RWL and WWL are also arranged, but are omitted in FIG. Similarly, the memory cell 1- (n−1) arranged in the column of the (n−1) th column includes a read bit line pair RDT _n−1 , RDB _n−1 and a write bit line pair WDT _n−1 , Connected to WDB _n−1 and connected to read word line RWL and write word line WWL. The memory cell 1 connected to the other word lines RWL and WWL is also arranged in the (n-1) th column, but is omitted in FIG. Although not shown in FIG. 3, the same applies to the structure of columns from the first column to the (n-1) th column.

  Referring to FIG. 3, a memory cell 1 according to the present invention is an SRAM cell connected to two ports, a read port and a write port. Here, the configuration of the memory cell 1-0 will be described, but the configuration of the other memory cells 1-1 to 1- (n-1) is the same, and thus the description thereof is omitted. Memory cell 1-0 includes a positive feedback loop (flip-flop) composed of two CMOS inverters INV1 and INV2, and N-channel MOS transistors N3 to N9 (hereinafter referred to as access transistors N3 to N8). The inverter INV1 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected between a first power supply (power supply voltage VDD) and a second power supply (GND), and is connected via a first storage node. Connected to access transistors N3 and N7. The inverter INV2 includes a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected between a first power supply (power supply voltage VDD) and a second power supply (GND), and is connected via a second storage node. Connected to access transistors N4 and N8.

Access transistor N3 has a gate connected to a word line WWL ₀ for writing, and a source and a drain connected to a first storage node of the bit line WDT ₀ and the inverter INV1. Thus, the access transistor N3, and controls the connection between bit line WDT ₀ and the first storage node in response to the signal level of the word line WWL ₀ (logic level). Access transistor N4 has its gate connected to a word line WWL ₀ for writing, and a source and a drain connected to the second storage node of the bit line WDB ₀ and the inverter INV2. Thus, the access transistor N4 controls the connection between bit line WDB ₀ and the second storage node in response to the signal level of the word line WWL ₀ (logic level). That is, the access transistors N3 and N4 control the connection between the memory cell 1 (storage node) and the bit line pair when writing data.

Access transistor N5 has a source and a drain gate connected to the word line RWL ₀ for reading is connected between the drain of the bit line RDB ₀ and the access transistor N7. The gate of the access transistor N7 is connected to the first storage node of the inverter INV1, and the source is connected to the second power supply (GND). Thus, the access transistors N5, N7 controls the connection between bit line RDB ₀ and the first storage node in response to the signal level of the word line RWL ₀ (logic level). Access transistor N6, a source and a drain gate connected to the word line RWL ₀ for reading is connected between the drain of the bit lines RDT ₀ and the access transistor N8. The gate of the access transistor N8 is connected to the second storage node of the inverter INV2, and the source is connected to the second power supply (GND). Thus, the access transistors N6, N8 controls the connection between bit line RDT ₀ and the second storage node in response to the signal level of the word line RWL ₀ (logic level). That is, the access transistors N5 to N8 control the connection between the memory cell 1 (storage node) and the bit line pair when reading data.

  Referring to FIG. 2, read circuit 100 reads data from memory cell array 10 in accordance with a clock signal CLK (hereinafter referred to as an external clock CLK) input from the outside. The read circuit 100 includes a read row address decoder 11 (hereinafter referred to as a row address decoder 11), a column selection precharge circuit 12 (Column SW & Precharge), a sense amplifier 13 (Sense Amp), and a read column. An address decoder (Column Address Decoder: hereinafter referred to as column address decoder 14) and a pulse generation circuit 15 are provided.

  The row address decoder 11 controls selection / non-selection of the read word line RWL. Specifically, the row address decoder 11 activates (selects) the word line RWL selected according to the row address selection signal RADD, and deactivates the other word lines RWL (unselected). At this time, the row address decoder 11 selects the word line RWL at a timing according to the internal clock signal ICLK (hereinafter referred to as the internal clock ICLK) generated in the pulse generation circuit 15.

  The column selection precharge circuit 12 electrically connects a column (bit line pair RDT, RDB) corresponding to the column selection signal RYSL and the data inputs YDT, YDB of the sense amplifier 13, and other columns (bit line pair RDT). , RDB) and data input YDT, YDB are disconnected. The column selection precharge circuit 12 precharges the bit line pair RDT, RDB according to the precharge control signal RPC. At this time, the column selection precharge circuit 12 precharges the bit line pair RDT, RDB with the precharge voltage VPC from the column address decoder 14.

Details of the configuration of the column selection precharge circuit 12 will be described with reference to FIG. Column selection precharge circuit 12, read bit line pair _{RDT 0, RDB 0 ~RDT n-} 1, RDB n-1 pre-charge circuit connected to the corresponding 121-0~121- (n-1) and Column selector 122. Precharge circuit 121-0~121- (n-1) in response to the precharge control signal _RPC 0 _{~RPC n-1} input corresponding to each bit line pair RDT connected to each RDB Is precharged by the precharge voltage VPC.

The precharge circuit 121-0 includes precharge transistors P3 and P4 and an equalize transistor P5 that are controlled to be turned on / off in response to a precharge control signal RPC ₀ supplied to each gate. The gates of the precharge transistors P3 and P4 and the equalizing transistor P5 are connected in common. Source or drain of the equalizing transistor P5 has a drain bit line RDB ₀ and the precharge transistor P3, connected between the bit lines RDT ₀ and precharge transistor P4. The sources of the precharge transistors P3 and P4 are connected to a power supply line to which a precharge voltage VPC is supplied. With such a configuration, the precharge circuit 121-0 precharges the read bit line pair RDT ₀ and RDB ₀ in accordance with the signal level (logic level) of the precharge control signal PRC ₀ . In the present embodiment, the precharge transistors P3 and P4 and the equalizing transistor P5 are P-channel MOS transistors, and are turned on in response to the precharge control signal RPC ₀ of low level “0”, and the bit line pair RDT ₀ , RDB ₀ is precharged. Since the other precharge circuits 121-1 to 121- (n-1) have the same configuration, the description thereof is omitted.

In response to the n-bit column selection signal RYSL, the column selector 122 converts bit line pairs connected to the data inputs YDT and YDB of the sense amplifier 13 to bit line pairs RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−. Select from ₁ .

  The sense amplifier 13 amplifies the differential signal input from the data inputs YDT and TDB, compares it with a reference value, thereby determining the value of the data read from the memory cell 1, and outputs it as read data Do. .

  Referring to FIG. 2, the column address decoder 14 controls selection / non-selection of a column to be read. Specifically, the column address decoder 14 outputs a column selection signal RYSL for selecting the bit line pair RDT and RDB to be read in response to the column address selection signal CADD. The column address decoder 14 includes a precharge control circuit 140 (Read Precharge Control) that determines the timing of precharging the bit line pair RDT, RDB and the magnitude of the precharge voltage VPC.

The precharge control circuit 140 supplies a precharge voltage VPC corresponding to the power supply voltage VDDC to the precharge circuits 121-0 to 121- (n−1). At this time, the precharge control circuit 140 outputs the precharge control signal RPC (RPC _{0 to} RPC _n-1 ) at the timing according to the internal clock ICLK and the external clock CLK from the pulse generation circuit 15. To 121- (n-1).

  The precharge control circuit 140 is switched to either the high speed operation mode or the low speed operation mode in accordance with the mode switching signal LSM. The precharge control circuit 140 changes the magnitude of the precharge voltage VOC and the precharge timing of the bit line pair RDT, RDB in accordance with the mode change. The precharge control circuit 140 specifies a selected column and a non-selected column according to the column address selection signal CADD.

  The precharge control circuit 140 determines the precharge timing of the bit line pair RDT, RDB based on the logical operation results based on the logic levels of the mode switching signal LSM, the external clock CLK, and the internal clock ICLK. For example, the precharge control circuit 140 controls the precharge operation by a logical operation according to the operation truth table shown in FIG. Referring to FIG. 4, when mode switching signal LSM is low level “0”, precharge control circuit 140 is in a high speed operation mode, and when high level is “1”, it is in a low speed operation mode.

  In the high-speed operation mode, the precharge control circuit 140 sets the magnitude (precharge level) of the precharge voltage VPC to the same voltage value as the power supply voltage VDD supplied to the memory cell, and outputs it to the unselected columns. The precharge control signal RPC is always set to a low level “0”. For the selected column, when the internal clock ICLK is at low level “0” regardless of the logic level of the external clock CLK, the precharge control signal RPC at low level “0” is output, and the internal clock ICLK is When the high level is “1”, the high level “1” precharge control signal RPC is output. Thus, in the high-speed operation mode, the power supply voltage VDD is always supplied to the bit line pair (non-selected bit line pair) in the non-selected column, and the internal clock ICLK is supplied to the bit line pair (selected bit line pair) in the selected column. The power supply voltage VDD is supplied only during the low level “0” period, and the supply of the power supply voltage VDD is interrupted during the high level “1” period.

  On the other hand, in the low-speed operation mode, the precharge control circuit 140 sets the precharge level to a voltage equal to or lower than the power supply voltage VDD, and always sets the precharge control signal RPC output to the non-selected column to the high level “1”. To do. For the selected column, the precharge control signal RPC at the low level “0” is output only when the external clock CLK is at the high level “1” and the internal clock ICLK is at the low level “0”. A precharge control signal RPC of high level “1” is output. Thus, in the low-speed operation mode, the precharge voltage VPC is not always supplied to the bit line pair (non-selected bit line pair) in the non-selected column, and the bit line pair (selected bit line pair) in the selected column is not externally supplied. The precharge voltage VPC is supplied only when the clock CLK is at a high level “1” and the internal clock ICLK is at a low level “0”, and the supply of the precharge voltage VPC is cut off during other periods. Here, the precharge voltage VPC in the low-speed operation mode is preferably larger than the threshold voltage of the access transistors N5 to N8 in order to suppress the degradation of the SNM.

  The internal clock ICLK is generated by the pulse generation circuit 15. Referring to FIG. 2, pulse generation circuit 15 includes a clock selection circuit 150, an internal clock generation circuit 153, and an enable signal generation circuit 154. The clock selection circuit 150 delays the external clock CLK, and a selector 152 that selects one of the external clock CLK and the output from the delay circuit 151 in accordance with the mode switching signal LSM and outputs it to the internal clock generation circuit 153. With. The delay circuit 151 may stop the delay operation according to the mode switching signal LSM. In this case, the external clock CLK is delayed and output to the selector 152 only in response to the mode switching signal LSM indicating the low-speed operation mode. The selector 152 selects the external clock CLK according to the mode switching signal LSM (low level “0”) indicating the high speed operation mode, and delays according to the mode switching signal LSM (high level “1”) indicating the low speed operation mode. The selected clock signal is selected and output to the internal clock generation circuit 153.

  The internal clock generation circuit 153 outputs an internal clock ICLK having a pulse width corresponding to the clock signal selected by the clock selection circuit 150 (selector 152) and the sense amplifier enable signal SAE output from the enable signal generation circuit 154. . The enable signal generation circuit 154 is a delay circuit that delays the internal clock ICLK and outputs it as a sense amplifier enable signal SAE. The internal clock generation circuit 153 raises the internal clock ICLK according to the rising edge of the clock signal output from the clock selection circuit 150, and falls the internal clock ICLK according to the rising edge of the sense amplifier enable signal SAE. Thereby, in the low-speed operation mode, the rising edge (trigger edge) of the internal clock ICLK is delayed from the external clock CLK.

  With the above configuration, in the high-speed operation mode, the power supply voltage VDD is supplied (precharged) to all the read bit line pairs RDT and RDB during a period other than when data is read, and the memory cell is accessed. Time is shortened. On the other hand, in the low-speed operation mode, the precharge voltage VPC lower than the power supply voltage is supplied (precharged) to the selected bit line pair RDT, RDB only during the period immediately before reading data, and the other period and the non-selected bit The supply of the precharge voltage VPC to the line is cut off. As a result, it is possible to reduce the charge / discharge current of the selected / non-selected bit line and the leakage current from the bit line of the non-selected column at the time of data reading.

(SRAM data read operation)
Next, details of the data read operation of the SRAM according to the present invention will be described with reference to FIGS. FIG. 5 is a timing chart showing an example of a read operation in the high-speed operation mode of the SRAM according to the present invention. FIG. 6 is a timing chart showing an example of the read operation in the low speed operation mode of the SRAM according to the present invention.

The details of the data read operation of the SRAM in the high-speed operation mode will be described with reference to FIG. Here, a case where data is read from the memory cell 1-i will be described. That is, the bit line pair RDT _i , RDB _i is selected (selected column), and the other bit line pair RDT _j , RDT _j (j is an integer other than i) becomes the non-selected column.

  First, the SRAM is set to the high-speed operation mode by inputting the mode switching signal LSM of low level “0”. Initially, the external clock CLK and the internal clock ICLK are at the low level “0”, and both the selected column and the non-selected column are precharged with the power supply voltage VDD (time T1).

Next, the internal clock ICLK rises in response to the rising edge (trigger edge) of the external clock CLK (time T2). At this time, the selected word line RWL is activated in response to the rising edge (trigger edge) of the internal clock ICLK, and the column selection signal RYSL _i and the precharge control signal RPC _i for the selected column transition to the high level “1”. . The memory cells 1-0 to 1- (n−1) connected to the activated selected word line RWL are electrically connected to the bit line pairs RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−1. Is done. The bit line pair RDT _i , RDB _i is connected to the sense amplifier 13 in response to the high level column selection signal RYSL _i . As a result, the voltage difference between the bit line pair RDT _i and RDB _i propagates to the data inputs YDT and YDB of the sense amplifier 13. Further, the supply of the power supply voltage VDD to the bit line pair RDT _i and RDB _i is cut off in response to the high-level precharge control signal RPC _i . At this time, the supply of the power supply voltage VDD to the unselected bit lines RDT _j and RDB _j is maintained.

In the high-speed operation mode, all the precharge control signals RPC _{0 to} RPC _n−1 are at the low level “0” until the time T2 when the SRAM starts the read operation by the input (rise) of the external clock CLK. That is, during this period, the power supply voltage VDD is supplied to all the bit line pairs. Therefore, at time T2, all the bit line pairs are charged / discharged in response to the rise of word line RWL.

After a predetermined time has elapsed from the rising edge of the internal clock ICLK, the sense amplifier enable signal SAE rises (time T3). As a result, the sense amplifier 13 senses the difference voltage between the selected bit line pair RDT _i and RDB _{i and} outputs it as read data Do.

The internal clock ICLK falls after the read data Do is output (after a predetermined time has elapsed since the rising edge of the sense amplifier enable signal SAE). In response to the falling edge of the internal clock ICLK, the selected word line RWL is deactivated, and the column selection signal RYSL _i and the precharge control signal RPC _i for the selected column transition to the low level “0”. Thereby, the electrical connection between the memory cells 1-0 to 1- (n-1) and the bit line pairs RDT ₀ , RDB ₀ to RDT _n-1 , RDB _n-1 is cut off. Further, the supply of the power supply voltage VDD to the bit line pair RDT _i , RDB _i is started again in response to the low level precharge control signal RPC _i . As a result, the bit line pairs RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−1 are charged to the power supply voltage VDD.

  In the high-speed operation mode, the bit line pair RDT, RDB is charged to the power supply voltage VDD before the appearance of the trigger edge of the external clock CLK. The In addition, since the bit line pair RDT, RDB is precharged with the power supply voltage VDD, the time from selection of the read target memory cell to data sensing is shortened. Note that the precharge voltage VPC in the high-speed operation mode may be lower than the power supply voltage VDD in accordance with the access speed to the memory cell. Thereby, charging / discharging current can be suppressed and current consumption can be reduced even in the high-speed operation mode.

Next, details of the data read operation of the SRAM in the low speed operation mode will be described with reference to FIG. Here, as in the high-speed operation mode, a case where data is read from the memory cell 1-i will be described. That is, the bit line pair RDT _i , RDB _i is selected (selected column), and the other bit line pair RDT _j , RDT _j (j is an integer other than i) becomes the non-selected column.

First, the SRAM is set to the low-speed operation mode by inputting the mode switching signal LSM of high level “1”. Initially, since the external clock CLK and the internal clock ICLK are at the low level “0”, the precharge signals RPC _i and RPC _j for the selected column and the non-selected column are both at the high level “1” (time T1). That is, before the read operation in the low-speed operation mode, the precharge operation for all the bit lines RDT ₀ , RDB _{0 to} RDT _n−1 , RDB _n−1 is not performed.

Next, in response to the rising edge (trigger edge) of the external clock CLK before the generation of the internal clock CLK (low level), the precharge control signal RPC _i for the selected column transitions to the low level “0” (time T2). . As a result, the selected column (bit line pair RDT _i , RDB _i ) is precharged by the precharge voltage VPC. The precharge voltage VPC is preferably set lower than the power supply voltage VDD by a predetermined value X. Thereby, leakage current from the bit line can be reduced. On the other hand, the precharge control signal RPC _j for the non-selected column maintains the high level “1” throughout the entire period. That is, in the SRAM according to the present invention, the precharge for the unselected bit line pair RDT _j and RDB _j is stopped during the read operation in the low-speed operation mode.

After a predetermined time has elapsed from the external clock CLK, the internal clock ICLK rises (time T3). In response to the rising edge (trigger edge) of the internal clock ICLK, the selected word line RWL is activated, and the column selection signal RYSL _i and the precharge control signal RPC _i for the selected column transition to the high level “1”. The memory cells 1-0 to 1- (n−1) connected to the activated selected word line RWL are electrically connected to the bit line pairs RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−1. Is done. The bit line pair RDT _i , RDB _i is connected to the sense amplifier 13 in response to the high level column selection signal RYSL _i . As a result, the voltage difference between the bit line pair RDT _i and RDB _i propagates to the data inputs YDT and YDB of the sense amplifier 13. Further, the supply of the precharge voltage VPC to the bit line pair RDT _i and RDB _i is cut off in response to the high level precharge control signal RPC _i .

After a predetermined time has elapsed from the rising edge of the internal clock ICLK, the sense amplifier enable signal SAE rises (time T4). Thus, the sense amplifier 13, the selected bit line pair _RDT i, senses the voltage difference between the RDB _i, and outputs it as read data Do.

The internal clock ICLK falls after the read data Do is output (after a predetermined time has elapsed since the rising edge of the sense amplifier enable signal SAE). In response to the falling edge of the internal clock ICLK, the selected word line RWL is deactivated, and the column selection signal RYSL _i for the selected column transitions to the low level “0”. Thereby, the electrical connection between the memory cells 1-0 to 1- (n-1) and the bit line pairs RDT ₀ , RDB ₀ to RDT _n-1 , RDB _n-1 is cut off. Further, the precharge control signal RPC _i maintains the low level “0” even after the read data Do is output. For this reason, in the SRAM according to the present invention, after the data is read, the supply (charging) of the precharge voltage to all the bit line pairs RDT ₀ , RDB ₀ to RDT _n−1 , RDB _n−1 is stopped.

  In the low-speed operation mode, only the selected column is precharged immediately before data is written, and the supply of the precharge voltage to the other non-selected columns is stopped. Since the charge is not discharged from the bit line pair of the non-selected column and is not charged in the non-selected access cycle, the power consumption in the non-selected column can be reduced.

  In the standby state in the low-speed operation mode, the supply of the precharge voltage VPC to all the bit line pairs RDT and RDB is stopped (not precharged). Therefore, the leakage current from the read bit line pair RDT, RDB to the memory cell 1 can be reduced.

  The differential type SRAM realizes a high-speed read operation by amplifying and reading the minute difference potential read to the data inputs YDT and YDB. In this case, the threshold voltages of the access transistors N5 to N8 are N-channel MOS transistors N1 of the inverters INV1 and INV2 constituting the memory cell 1 in order to obtain the potential difference by discharging the charges of the bit line pair RDT and RDB at high speed. , N2 is set lower. For this reason, in the high-speed operation mode, leakage current from access transistors N5 to N8 increases. However, in the low-speed operation mode, since the precharge voltage VPC is supplied (precharge) to all the bit lines during standby and to the unselected bit line pair during reading, leakage current to the access transistors N5 to N8 Can be reduced.

  In the present invention, the timing adjustment in the low-speed operation mode can be realized only by adjusting the delay so that the precharge is completed from the rising edge of the external clock CLK until the internal clock ICLK rises. Further, in switching the operation mode, the timing margin in the SRAM is the same as the conventional one except for the timing of the precharge control signal RPC, so that the design is easy.

  Unlike the patent document 1, the present invention controls bit line equalization and precharge with a common precharge control signal RPC. For this reason, a signal line dedicated for equalization is not required, and the charge / discharge current can be reduced by the current dedicated for equalization.

  The SRAM according to the present invention has a structure in which the read port and the write port are separated and the read operation does not affect the data held in the memory cell 1. Therefore, the data stored in the memory cell is not affected even if the precharge of the read bit line pair RDT, RDB is not performed. That is, data destruction does not occur even if the non-selected bit line is not precharged. Therefore, according to the present invention, it is possible to reduce the power consumption of the SRAM without causing data destruction.

  Further, according to the present invention, the high-speed operation mode and the low-speed operation mode can be switched according to the application. Note that the switching mechanism is not provided, and only a low-speed operation mode (power saving mode) that reduces power consumption may be applied.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. .

1, 1-0 to 1- (n-1): memory cell 10: memory array 11: row address decoder 12: column selection precharge circuit 13: sense amplifier 14: column address decoder 15: pulse generation circuit 121-0 121 (n-1): Precharge circuit 122: Column selector 140: Precharge control circuit 150: Clock selection circuit 151: Delay circuit 152: Selector 153: Internal clock generation circuit 154: Enable signal generation circuit RDT, RDB: For reading Bit line (bit line pair)
RWL: Read word line VPC: Precharge voltage RPC: Precharge control signal RYSL: Column selection signal CLK: External clock signal ICLK: Internal clock signal SAE: Sense amplifier enable signal

Claims (12)

A memory cell provided in each of the intersection regions of the plurality of read bit line pairs and the plurality of write bit line pairs;
A column address decoder for selecting a first read bit line pair connected to the first memory cell from which data is to be read and another second read bit line pair from the plurality of read bit line pairs; ,
A precharge control circuit for determining a precharge timing for the plurality of read bit line pairs in accordance with an external clock signal;
An SRAM (Static Random Access Memory) comprising: a precharge circuit that precharges the first read bit line pair without precharging the second read bit line pair. The SRAM according to claim 1,
The precharge control circuit supplies a precharge voltage having a magnitude set according to a mode switching signal to the precharge circuit;
The precharge circuit precharges the first read bit line pair with the precharge voltage SRAM. The SRAM according to claim 2,
The precharge control circuit switches between one of a high speed operation mode and a low speed operation mode in response to a mode switching signal, and supplies a power supply voltage to the precharge circuit as a precharge voltage in the high speed operation mode. A precharge voltage lower than the power supply voltage is supplied to the precharge circuit,
The precharge circuit precharges the first read bit line pair with the precharge voltage SRAM. The SRAM according to any one of claims 1 to 3,
A pulse generation circuit that delays the external clock signal to generate an internal clock signal;
A sense amplifier that detects a voltage of a bit line pair of a selected column according to an enable signal generated by delaying the internal clock;
The precharge circuit starts precharging the first read bit line pair in response to a trigger edge of the external clock signal, and precharges the first read line in response to a trigger edge of the internal clock signal. Terminate SRAM. The SRAM according to claim 4,
The precharge control circuit determines a precharge timing according to a logical operation result of a logic level of the external clock signal and a logic level of the internal clock signal. The SRAM according to claim 5,
The precharge control circuit switches between one of a high speed operation mode and a low speed operation mode according to a mode switching signal,
In the high-speed operation mode, the precharge circuit stops precharging the first read bit line pair during the high level period of the internal clock signal, and the entire period excluding the high level period of the internal clock signal. Precharging the plurality of read bit lines and precharging the first read bit line pair only during a period in which the external clock signal is at a high level and the internal clock signal is at a low level in the low-speed operation mode. An SRAM that stops precharging the plurality of read bit line pairs during a period other than a period when the external clock signal is at a high level and the internal clock signal is at a low level. In an access method to an SRAM (Static Random Access Memory) provided in each of intersection areas of a plurality of read bit line pairs and a plurality of write bit line pairs,
Selecting a first read bit line pair connected to a first memory cell from which data is to be read and another second read bit line pair from the plurality of read bit line pairs;
Determining a precharge timing for the plurality of read bit line pairs according to an external clock signal;
Precharging the first read bit line pair without precharging the second read bit line pair, and accessing the SRAM. The method of accessing an SRAM according to claim 7,
Supplying a precharge voltage of a magnitude set according to a mode switching signal to the precharge circuit;
Further comprising
The precharging step includes a step of precharging the first read bit line pair with the precharge voltage. The method for accessing an SRAM according to claim 7 or 8,
Switching to one of a high-speed operation mode and a low-speed operation mode according to a mode switching signal;
Supplying a power supply voltage to the precharge circuit as a precharge voltage in the high-speed operation mode; supplying a precharge voltage lower than the power supply voltage to the precharge circuit in the low-speed operation mode;
Further comprising
The precharging step includes a step of precharging the first read bit line pair with the precharge voltage. The method for accessing an SRAM according to any one of claims 7 to 9,
The step of determining the precharge timing includes:
Delaying the external clock signal to generate an internal clock signal;
Starting precharging the first read bit line pair in response to a trigger edge of the external clock signal;
Ending precharge for the first read line in response to a trigger edge of the internal clock signal,
A method of accessing an SRAM, further comprising a step of detecting a voltage of a bit line pair of a selected column in accordance with an enable signal generated by delaying the internal clock. The method of accessing an SRAM according to claim 10,
The step of determining the precharge timing includes a step of determining a precharge timing according to a logical operation result of the logical level of the external clock signal and the logical level of the internal clock signal. The method for accessing an SRAM according to claim 11,
Further comprising a step of switching to one of a high-speed operation mode and a low-speed operation mode in response to a mode switching signal;
The precharging step includes:
In the high-speed operation mode, during the high level period of the internal clock signal, the precharge to the first read bit line pair is stopped, and the plurality of read-out periods are performed for all periods except the high level period of the internal clock signal. Precharging the bit line;
In the low-speed operation mode, the first read bit line pair is precharged only while the external clock signal is at a high level and the internal clock signal is at a low level, the external clock signal is at a high level, and the internal clock signal is Stopping the precharge of the plurality of read bit line pairs during a period other than a period when the clock signal is at a low level.

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