KR100867538B1 - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a method of manufacturing the thin film transistor array to prevent the occurrence of a short defect between the storage line and the gate line.

A thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention include a first through hole formed through a gate insulating film and a protective film between a storage line and a gate line, and including forming a first through hole. Characterized in that.

Description

Thin Film Transistor Array Substrate and Method of Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME}             

1 is a plan view illustrating a portion of a thin film transistor array substrate included in a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 1 taken along the line AA ′.

3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a liquid crystal display device driven by a double bank driving method.

5 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the thin film transistor array substrate of FIG. 5 taken along the line BB ′.

7A through 7D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 5.                 

8 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view of the thin film transistor array substrate of FIG. 8 taken along the line CC ′.

10A through 10E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 8.

11 is a plan view illustrating a thin film transistor array substrate according to a third exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view of the thin film transistor array substrate of FIG. 11 taken along the line D-D '.

13A to 13E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 11.

 <Description of Symbols for Main Parts of Drawings>

1, 51: lower substrate 2, 52: gate line

4, 54: data line 6, 56: gate electrode

8, 58: source electrode 10, 60: drain electrode

12, 62: gate insulating film 14, 64: active layer

16, 66: ohmic contact layer 18, 68: protective film

22 and 72: pixel electrodes 26a and 76a: first contact hole                 

26b, 76c: second contact hole 26c, 76d: third contact hole

26d: fourth contact hole 28: data pad

30: data pad protective electrode 32: gate pad

36: gate pad protection electrode 76b: gate through hole

90: drain through hole 91: redundancy pattern

95: capacitance equivalent pattern

The present invention relates to a thin film transistor array substrate and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same to prevent the generation of misalignment between storage lines and gate lines.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. Each of the liquid crystal cells is provided with pixel electrodes and a common electrode for applying an electric field. Each of the pixel electrodes is connected to one of the data lines via a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines for causing the pixel voltage signal to be applied to the pixel electrodes for one line. The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signal, that is, the gate signal to the gate lines, to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode. Accordingly, the liquid crystal display device displays an image by adjusting the light transmittance by changing the liquid crystal arrangement state between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

In practice, the liquid crystal display includes a thin film transistor array substrate as shown in FIG. FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line AA ′.

The thin film transistor array substrate 11 illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating layer 12 interposed therebetween on a lower substrate 1, and an intersection thereof. Each of the thin film transistors TP, the pixel electrode 22 formed in the cell region provided in the intersection structure, and the storage capacitor SP formed at the overlapping portion of the previous gate line 22 and the pixel electrode 22. .

The thin film transistor TP includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. And an active layer 14 overlapping the gate electrode 6 and forming a channel between the source electrode 8 and the drain electrode 10. The active layer 14 is formed to overlap the data line 4, the source electrode 8, and the drain electrode 10, and further includes a channel portion between the source electrode 8 and the drain electrode 10. An ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, and the drain electrode 10 is further formed on the active layer 14. The thin film transistor TP causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 22 in response to the gate signal supplied to the gate line 2.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor TP through the first contact hole 26a penetrating through the passivation layer 18, and the gate line 2 through the second contact hole 26b. Is connected to the storage electrode 24 superimposed on a portion of the (). The pixel electrode 22 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal located between the thin film transistor substrate and the upper substrate is rotated by dielectric anisotropy and transmits light incident through the pixel electrode 22 from a light source (not shown) toward the upper substrate (not shown).

The gate line 2 is connected to a gate driver (not shown) through the gate pad part GP, and the data line 4 is connected to a data driver (not shown) through the data pad part DP.

The gate pad portion GP is formed in the gate pad 32 through the gate pad 32 extending from the gate line 2 and the third contact hole 26c penetrating through the gate insulating film 12 and the passivation layer 18. The gate pad protective electrode 36 is connected.

The data pad part DP is provided through the data pad 28 extending from the data line 4 via a data link (not shown) and through the fourth contact hole 26d penetrating through the passivation layer 18. And a data pad protection electrode 30 connected to the 28. As shown in FIG.

The storage capacitor SP is formed of a storage electrode 24 overlapping the gate line 2 with the previous gate line 2 and the gate insulating layer 12 interposed therebetween and connected to the pixel electrode 22. The storage capacitor SP keeps the data voltage applied to the pixel electrode 22 constant.

A method of manufacturing a thin film transistor substrate having such a configuration is shown in FIGS. 3A to 3E by a five mask process.

Referring to FIG. 3A, gate patterns are formed on the lower substrate 1.

The gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 2, the gate electrode 6, and the gate pad 32. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 3B, the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 are formed on the lower substrate 1 on which the gate patterns are formed.                         

The gate insulating layer 12, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower substrate 1 on which the gate patterns are formed by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously etched by the photolithography process and the etching process using the second mask to form the ohmic contact layer 16 and the active layer 14. As the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Referring to FIG. 3C, source / drain patterns are formed on the gate insulating layer 12 on which the active layer 14 and the ohmic contact layer 16 are formed.

A source / drain metal layer is formed on the gate insulating film 12 on which the active layer 14 and the ohmic contact layer 16 are formed by a deposition method such as sputtering. Subsequently, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask to form the data line 4, the source electrode 8, the drain electrode 10, the storage electrode 24, and the data pad 28. Source / drain patterns are formed. Then, the ohmic contact layer 16 between the source electrode 8 and the drain electrode 10 is removed by a dry etching process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), chromium (Cr), and the like are used.

Referring to FIG. 3D, a passivation layer 18 including a plurality of contact holes 26a to 26d is formed on the gate insulating layer 12 on which the source / drain patterns are formed.

The passivation layer 18 is entirely formed on the gate insulating layer 12 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 18 is patterned by a photolithography process using a fourth mask and a dry etching process to form first to fourth contact holes 26a to 26d. The first contact hole 26a is formed to pass through the passivation layer 18 to expose the drain electrode 10, and the second contact hole 26b is formed to pass through the passivation layer 18 to expose the storage electrode 24. Is formed. The third contact hole 26c is formed to pass through the passivation layer 18 and the gate insulating layer 12 to expose the gate pad 32. The fourth contact hole 26d is formed through the passivation layer 18 to expose the data pad 28. As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3E, transparent electrode patterns are formed on the passivation layer 18.

The transparent electrode material is deposited on the protective film 18 by a deposition method such as sputtering. Subsequently, the transparent electrode material is patterned through a photolithography process and an etching process using a fifth mask to form transparent electrode patterns such as the pixel electrode 22, the gate pad protection electrode 36, and the data pad protection electrode 30. do. The pixel electrode 22 is in surface contact with the drain electrode 10 through the first contact hole 26a and is in surface contact with the storage electrode 24 through the second contact hole 26b. The gate pad protection electrode 32 is in surface contact with the gate pad 32 through the third contact hole 26b, and the data pad protection electrode 30 is in contact with the data pad 28 through the fourth contact hole 26d. If you contact with. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.                         

As described above, the conventional thin film transistor array substrate mainly adopts a storage-on-gate method in which the storage capacitor SP is formed on the gate line 2. When the storage capacitor SP is formed on the gate line 2, the capacitance on the gate line 2 increases. The increase in capacitance of the gate line 2 may cause insulation breakdown of the liquid crystal panel, or increase the load of the gate line 2 to delay the gate signal on the gate line 2 to generate a luminance difference for each cell. do. As a result, the liquid crystal panel employing this substrate has a problem that spots occur in the screen display area. In other words, in the conventional thin film transistor array substrate using the storage-on-gate method, the capacitance of the gate line 2 increases so that the signal quality supplied to the gate line 2 is degraded and the display quality of the liquid crystal display device is reduced. Degrades.

In addition, as production of a large-area liquid crystal display (hereinafter referred to as "LCD") has recently begun, a large-area LCD includes a driver for driving an upper side and a driver for driving a lower side, as shown in FIG. 4. The double bank drive system provided is adopted. In case of adopting a storage-on-gate storage capacitor (SP) even in a large area LCD adopting such a double bank driving method, a gate signal on the gate line 2 is delayed due to an increase in the load amount of the gate line 2. There is. The delay of the gate signal becomes larger at the interface between the upper side and the lower side, causing a difference in luminance at the interface, resulting in deterioration of the display quality of the LCD.

 Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method for manufacturing the same, which can reduce the load amount of the gate line by separating the storage capacitor from the gate line.

Another object of the present invention is to form a thin film transistor array substrate and its fabrication that can prevent the occurrence of misalignment between the storage line and the gate line when the storage line is formed parallel to the gate line to separate the storage capacitor from the gate line. To provide a way.

In order to achieve the above object, the thin film transistor array substrate according to the present invention includes a gate line to which a gate voltage is supplied, a storage line parallel to the gate line adjacent to the gate line, and a gate line and the storage line with a gate insulating film interposed therebetween. A thin film transistor connected to an intersection of the data line, the gate line and the data line intersecting the pixel line; And a storage capacitor formed at an overlapping portion of the pixel electrode, and a first through hole formed between the storage line and the gate line through the gate insulating film and the protective film.

The first through hole may pass through the passivation layer and the gate insulating layer.

In the thin film transistor array substrate according to the present invention, the storage capacitor further comprises a storage electrode overlapping the storage line and connected to the pixel electrode.

The first through hole may be integrated with a contact hole for connecting the storage electrode and the pixel electrode.

A thin film transistor array substrate according to the present invention is characterized by having a capacitance equivalent pattern overlapping a part of a pixel electrode, parallel to a data line, and integrated with a storage electrode.

The width of the first through hole is at least 2 μm.

In the thin film transistor array substrate according to the present invention, a second through hole penetrating the gate insulating film and the protective film is provided between the capacitance equivalent pattern and the data line.

A thin film transistor array substrate according to the present invention is characterized by having a redundancy pattern overlapping a data line with a gate insulating film interposed therebetween.

A method of manufacturing a thin film transistor array substrate according to the present invention includes a gate line, a storage line adjacent to and parallel to the gate line, a data line intersecting the gate line and the storage line with a gate insulating film interposed therebetween, A first step of forming a thin film transistor positioned at an intersection of the lines, a second step of forming a first pass hole between the contact hole, the gate line, and the storage line by forming a protective film on the entire surface of the substrate and patterning the contact hole; It characterized in that it comprises a three step of forming a pixel electrode connected to the thin film transistor through.                     

The first step includes forming a gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a storage line adjacent to and parallel to the gate line, and covering the gate pattern on the substrate. Forming the entire surface, forming a semiconductor layer of the thin film transistor on the gate insulating film, and forming a source / drain pattern including a data line, a source electrode and a drain electrode of the thin film transistor on the gate insulating film on which the semiconductor layer is formed. Characterized in that it comprises a step.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the source / drain pattern may further include forming a storage electrode overlapping the storage line and connected to the pixel electrode.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the first through hole further includes forming a contact hole integrated with the first through hole and connecting the storage electrode and the pixel electrode to each other. It features.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the source / drain pattern may include forming a capacitance equivalent pattern overlapping a portion of the pixel electrode, parallel to the data line, and integrated with the storage electrode. It further comprises.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the first through hole is formed through the protective film and the gate insulating film.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the width of the first through hole is at least 2 μm.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the first through hole further includes forming a second through hole penetrating the passivation layer and the insulating layer between the capacitance equivalent pattern and the data line. Characterized in that.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the gate pattern may further include forming a redundancy pattern to overlap the data line with the gate insulating layer interposed therebetween.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 13.

5 and 7 are a plan view and a cross-sectional view showing a thin film transistor array substrate according to a first embodiment of the present invention.

5 and 7 are a plan view and a cross-sectional view showing a thin film transistor array substrate according to a first embodiment of the present invention.

5 and 6, the thin film transistor array substrate according to the first embodiment of the present invention may include a gate line 52 formed on the lower substrate 51 and a storage line parallel to the gate line 52. 88, a data line 54 arranged to intersect the gate line 52 and the storage line 88 with the gate insulating film 62 therebetween, the thin film transistor TP formed at each intersection thereof, and the intersection thereof. The pixel electrode 72 formed in the cell region having the structure, the storage capacitor SP formed at an overlapping portion of the pixel electrode 72 and the storage line 88, the previous gate line 52 and the storage capacitor SP. A first through-hole 76b formed therebetween and a capacitance equivalent pattern 95 extending from the storage electrode 74 of the storage capacitor SP and parallel to the data line 54. .

The thin film transistor TP includes a gate electrode 56 connected to the gate line 52, a source electrode 58 connected to the data line 54, a drain electrode 60 connected to the pixel electrode 72, and And an active layer 64 overlapping the gate electrode 56 and forming a channel between the source electrode 58 and the drain electrode 60. The active layer 64 further includes a channel portion formed to overlap the data line 54, the source electrode 58, and the drain electrode 60, and formed between the source electrode 58 and the drain electrode 60. An ohmic contact layer 66 for ohmic contact with the data line 54, the source electrode 58, and the drain electrode 60 is further formed on the active layer 64. The thin film transistor TP keeps the pixel voltage signal supplied to the data line 54 charged in the pixel electrode 72 in response to the gate signal supplied to the gate line 52.

The pixel electrode 72 is connected to the drain electrode 60 of the thin film transistor TP through the first contact hole 76a passing through the passivation layer 68. The pixel electrode 72 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to the potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate is rotated by dielectric anisotropy and transmits light incident from the light source (not shown) via the pixel electrode 72 toward the upper substrate (not shown). .

The gate line 52 is connected to a gate driver (not shown) through the gate pad part GP as shown in FIG. 1, and the data line 54 is connected to a data driver (not shown) through the data pad part DP. Not connected).

The gate pad portion GP may include the gate pad 32 connected to the gate line 52, the gate pad 32 through the second contact hole 76c penetrating through the passivation layer 68 and the gate insulating layer 62. It consists of the gate pad protection electrode 36 connected.

The data pad part DP includes a data pad 28 connected to the data line 54 and a data pad protection electrode connected to the data pad 28 through a third contact hole 76d passing through the passivation layer 68. It consists of 30.

The capacitance equivalent pattern 95 parallel to the data line 54 is connected to the pixel electrode 72 through the storage electrode 74 or integrated with the storage electrode 74 to be connected to the pixel electrode 72. The capacitive equivalent pattern 95 is formed of a source / drain metal on the same layer as the data line 54 and connected to the pixel electrode 72 so that a difference in distance between the pixel electrode 72 and the data line 54 is achieved. This prevents the parasitic capacitor capacity deviation caused by. Parasitic capacitor capacitance variation distorts the driving voltage of the data line 54, resulting in deterioration of image quality. The variation of the parasitic capacitor capacitance between the pixel electrode 72 and the data line 54 is caused by misalignment of the mask for forming the pattern of the data line 54 and the mask for forming the pattern of the pixel electrode 72. And the separation distance between the data lines 54 is different for each cell. The difference in separation distance between the pixel electrode 72 and the data line 54 is prevented by the capacitance equivalent pattern 95, thereby preventing occurrence of parasitic capacitor capacitance variation.

The storage capacitor SP includes a storage line 88 and a storage electrode 74 positioned between the storage line 88 and the gate insulating layer 12 and connected to the pixel electrode 72. The storage capacitor SP keeps the data voltage applied to the pixel electrode 72 constant.

The first through hole 76b is formed between the storage line 88 and the front gate line 52. Accordingly, the first through hole 76b is left in the narrow gap between the front gate line 52 and the storage line 88, the residue of the photo-resist used during the photolithography process is left. Will be prevented. As a result, the first through hole 76b prevents a pattern defect caused by the residue of the photoresist remaining between the front gate line 52 and the storage line 88, and furthermore, unevenness of the liquid crystal display device due to the pattern defect. It is possible to prevent afterimages and sorting defects.

A method of manufacturing a thin film transistor substrate having such a configuration is shown in FIGS. 7A to 7E by a five mask process.

Referring to FIG. 7A, gate patterns are formed on the lower substrate 51.

The gate metal layer is formed on the lower substrate 51 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, so that the gate includes the gate line 52, the gate electrode 56, the gate pad 32, and the storage line 88. Patterns are formed. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 7B, a gate insulating layer 62, an active layer 64, and an ohmic contact layer 66 are formed on the lower substrate 51 on which the gate patterns are formed.

The gate insulating layer 52, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower substrate 51 on which the gate patterns are formed through a deposition method such as plasma enhanced chemical vapor deposition (PECVD). Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously etched by the photolithography process and the etching process using the second mask to form the ohmic contact layer 56 and the active layer 54. As the material of the gate insulating film 62, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Referring to FIG. 7C, source / drain patterns are formed on the gate insulating layer 62 on which the active layer 64 and the ohmic contact layer 66 are formed.

A source / drain metal layer is formed on the gate insulating film 62 on which the active layer 64 and the ohmic contact layer 66 are formed by a deposition method such as sputtering. Subsequently, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask, so that the data line 54, the source electrode 58, the drain electrode 60, the storage electrode 74, and the capacitance equivalent are used. Source / drain patterns including the pattern 95 and the data pad 28 are formed. The ohmic contact layer 66 between the source electrode 58 and the drain electrode 60 is removed by a dry etching process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), chromium (Cr), and the like are used.

Referring to FIG. 7D, a passivation layer 68 including a plurality of contact holes 76a, 26c and 26d and a first through hole 76b is formed on the gate insulating layer 62 on which the source / drain patterns are formed.

The passivation layer 68 is entirely formed on the gate insulating layer 62 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 68 is patterned by a photolithography process using a fourth mask and a dry etching process to form contact holes 76a, 26c, and 26d and a first through hole 76b. The first contact hole 76a is formed through the passivation layer 68 to expose the drain electrode 60. The first through hole 76b is formed between the storage line 88 and the front gate line 52 through the passivation layer 68 and the gate insulating layer 62, and is formed to expose a portion of the storage electrode 74. . That is, the first through hole 76b is integrated with the storage contact hole. The second contact hole 76c is formed to pass through the passivation layer 68 and the gate insulating layer 62 to expose the gate pad 32. The third contact hole 76d is formed through the passivation layer 68 to expose the data pad 28. The through-hole 90 penetrates the passivation layer 68 and the gate insulating layer 62 and is formed between the data line 54 and the capacitance equivalent pattern 95. As the material of the protective film 68, an inorganic insulating material such as the gate insulating film 62, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

Referring to FIG. 7E, transparent electrode patterns are formed on the passivation layer 68.

The transparent electrode material is entirely deposited on the passivation layer 68 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through a photolithography process and an etching process using a fifth mask, thereby forming transparent electrode patterns such as the pixel electrode 72, the gate pad protection electrode 36, and the data pad protection electrode 30. Is formed. The pixel electrode 72 is in surface contact with the drain electrode 60 through the first contact hole 76a and in surface contact with the storage capacitor SP exposed through the first through hole 76b. The gate pad protection electrode 32 is in surface contact with the gate pad 32 through the second contact hole 76c, and the data pad protection electrode 30 is in contact with the data pad 28 through the third contact hole 76d. If you contact with. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the thin film transistor array substrate according to the first exemplary embodiment of the present invention is a storage on common method in which a storage capacitor SP is formed on the storage line 88. In this case, the storage line 88 may be formed to have a minimum distance from the front gate line 52 to reduce the aperture ratio loss as much as possible. In addition, by forming the first through hole 76b between the storage capacitor SP and the front gate line 52, the distance between the storage line 88 and the front gate line 52 may be reduced. Prevents residue residues. Here, the width W of the first through hole 76b is set to 2 μm or more so that the patterns of the storage line 88 and the front gate line 52 are not properly formed so that a defective pattern may be performed during the post process. The defective pattern is also removed during the protective film 68 batch etching process or the pixel electrode 72 etching process. That is, the thin film transistor array substrate and the manufacturing method according to the first embodiment of the present invention form a first through hole 76b so that the photoresist causing the sort failure as the storage line 88 is adjacent to the gate line 52. Self-Repair structure is adopted to remove the residue and bad pattern automatically during the process.

In addition, the thin film transistor array substrate and the manufacturing method according to the first embodiment of the present invention in the thin film transistor array substrate and manufacturing method employing the conventional on-gate method by forming a storage line 88 to charge the storage capacitor (SP). In comparison, the amount of charge accumulated in the gate line is reduced to reduce the resistance of the gate line. As a result, the thin film transistor array substrate and the manufacturing method according to the first embodiment of the present invention prevent the display line from being degraded by preventing the breakage of the gate line.

Furthermore, in the large area LCD employing the double bank driving method, the thin film transistor array substrate and the manufacturing method according to the first embodiment of the present invention form a storage line overlapping the storage electrode to form an image of the large area LCD. The capacitance of the gate line located at the boundary between the side and bottom surfaces is greatly reduced. Accordingly, the thin film transistor array substrate and the manufacturing method according to the first embodiment of the present invention improve the display quality of the large area LCD by preventing the signal delay of the interface between the upper side and the lower side in the large area LCD.

8 and 10 are a plan view and a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.

8 and 9, the thin film transistor array substrate according to the second embodiment of the present invention may include a gate line 52 formed on the lower substrate 51 and a storage line parallel to the gate line 52. 88, a data line 54 arranged to intersect the gate line 52 and the storage line 88 with the gate insulating film 62 therebetween, the thin film transistor TP formed at each intersection thereof, and the intersection thereof. The pixel electrode 72 formed in the cell region having the structure, the storage capacitor SP formed at an overlapping portion of the pixel electrode 72 and the storage line 88, the previous gate line 52 and the storage capacitor SP. A first through-hole 76b formed therebetween, a capacitance-equivalent pattern 95 extending from the storage electrode 74 of the storage capacitor SP and parallel to the data line 54, and a blackout Second through formed between the capacitive equivalent pattern 95 and the data line 54 Includes a (90).

The thin film transistor TP includes a gate electrode 56 connected to the gate line 52, a source electrode 58 connected to the data line 54, a drain electrode 60 connected to the pixel electrode 72, and And an active layer 64 overlapping the gate electrode 56 and forming a channel between the source electrode 58 and the drain electrode 60. The active layer 64 further includes a channel portion formed to overlap the data line 54, the source electrode 58, and the drain electrode 60, and formed between the source electrode 58 and the drain electrode 60. An ohmic contact layer 66 for ohmic contact with the data line 54, the source electrode 58, and the drain electrode 60 is further formed on the active layer 64. The thin film transistor TP keeps the pixel voltage signal supplied to the data line 54 charged in the pixel electrode 72 in response to the gate signal supplied to the gate line 52.

The pixel electrode 72 is connected to the drain electrode 60 of the thin film transistor TP through the first contact hole 76a passing through the passivation layer 68. The pixel electrode 72 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate is rotated by dielectric anisotropy and transmits light incident from the light source (not shown) via the pixel electrode 72 toward the upper substrate (not shown).

The gate line 52 is connected to a gate driver (not shown) through the gate pad part GP as shown in FIG. 1, and the data line 54 is connected to a data driver (not shown) through the data pad part DP. Not connected).

The gate pad portion GP may include the gate pad 32 connected to the gate line 52, the gate pad 32 through the second contact hole 76c penetrating through the passivation layer 68 and the gate insulating layer 62. It consists of the gate pad protection electrode 36 connected.

The data pad part DP includes a data pad 28 connected to the data line 54 and a data pad protection electrode connected to the data pad 28 through a third contact hole 76d passing through the passivation layer 68. It consists of 30.

The capacitance equivalent pattern 95 parallel to the data line 54 is connected to the pixel electrode 72 through the storage electrode 74 or integrated with the storage electrode 74 to be connected to the pixel electrode 72. The capacitive equivalent pattern 95 is formed of a source / drain metal on the same layer as the data line 54 and connected to the pixel electrode 72 so that a difference in distance between the pixel electrode 72 and the data line 54 is achieved. This prevents the parasitic capacitor capacity deviation caused by. Parasitic capacitor capacitance deviation causes distortion of the driving voltage of the data line 54, resulting in deterioration of image quality. The variation of the parasitic capacitor capacitance between the pixel electrode 72 and the data line 54 is caused by misalignment of the mask for forming the pattern of the data line 54 and the mask for forming the pattern of the pixel electrode 72. And the separation distance between the data lines 54 is different for each cell. The difference in separation distance between the pixel electrode 72 and the data line 54 is prevented by the capacitance equivalent pattern 95, thereby preventing occurrence of parasitic capacitor capacitance variation.

The second through hole 90 is formed between the capacitance equivalent pattern 95 and the data line 54. This may be performed during the batch etching process of the passivation layer 68 or the etching process of the pixel electrode 72 to eliminate the defective pattern of the capacitance equivalent pattern 95 and the data line 54. Here, the capacitance equivalent pattern 95 is designed to be formed in parallel with the data line 54 so that a failure of the source / drain pattern adjacent to the data line 54 or a failure of the semiconductor layer pattern occurs. The defect of the capacity | capacitance equivalent pattern 95 also arises. If a pattern failure of the capacitance equivalent pattern 95 and the data line 54 occurs, the sort failure occurs between the data line 54 and the drain electrode 60 to which the capacitance equivalent pattern 95 is connected. Such defects cause a decrease in display quality and a decrease in yield of the liquid crystal display. In order to prevent the occurrence of the failure of the capacitance equivalent pattern 95, the separation distance between the data lines 54 may be increased. There is a need for a way to repair defects. On the contrary, the second through hole 90 is formed between the capacitance equivalent pattern 95 and the data line 54 so that the second through hole 90 is sorted due to a pattern failure between the capacitance equivalent pattern 95 and the data line 54. The occurrence of defects is prevented.

The storage capacitor SP includes a storage line 88 and a storage electrode 74 positioned between the storage line 88 and the gate insulating layer 12 and connected to the pixel electrode 72. The storage capacitor SP keeps the data voltage applied to the pixel electrode 72 constant.

The first through hole 76b is formed between the storage line 88 and the front gate line 52. Accordingly, the first through hole 76b is left in the narrow gap between the front gate line 52 and the storage line 88, the residue of the photo-resist used during the photolithography process is left. Will be prevented. As a result, the first through hole 76b prevents a pattern defect caused by the residue of the photoresist remaining between the front gate line 52 and the storage line 88, and furthermore, unevenness of the liquid crystal display device due to the pattern defect. It is possible to prevent afterimages and sorting defects.

A method of manufacturing a thin film transistor substrate having such a configuration is shown in FIGS. 10A to 10E by a five mask process.

Referring to FIG. 10A, gate patterns are formed on the lower substrate 51.

The gate metal layer is formed on the lower substrate 51 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, thereby forming a gate including the gate line 52, the gate electrode 56, the gate pad 32, and the storage line 88. Patterns are formed. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 10B, a gate insulating layer 62, an active layer 64, and an ohmic contact layer 66 are formed on a lower substrate 51 on which gate patterns are formed.

The gate insulating layer 52, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower substrate 51 on which the gate patterns are formed through a deposition method such as plasma enhanced chemical vapor deposition (PECVD). Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously etched by the photolithography process and the etching process using the second mask to form the ohmic contact layer 56 and the active layer 54. As the material of the gate insulating film 62, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Referring to FIG. 10C, source / drain patterns are formed on the gate insulating layer 62 on which the active layer 64 and the ohmic contact layer 66 are formed.

A source / drain metal layer is formed on the gate insulating film 62 on which the active layer 64 and the ohmic contact layer 66 are formed by a deposition method such as sputtering. Subsequently, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask, so that the data line 54, the source electrode 58, the drain electrode 60, the storage electrode 74, and the capacitance are equivalent. Source / drain patterns including the pattern 95 and the data pad 28 are formed. The ohmic contact layer 66 between the source electrode 58 and the drain electrode 60 is removed by a dry etching process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), chromium (Cr), and the like are used.                     

Referring to FIG. 10D, a plurality of contact holes 76a, 26c, and 26d, a first through hole 76b, and a second through hole 90 are formed on a gate insulating layer 62 on which source / drain patterns are formed. The protective film 68 is formed.

The passivation layer 68 is entirely formed on the gate insulating layer 62 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 68 is patterned by a photolithography process using a fourth mask and a dry etching process to form contact holes 76a, 26c, and 26d, a first through hole 76b, and a second through hole 90. . The first contact hole 76a is formed through the passivation layer 68 to expose the drain electrode 60. The first through hole 76b is formed between the storage line 88 and the front gate line 52 through the passivation layer 68 and the gate insulating layer 62, and is formed to expose a portion of the storage electrode 74. . That is, the first through hole 76b is integrated with the storage contact hole. The second contact hole 76c is formed to pass through the passivation layer 68 and the gate insulating layer 62 to expose the gate pad 32. The third contact hole 76d is formed through the passivation layer 68 to expose the data pad 28. The through-hole 90 penetrates the passivation layer 68 and the gate insulating layer 62 and is formed between the data line 54 and the capacitance equivalent pattern 95. As the material of the protective film 68, an inorganic insulating material such as the gate insulating film 62, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

Referring to FIG. 10E, transparent electrode patterns are formed on the passivation layer 68.

The transparent electrode material is entirely deposited on the protective film 68 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through the photolithography process and the etching process using the fifth mask, so that the transparent electrode patterns such as the pixel electrode 72, the gate pad protection electrode 36, and the data pad protection electrode 30 are formed. Are formed. The pixel electrode 72 is in surface contact with the drain electrode 60 through the first contact hole 76a and in surface contact with the storage capacitor SP exposed through the first through hole 76b. The gate pad protection electrode 32 is in surface contact with the gate pad 32 through the second contact hole 76c, and the data pad protection electrode 30 is in contact with the data pad 28 through the third contact hole 76d. If you contact with. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the thin film transistor array substrate according to the second exemplary embodiment of the present invention has a storage on common method in which a storage capacitor SP is formed on the storage line 88. In this case, the storage line 88 may be formed to have a minimum distance from the front gate line 52 to reduce the aperture ratio loss as much as possible. In addition, by forming the first through hole 76b between the storage capacitor SP and the front gate line 52, the distance between the storage line 88 and the front gate line 52 may be reduced. Prevents residue residues. Here, the width W of the first through hole 76b is set to 2 μm or more so that the patterns of the storage line 88 and the front gate line 52 are not properly formed so that a defective pattern may be performed during the post process. The defective pattern is also removed during the protective film 68 batch etching process or the pixel electrode 72 etching process. That is, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention form a first through hole 76b so that the storage line 88 is adjacent to the gate line 52 to cause a sort defect. Self-repair structure is adopted in which the residue and defect pattern of the resist is automatically removed during the process.

In addition, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention to the thin film transistor array substrate and manufacturing method employing the conventional on-gate method by forming a storage line 88 to charge the storage capacitor (SP). In comparison, the amount of charge accumulated in the gate line is reduced to reduce the resistance of the gate line. As a result, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention prevent the display line from being degraded by preventing the breakage of the gate line.

In addition, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention by forming a second through hole 90 between the capacitance equivalent pattern 95 and the data line 54, the capacitance equivalent pattern The defective pattern 95 and the data line 54 are eliminated. As a result, the sorting defect that occurred between the data line 54 and the drain electrode 60 to which the capacitive equivalent pattern 95 is connected due to the defective pattern of the capacitance equivalent pattern 95 and the data line 54. Will be prevented.

Furthermore, in the large area LCD employing the double bank driving method, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention form a storage line overlapping the storage electrode to form an image of the large area LCD. The capacitance of the gate line located at the boundary between the side and bottom surfaces is greatly reduced. Accordingly, the thin film transistor array substrate and the manufacturing method according to the second embodiment of the present invention improve the display quality of the large area LCD by preventing the signal delay of the interface between the upper and lower surfaces in the large area LCD.

11 and 13 are a plan view and a cross-sectional view illustrating a thin film transistor array substrate according to a third embodiment of the present invention.

11 and 12, the thin film transistor array substrate according to the third embodiment of the present invention may include a gate line 52 formed on the lower substrate 51, and a storage line parallel to the gate line 52. 88, a data line 54 arranged to intersect the gate line 52 and the storage line 88 with the gate insulating film 62 therebetween, the thin film transistor TP formed at each intersection thereof, and the intersection thereof. The pixel electrode 72 formed in the cell region having the structure, the storage capacitor SP formed at an overlapping portion of the pixel electrode 72 and the storage line 88, the previous gate line 52 and the storage capacitor SP. A first through-hole 76b formed therebetween, a capacitance-equivalent pattern 95 extending from the storage electrode 74 of the storage capacitor SP and parallel to the data line 54, and a blackout Second through formed between the capacitive equivalent pattern 95 and the data line 54 Across the 90 and the gate insulating film 62 is provided with a redundancy pattern 91 is superimposed on the data line 54.

The thin film transistor TP includes a gate electrode 56 connected to the gate line 52, a source electrode 58 connected to the data line 54, a drain electrode 60 connected to the pixel electrode 72, and And an active layer 64 overlapping the gate electrode 56 and forming a channel between the source electrode 58 and the drain electrode 60. The active layer 64 further includes a channel portion formed to overlap the data line 54, the source electrode 58, and the drain electrode 60, and formed between the source electrode 58 and the drain electrode 60. An ohmic contact layer 66 for ohmic contact with the data line 54, the source electrode 58, and the drain electrode 60 is further formed on the active layer 64. The thin film transistor TP keeps the pixel voltage signal supplied to the data line 54 charged in the pixel electrode 72 in response to the gate signal supplied to the gate line 52.

The pixel electrode 72 is connected to the drain electrode 60 of the thin film transistor TP through the first contact hole 76a passing through the passivation layer 68. The pixel electrode 72 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate is rotated by dielectric anisotropy and transmits light incident from the light source (not shown) via the pixel electrode 72 toward the upper substrate (not shown).

The gate line 52 is connected to a gate driver (not shown) through the gate pad part GP as shown in FIG. 1, and the data line 54 is connected to a data driver (not shown) through the data pad part DP. Not connected).

The gate pad portion GP may include the gate pad 32 connected to the gate line 52, the gate pad 32 through the second contact hole 76c penetrating through the passivation layer 68 and the gate insulating layer 62. It consists of the gate pad protection electrode 36 connected.

The data pad part DP includes a data pad 28 connected to the data line 54 and a data pad protection electrode connected to the data pad 28 through a third contact hole 76d passing through the passivation layer 68. It consists of 30.                     

The capacitance equivalent pattern 95 parallel to the data line 54 is connected to the pixel electrode 72 through the storage electrode 74 or integrated with the storage electrode 74 to be connected to the pixel electrode 72. The capacitive equivalent pattern 95 is formed of a source / drain metal on the same layer as the data line 54 and connected to the pixel electrode 72 so that a difference in distance between the pixel electrode 72 and the data line 54 is achieved. This prevents the parasitic capacitor capacity deviation caused by. Parasitic capacitor capacitance variation distorts the driving voltage of the data line 54, resulting in deterioration of image quality. The variation of the parasitic capacitor capacitance between the pixel electrode 72 and the data line 54 is caused by misalignment of the mask for forming the pattern of the data line 54 and the mask for forming the pattern of the pixel electrode 72. And the separation distance between the data lines 54 is different for each cell. The difference in separation distance between the pixel electrode 72 and the data line 54 is prevented by the capacitance equivalent pattern 95, thereby preventing occurrence of parasitic capacitor capacitance variation.

The second through hole 90 is formed between the capacitance equivalent pattern 95 and the data line 54. This may be performed during the batch etching process of the passivation layer 68 or the etching process of the pixel electrode 72 to eliminate the defective pattern of the capacitance equivalent pattern 95 and the data line 54. Here, the capacitance equivalent pattern 95 is designed to be formed in parallel with the data line 54 so that a failure of the source / drain pattern adjacent to the data line 54 or a failure of the semiconductor layer pattern occurs. The defect of the capacity | capacitance equivalent pattern 95 also arises. When the pattern failure of the capacitance equivalent pattern 95 and the data line 54 occurs, the sort failure occurs between the drain line 60 to which the data line 54 and the capacitance equivalent pattern 95 are connected. Such defects cause a decrease in display quality and a decrease in yield of the liquid crystal display. In order to prevent the occurrence of the failure of the capacitance equivalent pattern 95, the separation distance between the data lines 54 may be increased. There is a need for a way to repair defects. On the contrary, the second through hole 90 is formed between the capacitance equivalent pattern 95 and the data line 54 so that the second through hole 90 is sorted due to a pattern failure between the capacitance equivalent pattern 95 and the data line 54. The occurrence of defects is prevented.

The redundancy pattern 91 is a gate pattern formed of a gate metal and is formed below the data line 54 so that when the pattern of the data line 54 is poor, the redundancy pattern 91 is between the redundancy pattern 91 which is a gate pattern. By removing the gate insulating layer 62 of the laser, a data signal may be applied to the pixel electrode 72 along the data line 54. As such, the redundancy pattern 91 repairs local pixel defects of the liquid crystal display device caused by the local pattern defect of the data line 54.

The storage capacitor SP includes a storage line 88 and a storage electrode 74 positioned between the storage line 88 and the gate insulating layer 12 and connected to the pixel electrode 72. The storage capacitor SP keeps the data voltage applied to the pixel electrode 72 constant.

The first through hole 76b is formed between the storage line 88 and the front gate line 52. Accordingly, the first through hole 76b is left in the narrow gap between the front gate line 52 and the storage line 88, the residue of the photo-resist used during the photolithography process is left. Will be prevented. As a result, the first through hole 76b prevents a pattern defect caused by the residue of the photoresist remaining between the front gate line 52 and the storage line 88, and furthermore, unevenness of the liquid crystal display device due to the pattern defect. It is possible to prevent afterimages and sorting defects.

A method of manufacturing a thin film transistor substrate having such a configuration is shown in FIGS. 13A to 13E by a five mask process.

Referring to FIG. 13A, gate patterns are formed on the lower substrate 51.

The gate metal layer is formed on the lower substrate 51 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using the first mask, thereby forming the gate line 52, the gate electrode 56, the gate pad 32, the storage line 88, and the redundancy pattern ( Gate patterns including 91 are formed. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 13B, a gate insulating layer 62, an active layer 64, and an ohmic contact layer 66 are formed on the lower substrate 51 on which the gate patterns are formed.

The gate insulating layer 52, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower substrate 51 on which the gate patterns are formed through a deposition method such as plasma enhanced chemical vapor deposition (PECVD). Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously etched by the photolithography process and the etching process using the second mask to form the ohmic contact layer 56 and the active layer 54. As the material of the gate insulating film 62, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Referring to FIG. 13C, source / drain patterns are formed on the gate insulating layer 62 on which the active layer 64 and the ohmic contact layer 66 are formed.

A source / drain metal layer is formed on the gate insulating film 62 on which the active layer 64 and the ohmic contact layer 66 are formed by a deposition method such as sputtering. Subsequently, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask, so that the data line 54, the source electrode 58, the drain electrode 60, the storage electrode 74, and the capacitance are equivalent. Source / drain patterns including the pattern 95 and the data pad 28 are formed. The ohmic contact layer 66 between the source electrode 58 and the drain electrode 60 is removed by a dry etching process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), chromium (Cr), and the like are used.

Referring to FIG. 13D, a plurality of contact holes 76a, 26c, and 26d, a first through hole 76b, and a second through hole 90 are formed on a gate insulating layer 62 on which source / drain patterns are formed. The protective film 68 is formed.

The passivation layer 68 is entirely formed on the gate insulating layer 62 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 68 is patterned by a photolithography process using a fourth mask and a dry etching process to form contact holes 76a, 26c, and 26d, a first through hole 76b, and a second through hole 90. . The first contact hole 76a is formed through the passivation layer 68 to expose the drain electrode 60. The first through hole 76b is formed between the storage line 88 and the front gate line 52 through the passivation layer 68 and the gate insulating layer 62, and is formed to expose a portion of the storage electrode 74. . That is, the first through hole 76b is integrated with the storage contact hole. The second contact hole 76c is formed to pass through the passivation layer 68 and the gate insulating layer 62 to expose the gate pad 32. The third contact hole 76d is formed through the passivation layer 68 to expose the data pad 28. The through-hole 90 penetrates the passivation layer 68 and the gate insulating layer 62 and is formed between the data line 54 and the capacitance equivalent pattern 95. As the material of the protective film 68, an inorganic insulating material such as the gate insulating film 62, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

Referring to FIG. 13E, transparent electrode patterns are formed on the passivation layer 68.

The transparent electrode material is entirely deposited on the protective film 68 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through a photolithography process and an etching process using a fifth mask, thereby forming transparent electrode patterns such as the pixel electrode 72, the gate pad protection electrode 36, and the data pad protection electrode 30. Is formed. The pixel electrode 72 is in surface contact with the drain electrode 60 through the first contact hole 76a and in surface contact with the storage capacitor SP exposed through the first through hole 76b. The gate pad protection electrode 32 is in surface contact with the gate pad 32 through the second contact hole 76c, and the data pad protection electrode 30 is in contact with the data pad 28 through the third contact hole 76d. If you contact with. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the thin film transistor array substrate according to the third exemplary embodiment of the present invention is a storage on common method in which a storage capacitor SP is formed on the storage line 88. In this case, the storage line 88 may be formed to have a minimum distance from the front gate line 52 to reduce the aperture ratio loss as much as possible. In addition, by forming the first through hole 76b between the storage capacitor SP and the front gate line 52, the distance between the storage line 88 and the front gate line 52 may be reduced. Prevents residue residues. Here, the width W of the first through hole 76b is set to 2 μm or more so that the patterns of the storage line 88 and the front gate line 52 are not properly formed so that a defective pattern may be performed during the post process. The defective pattern is also removed during the protective film 68 batch etching process or the pixel electrode 72 etching process. That is, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention form a first through hole 76b so that the photoresist causing the sort failure as the storage line 88 is adjacent to the gate line 52. Self-Repair structure is adopted to remove the residue and bad pattern automatically during the process.

In addition, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention in the thin film transistor array substrate and manufacturing method employing the conventional on-gate method by forming a storage line 88 to charge the storage capacitor (SP). In comparison, the amount of charge accumulated in the gate line is reduced to reduce the resistance of the gate line. As a result, the thin film transistor array substrate and the manufacturing method according to the third exemplary embodiment of the present invention prevent the display line from being degraded by preventing the breakage of the gate line.

In addition, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention by forming a second through-hole 90 between the capacitance equivalent pattern 95 and the data line 54, the capacitance equivalent pattern The defective pattern 95 and the data line 54 are eliminated. As a result, the sorting defect that occurred between the data line 54 and the drain electrode 60 to which the capacitive equivalent pattern 95 is connected due to the defective pattern of the capacitance equivalent pattern 95 and the data line 54. Will be prevented.

In addition, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention form a redundancy pattern 91, which is a gate pattern, on the lower layer of the data line 54, resulting in a pattern defect of the data line 54 during the inspection process. Even if a local pixel defect of the liquid crystal display device is found, when the gate insulating layer 62 is removed by using a laser, the data line 54 is connected to the redundancy pattern 91 formed at the lower layer so that the data signal is applied to the data line 54. To be authorized. That is, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention have the advantage that the data line 54 can be repaired. Accordingly, the manufacturing yield of the liquid crystal display device can be improved by repairing the pattern defect of the data line 54.

Furthermore, in the large area LCD employing the double bank driving method, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention form a storage line overlapping the storage electrode to form an image of the large area LCD. The capacitance of the gate line located at the radial interface between the side and bottom surfaces is greatly reduced. Accordingly, the thin film transistor array substrate and the manufacturing method according to the third embodiment of the present invention improve the display quality of the large area LCD by preventing the signal delay of the interface between the upper and lower surfaces in the large area LCD.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the embodiment of the present invention form a storage capacitor formed on the gate line on the storage line to separate the storage capacitor from the gate line to reduce the load amount of the gate line. By reducing it, it is possible to prevent deterioration in image quality due to an increase in the load amount of the gate line.

In addition, the liquid crystal display device employing the thin film transistor array substrate according to the embodiment of the present invention can prevent a short defect between two lines by forming a through hole between the gate line and the storage line.

Furthermore, the liquid crystal display device employing the thin film transistor array substrate according to the embodiment of the present invention has a second through hole between the capacitance equivalent pattern and the data line, thereby preventing short defects between the data line and the capacitance equivalent pattern. It can prevent occurrence.

Furthermore, a liquid crystal display device employing a thin film transistor array substrate according to an embodiment of the present invention includes a redundancy pattern, which is a gate pattern overlapping a data line with a gate insulating layer interposed therebetween, so that even if a pattern defect of a data line is found during an inspection process, It is possible to repair the data line using a laser. Therefore, it is possible to prevent the defective pattern of the data line to improve the manufacturing yield.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A gate line supplied with a gate voltage, A storage line adjacent to the gate line and parallel to the gate line; A data line crossing the gate line and the storage line with a gate insulating layer interposed therebetween; A thin film transistor connected to an intersection of the gate line and the data line; A pixel electrode positioned in a cell region formed at the intersection of the gate line and the data line and penetrating the passivation layer to be connected to the thin film transistor; A storage capacitor formed at an overlapping portion of the storage line and the pixel electrode, the storage capacitor including a storage electrode connected to the storage line and the pixel electrode; A capacitance equivalent pattern overlapping a portion of the pixel electrode and parallel to the data line and integrated with the storage electrode; A first through hole formed between the storage line and the gate line to prevent residue of photoresist used during the process by passing through a gate insulating film and the protective film; And And a second through hole formed between the capacitance equivalent pattern and the data line to prevent residue of photoresist used in the process by penetrating the gate insulating film and the protective film. Board. The method of claim 1, The first through hole, And the passivation layer and the gate insulating layer. delete The method of claim 1, The first through hole, And a contact hole for connecting the storage electrode and the pixel electrode to each other. delete The method of claim 1, The first through hole has a width of at least 2㎛ thin film transistor array substrate. delete The method of claim 1, And a redundancy pattern overlapping the data line with the gate insulating layer interposed therebetween. A gate line, a storage line adjacent to and parallel to the gate line, a data line intersecting the gate line and the storage line with a gate insulating film interposed therebetween, and a thin film transistor positioned at an intersection of the two lines. 1 step to form, Forming a passivation layer on the entire surface of the substrate and patterning the contact hole between the contact hole, the gate line, and the storage line to be integrated with the first through hole and the first through hole, and to connect the storage electrode and the pixel electrode; Forming a second through hole between the data line and a capacitance equivalent pattern integrated with the storage electrode; And forming a pixel electrode connected to the thin film transistor through the contact hole. The method of claim 9, The first step is, Forming a gate pattern on the substrate, the gate pattern including a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a storage line adjacent to and parallel to the gate line; Forming an entire gate insulating film to cover the gate pattern; Forming a semiconductor layer of the thin film transistor on the gate insulating layer; And forming a source / drain pattern including the data line, the source electrode and the drain electrode of the thin film transistor on the gate insulating layer on which the semiconductor layer is formed. The method of claim 10, Forming the source / drain pattern, And forming the storage electrode overlapping the storage line and connected to the pixel electrode. delete The method of claim 11, Forming the source / drain pattern, And forming the capacitive equivalent pattern overlapping a portion of the pixel electrode and parallel to the data line and integrated with the storage electrode. The method of claim 9, The first through hole, And a passivation layer formed through the passivation layer and the gate insulating layer. The method of claim 9, A method of manufacturing a thin film transistor array substrate, wherein the width of the first through hole is at least 2 μm. delete The method of claim 9, Forming the gate pattern, And forming a redundancy pattern to overlap the data line with the gate insulating layer interposed therebetween.

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