KR100859509B1 - a thin film transistor array panel - Google Patents

Abstract

Gate lines are formed in the horizontal direction on the insulating substrate, storage capacitor lines and storage electrodes are formed, and data lines insulated from and intersecting the gate lines and storage capacitor lines are formed in the vertical direction. A thin film transistor connected to the data line and the gate line is formed, and a pixel electrode is connected to the thin film transistor. On the same layer as the pixel electrode, a bridge connecting the storage capacitor line positioned on both sides of the gate line and the storage electrode is formed. At this time, the storage capacitor wiring including the storage capacitor line has a dummy wiring formed at the edge of the pixel in the column direction or the row direction in the same wiring structure as the other pixels. In this way, a display device is formed by adding dummy wiring adjacent to a gate line or a data line that transmits a scan signal or an image signal to a pixel positioned at the edge of the pixel, similarly to other pixels, to form driving conditions for the edge pixel and another pixel in the same manner. The display characteristics of can be ensured uniformly.

Thin film transistor, dummy wiring, drive, maintenance capacitance wiring

Description

Thin film transistor array panel

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 2 is an enlarged view of region II of FIG. 1;

3 is a cross-sectional view taken along line III-III 'of FIG. 2,

4 is a layout view of a thin film transistor array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

The present invention relates to a thin film transistor substrate.

In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates on which an electrode is formed, and a light transmission amount is controlled by adjusting the intensity of a voltage applied to the electrode.

The liquid crystal display has pixels in a matrix arrangement, each pixel is arranged in a matrix form, and each pixel is electrically connected to a signal line through a thin film transistor and a thin film transistor connected to a gate line and a data line. It is formed in the electrode. Each pixel includes a liquid crystal capacitor having a common electrode facing the pixel electrode on one end thereof with a pixel electrode and a sustain electrode facing the pixel electrode on the other end with an insulating layer on the other end thereof. Has a holding capacitor.

Here, the thin film transistor substrate is used as a circuit board for driving each pixel independently, and the thin film transistor substrate defines a pixel area crossing the scan signal line or the gate line for transmitting the scan signal and the image signal line for transferring the image signal. Alternatively, a data line is formed, and a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like are formed. The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode and a drain electrode connected to the data line, a gate insulating layer, and the like, and the data line according to a scan signal transmitted through the gate line. A switching device that transfers or blocks an image signal transmitted through the pixel electrode.

In such a liquid crystal display, each pixel is driven by controlling an image signal transmitted to a pixel electrode through a data line through a thin film transistor to display an image.

At this time, practically, each pixel, as well as the liquid crystal capacitor and the storage capacitor, adjacent wires or electrodes are made of a parasitic capacitor through an insulating film, and when driven, a coupling capacitance is generated, which affects an electric field exerting liquid crystal molecules. Crazy                         

However, the wiring structure of the pixel disposed at the edge of the display area where the image is displayed is different from the wiring structure of other pixels, so that the driving conditions of the edge pixels have characteristics different from those of the other pixels. This may cause non-uniformity of the entire display panel, which causes product defects.

An object of the present invention is to provide a thin film transistor array substrate capable of ensuring uniform display characteristics.

In order to solve this problem, in the present invention, the dummy wiring is formed adjacent to the gate line and the data line so that the pixel at the edge thereof has a wiring structure similarly to other pixels.

Specifically, in the thin film transistor array substrate according to the present invention, a first signal line and a second signal line which are insulated from each other and cross each other are formed on a transparent insulating substrate, and a plurality of branches connected to the main line and the main line which are insulated from and cross the second signal line. Signal wirings having lines are formed. A thin film transistor having the same structure as that of the signal wiring line is formed in parallel with the first or second signal line which transmits the signal to the pixel located at the edge, and the thin film transistor connected to the first signal line and the second signal line; The pixel electrode connected to the thin film transistor is formed on the transparent insulating substrate.

In this case, the first signal line is a gate line including a gate line extending in the horizontal direction and a gate electrode connected to the gate line, and the second signal line is connected to the data line and the data line formed in the vertical direction and at least partially It is preferable that it is a data wiring including a source electrode positioned on the semiconductor layer of the thin film transistor, a counter electrode of the source electrode, and at least part of which is a drain electrode positioned on the semiconductor layer of the thin film transistor.

Further, the signal wiring is a storage capacitor wiring which is a branch of the storage capacitor line and the storage capacitor line parallel to the gate line and includes a storage electrode extending in the vertical direction, and the dummy wiring is parallel to the gate line and may be formed in the same manner as the storage paper capacitance line or Side by side may be formed in the same manner as the sustain electrode.

Next, the thin film transistor array substrate according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the present invention.

In the embodiment of the present invention, the pixel located at the edge of the display area where the image is displayed also has dummy wiring adjacent to the gate line and the data line so as to have a wiring structure like other pixels, and in the drawing, the wiring of the pixel located at the edge The structure is shown.

FIG. 1 is a layout view illustrating a wiring structure of a thin film transistor array substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 2 is an enlarged view of region II in FIG. 1, and FIG. 3 is III of FIG. 2. It is sectional drawing about the -III line.

1 to 3, in the thin film transistor array substrate for a liquid crystal display according to the first embodiment of the present invention, the gate wirings 20 and 21 and the storage capacitors are disposed on a transparent insulating substrate 10 such as glass. Wirings 30, 31, 32, 33, 34, 35, and 36 are formed.

The gate lines 20 and 21 include gate lines 20 extending in the horizontal direction, and a portion of the gate lines 20 protrude upward and downward to form the gate electrode 21.

The storage capacitor wirings 30, 31, 31 ′, 32, 33, 34, 35, and 36 have the storage capacitor line 30 parallel to the gate line 20 and the first to fifth storage electrodes 31 and 32 that are branches thereof. , 33, 34, 35). One end of the first storage electrode 31 positioned at the edge of the pixel region extends in the vertical direction by being directly connected to the storage capacitor line 30, and the second storage electrode 32 is the other end of the first storage electrode 31. It is connected in the form of protrusions. The third storage electrode 33 is positioned at an opposite edge of the first storage electrode 31 with respect to the pixel area and extends in the vertical direction, and the first storage electrode 31 of the neighboring pixel area is formed through the storage electrode connection part 36. It is also connected to. The fourth storage electrode 34 and the fifth storage electrode 35 connect the first storage electrode 31 and the third storage electrode 33 in an oblique direction, respectively, and the fourth storage electrode 34 is the pixel region. From the lower left to the center of the left, the fifth storage electrode 35 extends from the right to the left center, so that the two storage electrodes 34 and 35 converge on the left center. These 34 and 35 are formed in the diagonal direction with respect to the 1st storage electrode 31, and the extension line of the 4th storage electrode 34 and the 5th storage electrode 35 forms the angle of about 90 degrees. In addition, the storage capacitor wiring is formed adjacent to the data line 70 which transmits an image signal to the pixel P _{m in} the column direction positioned at the edge of the display area, and has a shape similar to that of the first storage electrode 31. One end thereof is directly connected to the storage capacitor line 30, and includes a dummy wiring 31 ′ extending in the vertical direction. As in the present invention, a dummy wiring 31 ′ connected to the storage capacitor line 3 of the pixel P _{m in} the last column direction of the display area and to which the storage capacitor voltage is transmitted is formed adjacent to the data line 70. Since the driving conditions of the pixels P _{m in the} last column direction are also the same as the driving conditions of other pixels in the display area, display characteristics of the display device may be uniformly secured, thereby minimizing product defects. In addition, the dummy wire 31 ′ may be used as a repair line when the data line 70 transferring the image signal to the pixel P _m in the last column direction is disconnected. That is, when the data line 70 of the pixel P _{m in} the last column direction is disconnected, the data line 70 and the storage capacitor line 30 overlap each other at the upper and lower portions of the disconnected portion to short-circuit the data line ( The image signal transmitted through 70 is bypassed to the dummy wiring 31 ′, and the portion including the dummy wiring 31 ′ and used as a repair line to prevent the interference of the signal is provided in the storage capacitor wiring 30, 31, and the like. 31 ', 32, 33, 34, 35, 36).

The gate wirings 20 and 21 and the storage capacitor wirings 30, 31, 31 ′, 32, 33, 34, 35, and 36 are covered with a gate insulating film 40, and a semiconductor made of amorphous silicon on the gate insulating film 40. Layers 50 and 51 are formed. The semiconductor layers 50 and 51 extend in the longitudinal direction and extend in the vertical direction near the gate electrode 21 and the vertical portion 50 passing through the storage electrode connection portion 36 and overlap the gate electrode 21. And 51. On the semiconductor layers 50 and 51, ohmic contacts 60, 61 and 62 made of amorphous silicon doped at high concentration with N-type impurities such as phosphorus are formed.

Data wires 70, 71, 72, and 74 are formed on the contact layers 60, 61, 62, and the gate insulating film 40. The data line includes a data line 70 extending along the vertical portion 50 of the semiconductor layer, a source electrode 71 connected thereto, and a drain electrode 72 separated from the data line 70. The source electrode 71 protrudes in a U shape from the data line 70 in the vicinity of the gate electrode 21, and one end of the drain electrode 72 extends toward the center of the U-shaped portion of the source electrode 71. The end extends into the pixel area. The data line further includes a data metal piece 74 positioned on the gate line 20 adjacent to the second storage electrode 32. Here, the ohmic contacts 60, 61, and 62 are formed only at the portion where the semiconductor layers 50, 51 and the data lines 70, 71, 72, and 74 overlap.

The passivation film 80 is formed on the data wirings 70, 71, 72, and 74. At this time, the protective film 80 has a first contact hole 81 exposing one end of the drain electrode 72 and a second contact hole 82 exposing the data metal piece 74. The second insulating electrode 32 and the third and fourth contact holes 83 and 84 exposing a part of the storage capacitor line 30 respectively positioned above and below the 82 are provided together with the gate insulating film 40. .

On the passivation layer 80, the pixel electrode 90 is connected to the drain electrode 72 through the first contact hole 81, and the data metal piece 74 is connected through the second contact hole 82. A leg 91 connected to the second storage electrode 32 and the storage wiring 84 through the third and fourth contact holes 83 and 84 is formed. The pixel electrode 90 and the leg 91 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 90 has first to third openings 92, 93, and 94. The first and second openings 92 and 93 overlap with the fourth and fifth sustain electrodes 34 and 35, respectively. The third opening portion 94 is formed between the first opening portion 92 and the second opening portion 93. The third opening portion 94 extends from the right side of the pixel electrode 90 toward the left side thereof, and the entrance thereof is chamfered. On the other hand, it is common that the potential of the common electrode opposite to the pixel electrode 90 is applied to the storage capacitor wirings 30, 31, 31 ', 32, 33, 34, 35, 36.

On the other hand, the first storage electrode 31 and the storage capacitor line 30 are each formed with a mark in the form of a projection. These marks indicate where to irradiate a laser when repairing wiring defects. The portion where the mark is formed is adjacent to the pixel electrode 90 or the leg 91, so that if the laser irradiation position is only slightly off, the pixel electrode 90 or the leg 91 may be damaged or the pixel electrode 90 or the leg 91 may be damaged. It is a part which may short-circuit the leg 91 with other wiring. In addition, a mark is formed at a portion that does not have a feature that can be distinguished from other portions of the surrounding by having an unusual shape or intersecting with other surrounding opaque patterns. In this embodiment, the part with a mark is a part which will be irradiated and cut | disconnected when repairing wiring. The size of the cover is the width of the cross-sectional area of the laser beam to be irradiated (3 μm × 3 μm) and the interlayer margin, that is, the overlap width of each layer pattern, which may vary due to the misalignment of the optical masks in forming each layer. Taking into account 2.5 to 3 μm), the length (the holding capacitive or the first sustaining electrode in the longitudinal direction) is 4 μm to 5 μm, and the width (the holding capacitive or the first sustaining electrode in the width direction) is 0.5 μm to 1.5 It is preferably micrometers, and was formed in the first embodiment of the present invention at a length of 4.5 m and a width of 1 m.

In the first embodiment of the present invention, the dummy wiring is formed only in parallel with the data line, but the dummy wiring may be formed in parallel with the gate line, which will be described in detail with reference to the accompanying drawings.

4 is a layout view of a thin film transistor array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

The thin film transistor array substrate according to the second embodiment has almost the same wiring structure as the thin film transistor array substrate according to the first embodiment.

However, the storage capacitor wiring is formed adjacent to the gate line 20 that transmits the scan signal to the pixel P _{n in} the row direction positioned at the edge of the display area, and has a shape similar to that of the storage capacitor line 30. The dummy wire 30 ′ extends in the horizontal direction parallel to the gate line 20. Of course, the dummy wiring 30 ′ is electrically connected to the storage capacitor line 30 to transmit the storage voltage. As in the present invention, the dummy line 30 ′ connected to the storage capacitor line 30 of the pixel P _{n in} the row direction positioned at the edge of the display area, to which the storage capacitor voltage is transmitted, is the gate line 20. It is formed adjacent to the driving conditions of the pixel P _{n in the} last row direction is also the same as the driving conditions of the other pixels in the display area to ensure the display characteristics of the display device uniformly to minimize the defect of the product have. Here, the dummy wiring 30 'can also be used as a repair line when the gate line 20 for transmitting the scan signal to the pixel P _n in the last row direction is disconnected. That is, when the gate line 20 of the pixel P _{n in} the last row direction is disconnected, the gate line 20 and the bridge 91 overlap each other at the left and right sides of the disconnected portion to short-circuit the gate line 20. Bypass the scan signal transmitted through the dummy wiring (30 '), and the portion used as a repair line to prevent the interference of the signal storage capacitor wiring (30, 31, 31', 32, 33, 34, 35, 36).

Although the invention has been described with reference to the most practical and preferred embodiments, the invention is not limited to the embodiments described above, but also includes various modifications and equivalents within the scope of the following claims.

As described above, according to the present invention, since the dummy wiring is formed only outside the pixel located at the edge, the driving condition of the pixel located at the edge becomes the same as the driving condition of the other pixel not located at the edge. Since it can be secured uniformly, the defect of the product can be minimized.

Claims (9)

Transparent insulation substrate, A plurality of first signal lines formed on the insulating substrate, A plurality of second signal lines insulated from and intersecting the first signal line to define a display area including a plurality of pixel areas; A sustain electrode line having a main line insulated from and intersecting the second signal line and a plurality of branch lines connected to the main line; A dummy wiring positioned outside the display area and parallel to the first or second signal line and formed in the same structure as the storage electrode line and electrically connected to the storage electrode line; A thin film transistor connected to the first signal line and the second signal line, A pixel electrode connected to the thin film transistor and overlapping the storage electrode line to form a storage capacitor Thin film transistor array substrate comprising a. In claim 1, And the first signal line is a gate line including a gate line extending in a horizontal direction and a gate electrode connected to the gate line. In claim 2, The second signal line is a data line formed in a vertical direction, a source electrode connected to the data line and at least a portion of which is positioned on a semiconductor layer of the thin film transistor, an opposite electrode of the source electrode, and at least a portion of the semiconductor of the thin film transistor. A thin film transistor array substrate, which is a data line including a drain electrode positioned on a layer. delete In claim 3, The dummy wiring line is parallel to the gate line. In claim 3, The dummy wiring line is parallel to the data line. delete In claim 5,  And the dummy wire and the storage electrode line are connected by a bridge crossing the gate line. In claim 1, And the sustain electrode line has a mark indicating a point at which the laser is irradiated to repair a defect of the first signal line or the second signal line.

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