KR20060084147A - Thin film transistor substate - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a display device. The thin film transistor substrate according to the present invention comprises: a signal line defining a display area; A signal line fan out part connected to the signal line at an outer side of the display area, the signal line fan out part including a plurality of fan outs extending from the center to the outer part of the display area; And an overlapping electrode overlapping the signal line fan-out part and having an overlapping area extending from the outer portion toward the center portion. As a result, a thin film transistor substrate capable of compensating for the RC delay of the signal line fanout part is provided.

Description

Thin Film Transistor Boards {THIN FILM TRANSISTOR SUBSTATE}

1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention;

2 is a cross-sectional view taken along II-II of FIG. 1;

3 is a cross-sectional view for explaining a second embodiment of the present invention;

4 is an enlarged view of a signal line fan out part according to a third exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11 gate line 13 gate fan out portion

15: gate fanout 21: data line

23: data fan out section 25: data fan out section

30: gate overlap electrode 40: data overlap electrode

53: gate driving circuit 63: data driving circuit

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate including a fanout portion of a gator line and a data line.

A thin film transistor (TFT) substrate is used as a circuit board for driving each pixel independently in a liquid crystal display (LCD) or an organic light emitting diode (OLED) display, and the thin film transistor substrate is scanned. Scanning signal wirings or gate wirings for transmitting signals and image signal lines or data wirings for transmitting image signals. The substrate is provided with a thin film transistor connected to the gate wiring and a data wiring, a pixel electrode connected to the thin film transistor, a gate insulating film covering and insulating the gate wiring, and a protective film covering and insulating the thin film transistor and the data wiring. Here, the gate insulating film and the protective film are usually made of silicon nitride.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel portion which are part of a gate wiring, a source electrode and a drain electrode which are part of a data wiring, a gate insulating film and a protective film. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

A driving circuit for applying a driving signal to a gate line and a data line is connected to the thin film transistor substrate. The driving circuit is connected to the gate line or the data line through the pad, and the pad is densely formed in a narrow area for connection with the driving circuit. On the other hand, since the line spacing between the gate lines and the data lines positioned in the display area should have a width determined according to the pixel size, the spacing between the gate lines and the data lines is larger than that between the pads. Accordingly, there is a fanout portion between the pad portion and the display area in which the line spacing of the wiring gradually increases. These fan-out parts cause wires to be different in length, and therefore, RC delays vary from wire to wire. RC delay causes a variation in kickback voltage in the pixel, which causes a difference in luminance of the pixel, thereby degrading image quality.

Accordingly, an object of the present invention is to provide a thin film transistor substrate capable of compensating for the RC delay of the gate fanout part and the data fanout part.

The object is, according to the present invention, a signal line defining a display area; A signal line fan out part connected to the signal line at an outer side of the display area, the signal line fan out part including a plurality of fan outs extending from the center to the outer part of the display area; The overlapping area of the signal line fan-out part is achieved by including an overlapping electrode, the overlapping area of which extends from the outer portion toward the center portion.

The product of the resistance occurring at each fanout and the capacitance between each fanout and the overlap electrode is preferably constant, thereby compensating for the RC delay occurring at the fanout.

The signal line may include a gate line and a data line crossing the gate line, and a portion of the overlap electrode may be formed of the same layer as the gate line.

In addition, a part of the overlap electrode may be formed of the same layer as the data line.

The pixel electrode may further include a pixel electrode electrically connected to the data line, and the overlap electrode may be formed on the same layer as the pixel electrode.

In this case, the overlap electrode is characterized in that it comprises an ITO or IZO material.

At least a portion of the fanout is formed in a zigzag pattern, and the extension length of the zigzag pattern is preferably formed longer from the outer portion to the center, thereby adjusting the resistance of the fanout.

A driving circuit for driving the signal line; The apparatus may further include an electrode wiring connecting the driving circuit and the overlap electrode.

The driving circuit may include a gate driving circuit and a data driving circuit, and the electrode wiring may be configured to connect the overlapping electrode overlapping the gate driving circuit and the gate line and the overlapping electrode overlapping the data driving circuit and the data line. It features.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention.

As shown, the thin film transistor substrate 1 includes a display area 100 defined by a signal line such as a gate line 11 and a data line 21 intersecting the thin film transistor substrate 1. The gate driving circuit 53 and the data circuit 63 for driving the gate line 11 and the data line 21 are shown.

The gate driving circuit 53 and the data driving circuit 63 are electrically connected to the thin film transistor substrate 1. As a method of connecting the gate driving circuit 53 and the data driving circuit 63, a driving part is directly mounted on a thin film transistor substrate, a chip on glass (COG), and a TCP (tape carrier) in which a driving circuit is mounted on a polymer film. package) and a chip on film (COF) for mounting and attaching a driving unit on a driving circuit board. The gate driving circuit 53 and the data driving circuit 63 of this embodiment are connected to the gate COF 50 and the data COF 60 which are attached to the outside of the thin film transistor substrate 1.

The gate line 11 and the data line 21 in the display area 100 extend to the outer region so that the gate driving circuit may be driven through a gate pad (not shown) and a data pad (not shown) positioned at the end of the thin film transistor substrate 1. It is connected to the furnace 53 and the data driving circuit 63. In the connected portion, the gate fanout part 13 in which the wiring interval of the gate line 11 extending from the display area 100 becomes narrower and the data fanout part 23 in which the wiring interval of the data line 21 becomes narrower. ) Is formed. The gate fanout part 13 and the data fanout part 23 include a gate overlap electrode 30 and a data overlap electrode 40 overlapping the gate fanout part 13 and the data fanout part 23. . Hereinafter, the term signal line will be used for common components corresponding to the gate line and the data line.

The signal line fanout parts 13 and 23 have an outer portion having a long signal line and a central portion having a short length of the signal line, and gate fan out a plurality of gate lines and data lines constituting the signal line fanout parts 13 and 23. (15) and data fanout (25). The lengths of the signal line fanouts 15 and 25 become longer from the center to the outer portion thereof, and are arranged closer to the display area 100, so that the spacing of the signal line fanouts 15 and 25 becomes wider.

The signal line fanout parts 13 and 23 overlap the triangular signal line overlap electrodes 30 and 40. The signal line overlap electrodes 30 and 40 include a gate overlap electrode 30 overlapping with the gate fanout part 13 and a data overlap electrode 40 overlapping with the data fanout part 23. The area overlapping with the signal line fan-out parts 13 and 23 of the signal line overlap electrodes 30 and 40 becomes wider from the outer portion toward the center portion. Specifically, the lengths of the signal line fanouts 15 and 25 overlapping the signal line overlap electrodes 30 and 40 are long at the centers of the fanout parts 13 and 23, and the signal line fanouts 15 and 25 are relatively long at the outer portions. ) And overlap length is short. This is because the capacitance between the signal line overlap electrodes 30 and 40 and the signal line fanouts 15 and 25 is large at the center, and the capacitance between the signal line overlap electrodes 30 and 40 and the signal line fanouts 15 and 25 is relatively large at the outer portion. It means to write down.

Meanwhile, as described above, the lengths of the signal line fanouts 15 and 25 become longer from the center of the signal line fanouts 13 and 23 to the outer portion, so that the resistance generated in each of the fanouts 15 and 25 is the outer portion of the center. It gets bigger as it gets richer.

In the outer portion of the signal line fanout parts 13 and 23, the resistance of each signal line fanout 15 and 25 is large, but the capacity is small, and in the center of the signal line fanout parts 13 and 23, each signal line fanout 15, The resistance of 25) is small, but the capacitance is large, and as a result, the product of the resistance and capacitance generated in each signal line fanout 15, 25 becomes constant. Therefore, the RC delay caused by the difference in the lengths of the fanouts 15 and 25 can be effectively compensated for by the generation of the capacitance using the overlap electrodes 30 and 40.

The length of the signal line fanout 15 and 25 and the overlapping area of the signal line overlap electrodes 30 and 40 are determined in consideration of the RC delay occurring in the signal line of the thin film transistor substrate 1.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, but the cross section of the gate fanout part 13 is described below, but this may also be applied to the data fanout part 23 having a similar configuration.

A plurality of gate fanouts 15 are formed on an insulating substrate 10 made of an insulating material such as glass, quartz, ceramic, or plastic, and a portion of the gate line 11 branches to form the gate electrode 12. It is coming true. The gate line 11 including the gate fanout 13 and the gate electrode 12 is called a gate wiring.

Although the gate wiring of the present invention is formed in a single layer, it may be formed in multiple layers to compensate for the disadvantages of the metal or alloy and obtain desired properties. In one example, a double layer using aluminum or an aluminum alloy as a lower layer and chromium, molybdenum, molybdenum-tungsten or molybdenum-tungsten nitride as the upper layer is formed. The lower layer uses aluminum or aluminum alloy with low specific resistance to prevent signal resistance due to wiring resistance. It is to use chromium, molybdenum, molybdenum-tungsten or molybdenum-tungsten nitride which are highly corrosion-resistant to chemicals. In recent years, molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W) and the like have been spotlighted as wiring materials.

A gate insulating layer 26 made of silicon nitride (SiNx) is formed on the gate fanout 13 and the gate electrode 12 to cover the gate lines 13 and 12.                     

On the gate fanout 13 is covered the gate overlap electrode 30 which overlaps the gate fanout 13 and forms a capacitor therebetween. Although not shown in the drawing, the area of the gate overlap electrode 30 overlapping with the gate fan out 13 becomes wider toward the center of the gate fan out part. The gate overlap electrode 30 is formed of the same layer as the source electrode 93 and the drain electrode 94 formed on the gate electrode 12. When patterning a data line including the source electrode 93 and the drain electrode 94, a gate overlap electrode 30 is formed in the gate fanout part 13 to form a capacitor together with the gate fanout part 13. Can be. The gate overlap electrode 30 and the source electrode 93 and the drain electrode 94 are formed of the same layer, but they are physically separated from each other so that no electrical contact occurs.

The gate overlap electrode 30 is connected to the gate driving circuit 53 and the electrode wiring 71. The gate overlap electrode 30 receives a constant DC voltage or the like from the gate driving circuit 71 through the electrode wiring 71 to accumulate charge.

On the gate insulating layer 26 where the gate electrode 12 is located, a semiconductor layer 91 made of a semiconductor such as hydrogenated amorphous silicon and an ohmic contact layer 92 made of n + hydrogenated amorphous silicon heavily doped with n-type impurities ) Are formed sequentially. Here, the ohmic contact layer 92 is separated at both sides with respect to the gate electrode 12. The source electrode 93 and the drain electrode 94 are formed on the ohmic contact layer 92. The source electrode 93 and the drain electrode 94 may also be a single layer or multiple layers of a metal layer. A protective film 95 made of a material including silicon nitride (SiNx) is formed on the data line. The protective film 95 has a contact hole for exposing the drain electrode 94. On the passivation layer 95, a pixel electrode 96 is formed which receives an image signal from the thin film transistor and generates an electric field together with the common electrode of the upper plate. The pixel electrode 96 is formed of the same layer as the gate overlap electrode 30, and is physically and electrically connected to the drain electrode 94 through a contact hole to receive an image signal.

In the case of the data fanout part 23, the data overlap electrode 40 which is similar to the gate fanout part 13 but overlaps the data fanout 25 is formed of the same layer as the gate line 11. That is, when the data overlap electrode 40 is formed on the gate wiring, the data overlap electrode 40 is formed under the data fan-out 25, and a gate insulating film made of silicon nitride (SiNx) is stacked therebetween. The data overlap electrode 40 is connected to the data driving circuit 63 through the electrode wiring 81 and receives a constant voltage from the data driving circuit 63.

3 is a cross-sectional view for describing a second embodiment of the present invention, and descriptions of the same components as in FIG. 2 will be omitted.

As shown, the gate overlap electrode 30 is formed of the same layer as the pixel electrode 96, not the same layer as the source electrode 93 and the drain electrode 94. That is, the gate insulating film 12 and the protective film 90 made of silicon nitride (SiNx) are stacked between the gate fanout 15 and the gate overlap electrode 30.

After forming the passivation layer 90, the gate overlap electrode 30 is finally patterned together with the pixel electrode 96 and is made of a transparent conductive material such as indium tin oxide (ITO) or indium tin oxide (IZO). .

The description of the data fanout part 23 and the data overlap electrode 40 is similar to the above description of the gate fanout part 13 and the gate overlap electrode 40. Referring to the cross-section of the data fan-out part 40, the gate insulating layer 26 and the passivation layer 90 are sequentially stacked on the insulating substrate 10, and the data overlap electrode (the same layer as the pixel electrode 90) is formed thereon. 40) is formed.

4 is an enlarged view of a gate fan-out part according to another exemplary embodiment of the present invention, and components not shown are the same as those of FIG. 1.

The gate fanout part 13 including the plurality of gate fanouts 15a and 15b overlaps the gate overlap electrode 30. The gate fanout 15 includes a portion formed in a zigzag pattern rather than a straight line shape, and the closer the wiring is to the display area, the wider the wiring spacing. The interval of the zigzag pattern is different between the gate fanout 15a located in the center of the gate fanout part 13 and the gate fanout 15b located in the outer part, and the zigzag interval increases toward the outer part. That is, it is preferable that the extension length of the zigzag pattern is formed longer from the outer portion to the center portion. Since the portion of the gate fanout 15 having a straight shape rather than the zigzag pattern becomes shorter from the outer portion to the center, the length of the overall gate fanout 15 can be the same by adjusting the length of the zigzag pattern.

By forming the gate fanout 15 including the zigzag pattern as described above, the difference in resistance between the wirings generated in each gate fanout 15 can be compensated for, and the area of the gate overlap electrode 30 is additionally adjusted to adjust each fanout. Adjust so that the product of the resistance and capacity of the circuit is constant, which compensates for the RC delay difference between each fanout and improves the overall picture quality.

The shape of the gate fanout 15 according to the present embodiment may be applied to the data fanout 25 in the same manner, and the resistance compensation may be applied together with the capacitance compensation shown in FIG. 1 to more effectively correspond to the RC delay.

Although some embodiments of the invention have been shown and described, those skilled in the art will appreciate that various configurations of signal line fanouts can be used to compensate for RC delay without departing from the principles or spirit of the invention. It will be appreciated that this embodiment may be modified for modification. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

As described above, according to the present invention, a thin film transistor substrate capable of compensating for the RC delay of the gate fanout part and the data fanout part is provided.

Claims (9)

A signal line defining a display area; A signal line fan out part connected to the signal line at an outer side of the display area, the signal line fan out part including a plurality of fan outs extending from the center to the outer part of the display area; And a overlap electrode overlapping with the signal line fan-out part and having an overlapping area extending from the outer portion toward the center portion. The method of claim 1, The product of the resistance generated in each fan out and the capacitance between each fan out and the overlap electrode is constant. The method of claim 1, The signal line includes a gate line and a data line crossing the gate line. A portion of the overlap electrode is a thin film transistor substrate, characterized in that formed with the same layer as the gate line. The method of claim 3, wherein A portion of the overlap electrode is a thin film transistor substrate, characterized in that formed in the same layer as the data line. The method of claim 3, wherein And a pixel electrode electrically connected to the data line. The overlap electrode is a thin film transistor substrate, characterized in that formed with the same layer as the pixel electrode. The method of claim 5, The overlap electrode is a thin film transistor substrate comprising an ITO or IZO material. The method of claim 1, At least a portion of the fan out is formed in a zigzag pattern, The extension length of the zigzag pattern is a thin film transistor substrate characterized in that is formed longer from the outer portion toward the center. The method of claim 1, A driving circuit for driving the signal line; The thin film transistor substrate further comprises an electrode wiring connecting the driving circuit and the overlap electrode. The method of claim 8, The driving circuit includes a gate driving circuit and a data driving circuit, And the electrode wiring connects the overlap electrode overlapping the gate driving circuit and the gate line, and the overlap electrode overlapping the data driving circuit and the data line.

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