KR20050044947A - Display apparatus and method of manufacturing the same - Google Patents

Abstract

In a display device and a method of manufacturing the same, a display panel includes a display area for displaying an image and a peripheral area adjacent to the display area. In the peripheral area of the display panel, first and second output parts are provided on different layers and provide driving signals to the display area from the outside. The driving chip is provided on the peripheral area of the display panel and outputs a driving signal for driving the display panel. The conductive adhesive member fixes the driving chip to the peripheral area of the display panel and transmits driving signals output from the driving chip to the first and second output units. Therefore, the display device can be implemented in high resolution, and the yield of the product can be increased.

Description

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a display device and a method for manufacturing the same, and more particularly, to a display device and a method for manufacturing the same that can be implemented in high resolution while increasing the yield.

The liquid crystal display device includes a liquid crystal display panel including a lower substrate, an upper substrate facing the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate. The display area of the lower substrate includes a gate line and a data line orthogonal to the gate line.

A gate driving circuit for outputting a gate signal is connected to an end of the gate line, and a data driving circuit for outputting a data signal is connected to an end of the data line. The gate driving circuit and the data driving circuit are formed in a chip shape and are mounted on a peripheral area adjacent to the display area of the lower substrate. The gate and data driving circuit consists of one or more chips.

Due to a design problem of the liquid crystal display panel, the size of the gate driving chip is generally smaller than the width in the column direction of the display area, and the size of the data driving chip is also smaller than the width in the row direction of the display area.

Therefore, the distance between the gate-side output wirings for transmitting the gate signal output from the gate driving chip to the gate line becomes narrower as it is closer to the gate driving chip. In addition, the interval between the data side output wires for transmitting the data signal output from the data driving chip to the data line becomes narrower as the data driving chip is adjacent to the data driving chip.

Recently, although the liquid crystal display panel is implemented at a high resolution, the number of chips mounted on the liquid crystal display panel is reduced in order to reduce the number of processes while improving the yield.

Therefore, in order to form output wirings in a given space, the line widths of the output wirings may be reduced or the intervals of the output wirings may be narrowed. However, such a structure causes disconnection of the output wirings in the peripheral region of the liquid crystal display panel or increases the line resistance of the output wirings.

Accordingly, an object of the present invention is to provide a display device capable of increasing the yield while achieving high resolution.

It is also an object of the present invention to provide a manufacturing method used to manufacture the display device described above.

A display device according to an aspect of the present invention includes a display panel, a driving chip, and a conductive adhesive member.

The display panel includes a display area for displaying an image and a peripheral area adjacent to the display area, and the first and second outputs are disposed on different layers in the peripheral area to provide driving signals from the outside to the display area. Is provided.

The driving chip is provided on a peripheral area of the display panel and outputs the driving signal for driving the display panel. The conductive adhesive member fixes the driving chip to a peripheral area of the display panel, and transmits the driving signal output from the driving chip to the first and second output units.

According to another aspect of the present invention, there is provided a method of manufacturing a display device, including a display area for displaying an image and a peripheral area adjacent to the display area, wherein the peripheral area is located on a different layer and receives a drive signal from an external device. Forming a display panel including first and second output parts to provide a light emitting layer; forming the conductive adhesive member on a peripheral area of the display panel; and driving the display panel through the conductive adhesive member. And electrically connecting the driving chip to the first and second output units while fixing the driving chip outputting the driving signal to the display panel.

According to such a display device and a method of manufacturing the same, first and second output parts are provided in peripheral areas of the display panel to provide driving signals from the outside to the display area on different layers. The unit is electrically connected to the driving chip generating the driving signal through an ACF. Therefore, the display device can realize high resolution, while increasing the yield.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of the liquid crystal display shown in FIG. 1.

Referring to FIG. 1, the liquid crystal display device 400 includes a liquid crystal display panel 100 for displaying an image, a driving chip 210 for outputting a data signal and a gate control signal for driving the liquid crystal display panel 100, The gate driving circuit 220 outputs a gate signal in response to the gate control signal, and the flexible circuit board 300 providing various signals to the driving chip 210.

The liquid crystal display panel 100 is divided into a display area DA displaying an image and a peripheral area PA adjacent to the display area DA. 2A and 2B, in the display area DA, the liquid crystal display panel 100 includes a lower substrate 110, an upper substrate 120, and a lower substrate 110 and an upper substrate 120. It consists of a liquid crystal layer 130 interposed between.

The lower substrate 110 includes a data line DL and a gate line GL orthogonal to the data line DL in the display area DA on the first substrate 111. The semiconductor device may further include a thin film transistor (TFT) 112 connected to the DL and the gate line GL, and a pixel electrode 115 connected to the TFT 112. The TFT 112 includes a gate electrode 112a connected to the gate line GL, a source electrode 112b connected to the data line DL, and a drain electrode 112c coupled to the pixel electrode 115. do. The gate electrode 112a is electrically insulated by the source and drain electrodes 112b and 112c and the gate insulating layer 113.

The lower substrate 110 further includes a passivation layer 114 covering the data line DL, the gate line GL, and the TFT 112. A first contact hole 114a exposing the drain electrode 112c is formed in the passivation layer 114. The passivation layer 114 is formed of an inorganic insulating layer such as a silicon nitride layer (SiNx) and a silicon oxide layer (SiOx).

The pixel electrode 115 is provided on the passivation layer 114 and is electrically connected to the drain electrode 112c of the TFT 112 through the first contact hole 114a. The pixel electrode 115 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The driving chip 210 is mounted on the lower substrate 110 to correspond to the peripheral area PA. A plurality of first and second output terminals OT1 and OT2 through which the gate control signal or the data signal is output are provided on the rear surface of the driving chip 210.

In addition, the peripheral area PA may include a first output unit for electrically connecting the driving chip 210 to the data line GL of the gate driving circuit 220 or the display area PA. AA) and a second output unit BB are provided.

The first output part AA includes a plurality of first output wires OL1 and a plurality of first output pads OP1 extending from the plurality of first output wires OL1. The first output part AA is provided on the same layer as the gate electrode 112a of the TFT 112. The gate insulating layer 113 is provided on the first output part AA, and the plurality of second contact holes 113a exposing the plurality of first output pads OP1 are formed in the gate insulating layer 113. do.

The second output part BB includes a plurality of second output wires OL2, a plurality of second output pads OP2 extending from the plurality of second output wires OL2, and the plurality of second output pads ( OP3) and a plurality of third output pads OP3 spaced apart from each other. The plurality of third output pads OP3 are electrically connected to the plurality of first output pads OP1 exposed through the plurality of second contact holes 113a, respectively.

The second output part BB is disposed on the same layer as the source and drain electrodes 112b and 112c of the TFT 112. Accordingly, the plurality of second and third output pads OP2 and OP3 are directly connected to the first and second output terminals OT1 and OT2 of the driving chip 210 to the gate control signal or the data. Receive the signal.

An anisotropic conductive film (hereinafter, referred to as an anisotropic conductive film) between the plurality of second and third output pads OP2 and OP3 and the first and second output terminals OT1 and OT2 of the driving chip 210. ACF) 250 is interposed. The ACF 250 is formed of an adhesive material 251 having adhesiveness and conductive particles 252 having the conductivity and formed in the adhesive material 251.

Accordingly, the ACF 250 adheres the driving chip 210 onto the lower substrate 110, and the plurality of second and third output pads OP2 and OP3 through the conductive particles 252. And electrically connect the first and second output terminals OT1 and OT2 to each other.

Meanwhile, the upper substrate 120 is a substrate on which the color filter 122 and the common electrode 123 are provided on the second substrate 121. The color filter 122 is made of R (Red), G (Green), and B (Blue) color pixels, and the common electrode 123 is made of ITO or IZO.

1 to 2B, the gate driving circuit 220 forms the TFT 112 through the same process as forming the TFT 112 in the display area DA of the lower substrate 110. In the process, the lower substrate 110 is formed in the peripheral area PA.

However, the gate driving circuit 220 may be embedded in the driving chip 210 or may be formed as a separate chip to be mounted in the peripheral area PA of the lower substrate 110. When the gate driving circuit 220 is embedded in the driving chip 210, the driving chip 210 outputs a gate signal to the gate line GL provided in the display area DA.

3A to 6B are views illustrating a manufacturing process of the lower substrate shown in FIGS. 2A and 2B.

First, referring to FIGS. 3A and 4A, a first metal film made of aluminum (Al), chromium (Cr), or molybdenum tungsten (MoW) may be formed on a first substrate 111 made of an insulating material such as glass or ceramic. Is deposited by the sputtering method.

Thereafter, the first metal layer is patterned to form the gate electrode 112a in the display area DA, and at the same time, the plurality of first output wires OL1 and the plurality of first output wires are formed in the peripheral area PA. A plurality of first output pads OP1 extending from OL1 are formed.

Next, referring to FIGS. 3B and 4B, silicon nitride is deposited on a plasma chemical vapor phase on the first substrate 111 on which the gate electrode 112a, the plurality of first output wirings OL1, and the plurality of first output pads OP2 are formed. The gate insulating layer 113 is formed by depositing by a plasma-enhanced chemical vapor deposition (PECVD) method.

Thereafter, the gate insulating layer 113 is patterned to form a plurality of second contact holes 113a exposing the plurality of first output pads OP1, respectively.

5A and 6A, an amorphous silicon film (not shown) is deposited on the gate insulating layer 113 by a plasma chemical vapor deposition method, and an n + doped amorphous silicon film (not shown) is deposited on the gate insulating film 113. It deposits by a vapor deposition method. At this time, the amorphous silicon film and the n + doped amorphous silicon film are deposited in-situ in the same chamber of the plasma chemical vapor deposition facility.

In addition, the amorphous silicon film and the n + doped amorphous silicon film are patterned to form an active layer 112d and an ohmic contact layer 112e corresponding to a region where the gate electrode 112a is formed.

Subsequently, a second metal film (not shown) such as chromium (Cr) is deposited on the first substrate 111 on which the gate insulating layer 113 and the ohmic contact layer (not shown) are formed by a sputtering method. Next, the second metal layer is patterned to form a source electrode 112b and a drain electrode 112c spaced apart from the source electrode 112b in the display area DA.

In addition, the peripheral area PA includes a plurality of second output wires OL2, a plurality of second output pads OP2 extending from the plurality of second output wires OL2, and the plurality of second output pads ( A plurality of third output pads OP3 spaced apart from OP2) is formed.

Each of the plurality of second output wires OL2 is provided in a space between the plurality of first output wires OP1. A first horizontal separation distance d1 between each of the second output wires OL2 and the first output wires OL1 adjacent to each other is a second horizontal separation between the first output wires OL1 adjacent to each other. The distance d2 is smaller than the third horizontal separation distance d3 between the adjacent second output lines OL2.

Since the gate insulating layer 113 is interposed between the plurality of second output wires OL2 and the plurality of first output wires OL1, the first horizontal separation distance d1 is determined as the second or second distance. It may be smaller than the third horizontal separation distance d2 and d3. Here, horizontal indicates that the surface is parallel to the laminated surface of the first substrate 111 in which a plurality of layers are formed.

As illustrated in FIGS. 5A and 6B, the plurality of third output pads OP3 may be exposed through the second contact hole 113a formed in the gate insulating layer 113. Are formed to correspond to each other. Therefore, the plurality of third output pads OP3 are electrically connected to the plurality of first output pads OP1.

Subsequently, the ohmic contact layer 112e exposed between the source and drain electrodes 112b and 112c is removed by a reactive ion etching (RIE) method. Then, the active layer 112d exposed between the source and drain electrodes 112b and 112c is provided to the channel region of the TFT 112. As a result, a TFT 112 is formed in the display area DA.

As illustrated in FIG. 5B, each of the plurality of second output wires OL2 may partially overlap the two adjacent first output wires OL1 or the first output pads OP1. . Each of the plurality of first output wires OL1 may partially overlap the second output wire OL1, the second output pad OP2, or the third output pads OP3 that are adjacent to each other.

In particular, since the first to third output pads OP1 to OP3 have a wider width than the first and second output wires OL1 and OL2, the first to third output pads OP1. In the region where OP3) is formed, overlapping portions increase. As such, when overlapping, the first and second output units AA and BB may be further integrated.

FIG. 7 is a view illustrating in detail the rear surface of the driving chip illustrated in FIG. 1.

Referring to FIG. 7, the driving chip 210 includes a plurality of first and second output terminals OT1 and OT2 on its rear surface. When the plurality of first output terminals OT1 are provided on the rear surface of the driving chip 210, the plurality of second output terminals OT2 are disposed outside the plurality of first output terminals OT1. Here, each of the second output terminals OT2 is disposed between the first output terminals OT1.

2A and 2B, between the plurality of second and third output pads OP2 and OP3 and the first and second output terminals OT1 and OT2 of the driving chip 210. ACF 250 is interposed. Accordingly, the plurality of second output pads OP2 are electrically connected to the corresponding first output terminals OT1 through the ACF 250, and the plurality of third output pads OP3 correspond to the corresponding first output terminals OT1. The second output terminal OT2 is electrically connected through the ACF 250.

Therefore, the signal output through the first output terminal OT1 of the driving chip 210 is applied to the second output wiring OL2 via the second output pad OP2. In addition, the signal output through the second output terminal OT2 of the driving chip 210 is transferred to the first output wiring OL1 via the third output pad OP3 and the first output pad OP1. Is approved.

According to such a display device and a method of manufacturing the same, first and second output parts are provided in peripheral areas of the display panel to provide driving signals from the outside to the display area on different layers. The output unit is electrically connected to the driving chip generating the driving signal through an ACF.

Therefore, even if the display device is developed at a high resolution, disconnection or short circuits occurring in the first and second output units connecting the driving chip and the display area can be prevented and the line resistance of each of the wirings can be reduced. You can. As a result, malfunction of the display device can be prevented, whereby the yield can be improved.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the liquid crystal display shown in FIG. 1.

3A to 6B are views illustrating a manufacturing process of the lower substrate shown in FIGS. 2A and 2B.

FIG. 7 is a view illustrating a rear surface of the driving chip shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: liquid crystal display panel 110: lower substrate

120: upper substrate 130: liquid crystal layer

210: driving chip 220: gate driving circuit

300: flexible circuit board 400: liquid crystal display device

Claims (9)

A display area configured to display an image and a peripheral area adjacent to the display area, wherein the peripheral area includes a first and second output parts disposed on different layers to provide driving signals from the outside to the display area; panel; A driving chip provided on a peripheral area of the display panel and outputting the driving signal for driving the display panel; And And a conductive adhesive member which fixes the driving chip to a peripheral area of the display panel and transmits the driving signal output from the driving chip to the first and second output parts. The display device of claim 1, wherein the first output part comprises a first output wire and a first output pad having a width wider than that of the first output wire. The second output unit may include a second output wiring, a second output pad having a wider width than the second output wiring and spaced apart from the first output pad by a predetermined interval, and a third output pad provided corresponding to the first output pad. Display device comprising a. The method of claim 2, further comprising an insulating film interposed between the first and second output unit, A contact hole for exposing the first output pad is formed in the insulating layer, and the third output pad is electrically connected to the first output pad through the contact hole. The display device of claim 2, wherein the first output line is disposed between two second output lines. The display device of claim 4, wherein the first output wiring partially overlaps the two second output wiring. The display device of claim 2, wherein the driving chip comprises first and second output terminals electrically connected to the second and third output pads, respectively. The display device of claim 1, wherein the display area includes a gate wiring provided in a first layer identical to the first output wiring, a data wiring provided in a second layer identical to the second output wiring, and the gate wiring and a data wiring; And a thin film transistor connected thereto. A display area configured to display an image and a peripheral area adjacent to the display area, wherein the peripheral area includes a first and second output parts disposed on different layers to provide driving signals from the outside to the display area; Forming a panel; Forming the conductive adhesive member on a peripheral area of the display panel; And Electrically connecting the driving chip to the first and second output parts while fixing the driving chip for outputting the driving signal for driving the display panel to the display panel through the conductive adhesive member. A method of manufacturing a display device, characterized in that. The method of claim 8, wherein the forming of the display panel comprises: Forming a first output pad in the peripheral area and a first output pad having a width wider than that of the first output wire; Forming an insulating film on the first output line and the first output pad; Patterning the insulating layer to form a contact hole exposing the first output pad; And A second output wiring on the insulating layer, a second output pad having a width wider than the second output wiring, and spaced apart from the first output pad by a predetermined distance and electrically connected to the first output pad through the contact hole. And forming an output pad (3).