KR100823820B1 - Nonvolatile semiconductor memory - Google Patents

Abstract

When the different word lines are sequentially accessed, the word decoder overlaps a part of the activation periods of the word lines with each other to execute the access operation in parallel. That is, the nonvolatile semiconductor memory can perform pipeline processing for executing access operations in parallel. The combination of bit lines and source lines connected to the drain and the source of the nonvolatile memory cell are all different. For this reason, even when a plurality of word lines are activated to execute a plurality of read operations in parallel, the memory cell current can flow only between the drain and the source of the nonvolatile memory cell of interest. Therefore, in the nonvolatile semiconductor memory having a pipeline function for executing a plurality of read operations in parallel, random access for sequentially accessing any nonvolatile memory cells can be performed.

Description

Nonvolatile Semiconductor Memory {NONVOLATILE SEMICONDUCTOR MEMORY}

The present invention relates to a nonvolatile semiconductor memory having a nonvolatile memory cell.

A nonvolatile semiconductor memory such as a flash memory stores data by whether electrons are held in a floating gate or a trap gate of a memory cell transistor (hereinafter referred to as a memory cell). For example, in the nonvolatile semiconductor memory disclosed in Japanese Patent Laid-Open No. 7-114796, memory cells are formed at intersections of word lines and bit lines that are perpendicular to each other. Source lines connected to the source of the memory cells are wired along the word lines. Sources of memory cells arranged along a pair of word lines are connected to a common source line. The drains of the memory cells arranged along the bit lines are connected to a common bit line.

In Japanese Patent Laid-Open No. 8-69696, by accessing two memory cell arrays (sub arrays) alternately, it is possible to continuously read data from the memory cells even when switching word lines.

[Patent Document 1] Japanese Patent Application Laid-Open No. 7-114796

[Patent Document 2] Japanese Patent Application Laid-Open No. 8-69696

The present invention could be made to solve the following problems.

In the nonvolatile semiconductor memory of Japanese Patent Laid-Open No. 7-114796, memory cells connected to adjacent word lines and arranged along bit lines are connected to common bit lines and common source lines. When these memory cells are read sequentially, the selection periods of word lines adjacent to each other cannot be duplicated. Therefore, when addresses are randomly supplied (random access) in the read operation, data from the memory cells cannot be continuously output. In Japanese Patent Laid-Open No. 8-69696, random access is possible only when the sub arrays are alternately accessed. In other words, when random access is performed with one sub array, data cannot be output continuously. In particular, in the read operation, random access cannot be executed in a nonvolatile semiconductor memory in which part of the activation period of the word line is overlapped to perform parallel processing (pipeline processing).

An object of the present invention is to perform random access in a nonvolatile semiconductor memory having a pipeline function of executing successive read operations in parallel. In particular, it is to provide a nonvolatile semiconductor memory capable of random access without increasing the chip size.

In one embodiment of the present invention, word lines, bit lines, and source lines are connected to gates, drains, and sources of a plurality of nonvolatile memory cells arranged in a matrix. The word decoder activates the word line in accordance with the address signal. Further, when the different word lines are sequentially accessed, the word decoder overlaps a part of the activation periods of the word lines with each other to execute the access operation in parallel. That is, the nonvolatile semiconductor memory can perform pipeline processing for executing access operations in parallel. The combination of bit lines and source lines connected to the drain and the source of the nonvolatile memory cell are all different. For this reason, even when a plurality of word lines are activated to execute a plurality of read operations in parallel, the memory cell current can flow only between the drain and the source of the nonvolatile memory cell of interest. Therefore, in the nonvolatile semiconductor memory having a pipeline function for executing a plurality of read operations in parallel, random access for sequentially accessing any nonvolatile memory cells can be performed.

In a preferable example of one embodiment of the present invention, the plurality of cell groups are arranged in the wiring direction of a word line and are configured by connecting nonvolatile memory cells in series. For each cell group pair which is a pair of cell groups adjacent to each other, a pair of bit lines cross each other and are wired in a zigzag form. By changing the wiring method of the bit lines, a nonvolatile semiconductor memory capable of performing random access without increasing the chip size can be constructed.

In a preferable example of one embodiment of the present invention, each cell group is composed of a plurality of nonvolatile memory cell pairs whose sources are connected to each other. In each cell group pair, nonvolatile memory cell pairs opposed to each other are connected to different source lines. Therefore, the combination of bit lines and source lines connected to the drain and source of the nonvolatile semiconductor memory can be made different for each pair of nonvolatile memory cells (including four nonvolatile memory cells) facing each other.

In a preferable example of one embodiment of the present invention, a source region where a source is formed and a drain region where a drain is formed are alternately formed between word lines. In each cell group pair, a pair of source lines connected to sources of opposing nonvolatile memory cell pairs are wired on the source region and the drain region, respectively. For this reason, a large number of source lines can be wired without increasing the size of the memory cell array. That is, it is possible to prevent the chip size of the nonvolatile semiconductor memory from increasing.

In a preferable example of one embodiment of the present invention, the source line on the drain region has a protrusion that protrudes toward the source region. The source line on the drain region is wired using a wiring layer below the source line on the source region. For this reason, even when wiring the number of source lines with a larger number than before, the wiring width of each source line can be enlarged and the source resistance can be reduced, without making a chip size large.

In a preferable example of one embodiment of the present invention, each cell group is composed of a plurality of nonvolatile memory cell pairs whose sources are connected to each other. In the cell group pairs adjacent to each other, the source of each of the nonvolatile memory cell pairs facing each other is formed by a common diffusion layer. For this reason, the total area of the source diffusion layer can be reduced, and the chip size of the nonvolatile semiconductor memory can be reduced.

In a preferable example of one embodiment of the present invention, the contact portion is formed between the cell group pairs and connects the source line formed by using the wiring layer to the diffusion layer. Each source line is connected to the diffusion layer via a contact portion. Since the number of contact portions can be minimized, it is possible to prevent the chip size from increasing.

In a preferable example of one embodiment of the present invention, in each cell group pair, the nonvolatile memory cell pairs opposed to each other are connected to different source lines. Each contact portion formed along the wiring direction of the word line is connected to one and the other source line. Also in this example, the number of contact portions formed can be minimized, and the chip size can be prevented from increasing.

In a preferred example of one embodiment of the present invention, the source decoder sets a source line connected to a nonvolatile memory cell to be accessed to a ground voltage and sets another source line to a floating state when the memory cell is accessed. Therefore, even when a plurality of word lines are activated by the pipeline processing, the memory cell current can flow only between the drain and the source of the nonvolatile memory cell of interest. Therefore, in the nonvolatile semiconductor memory that executes a plurality of read operations in parallel, random access for sequentially accessing any nonvolatile memory cells can be performed.

In a preferred example of one embodiment of the present invention, the column decoder sets a bit line connected to a nonvolatile memory cell to be accessed as a drain voltage and sets another bit line to a floating state when the memory cell is accessed. Also in this example, even when a plurality of word lines are activated by pipeline processing, the memory cell current can flow only between the drain and the source of the nonvolatile memory cell of interest. Therefore, in the nonvolatile semiconductor memory that executes a plurality of read operations in parallel, random access for sequentially accessing any nonvolatile memory cells can be performed.

1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory of the present invention;

FIG. 2 is a circuit diagram showing details of the memory cell array shown in FIG.

3 is a layout diagram showing details of the memory cell array shown in FIG. 1;

4 is a timing chart showing an example of a read operation of the flash memory of the present invention.

5 is an explanatory diagram showing a state of a memory cell when a read operation is executed continuously;

Fig. 6 is a circuit diagram showing a state of the memory cell MC when the read operation is executed in succession.

7 is a layout showing an example of a memory cell array examined by the inventor before the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described using drawing. In the drawings,? Denotes an external terminal. In the figure, the signal line shown by the thick line consists of a plurality of lines. In addition, a part of the block to which the thick line is connected is comprised by the some circuit. The same code as the terminal name is used for the signal supplied through the external terminal. In addition, the same code | symbol as a signal name is used for the signal line to which a signal is transmitted.

1 illustrates an embodiment of a nonvolatile semiconductor memory of the present invention. This nonvolatile semiconductor memory is formed as a NOR flash memory using a CMOS process on a silicon substrate. The flash memory includes a command input circuit 10, a state machine 12, an address input circuit 14, a data input / output circuit 16, a word decoder 18, a source decoder 20, a column decoder 22, and data control. It has a circuit 24 and a memory cell array 26. The memory core 28 is constituted by the word decoder 18, the source decoder 20, the column decoder 22, the data control circuit 24, and the memory cell array 26.

The command input circuit 10 decodes the command signal CMD received through the command terminal CMD and notifies the state machine 12 of the decoded command. Examples of the command signal CMD include a chip enable signal, an output enable signal, a write enable signal, and the like. The state machine 12 generates a plurality of timing signals for operating the flash memory according to the command decoded by the command input circuit 10 and stores the generated timing signals in an internal circuit (address input circuit 14, data). Input / output circuit 16, word decoder 18, source decoder 20, column decoder 22, data control circuit 24 and the like. The state machine 12 divides the operations of the internal circuits into a plurality of stages that are independent of each other in order to execute pipeline processing for executing a plurality of read operations (access operations) in parallel. Each step is executed sequentially by a timing signal. The pipeline processing will be described later with reference to FIG. 4.

The address input circuit 14 outputs the address signal AD received through the address terminal AD to the word decoder 18, the source decoder 20, and the column decoder 22. Further, a predecoder for predecoding the address signal AD may be disposed between the address input circuit 14 and the word decoder 18, the source decoder 20, and the column decoder 22. The data input / output circuit 16 outputs data read from the memory cell array 26 to the data terminal DQ. The data input / output circuit 16 receives data written to the memory cell array 26 through the data terminal DQ. A part of the command signal may be received at the data terminal DQ, and the state machine 12 may determine an operation command in combination with the command signal CMD received at the command terminal CMD.

The word decoder 18 selects any one of the word lines WL in accordance with the address signal AD when the memory cell MC is accessed. The word decoder 18 performs a function of overlapping a part of the activation period of the word line WL under the control of the state machine 12 when the read operation is continuously executed and different word lines WL are sequentially selected. Has In the read operation, the source decoder 20 sets the source line SL selected by the address signal AD to the ground voltage, and sets the other source line SL to the floating state. That is, the source line SL connected to the nonvolatile memory cell MC to be accessed is set to the ground voltage, and the other source line SL is set to the floating state. In the read operation, the column decoder 22 sets the bit line BL selected by the address signal AD to the drain voltage (for example, 1V) and sets the other bit line BL to the floating state. That is, the bit line BL connected to the nonvolatile memory cell to be accessed is set to the drain voltage, and the other bit line BL is set to the floating state.

The data control circuit 24 has a sense amplifier (not shown), a data writing circuit, and the like. The sense amplifier detects the memory cell current flowing between the drain and the source of the memory cell MC during the read operation, and determines the logic value of the data held in the memory cell MC. The write circuit controls the write operation (program) and erase operation of the data.

The memory cell array 26 has a plurality of nonvolatile memory cells MC arranged in a matrix. Each memory cell MC is composed of a memory cell transistor having a floating gate. The control gate of the memory cell MC is connected to any one of the word lines WL (WL0, 1, ...). The drain of the memory cell MC is connected to any one of the bit lines BL (BL0, 1, ...). The source of the memory cell MC is connected to any one of the source lines SL (SL0, 1, ...). The memory cell array 26 will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 shows details of a circuit of the memory cell array 26 shown in FIG. The memory cell array 26 has a plurality of cell groups CG formed by connecting memory cells MC in series. Each cell group CG is constituted by a nonvolatile memory cell pair MCP (ellipse frame in the figure), which consists of a pair of memory cells MC whose sources are connected to each other. The cell groups CG are arranged in the wiring direction (left and right directions in the figure) of the word line WL. A cell group pair CGP is formed by a pair of cell groups adjacent to each other. A pair of bit lines BL (for example, BL0 and BL1) are wired for each cell group pair CGP along the orthogonal direction of the word line WL. The bit line pair BL is wired in a zigzag form while crossing each other.

In the cell group pair CGP adjacent to each other, the source of each memory cell pair MCP facing each other is formed by a common diffusion layer (a rectangular frame of a broken line). In each cell group pair CGP, two nonvolatile memory cell pairs MCP facing each other are connected to different source lines SL. For example, two memory cell pairs MCP connected to word lines WL1 and 2 are connected to different source lines SL1 and SL0, respectively. Hereinafter, two memory cell pairs MCP (including four memory cells MC) that face each other in each cell group pair CGP are referred to as memory cell groups. In each memory cell group, the combination of the bit line BL and the source line SL connected to the drain and the source of the memory cell MC are all different.

At least one of the word line pair WL and the bit line pair BL is different from each other in the plurality of memory cell groups. Accordingly, the bit line pair BL is wired in a zigzag pattern so that the source lines SL of the two memory cell pairs MCP facing each other in each cell group pair CGP are different from each other. The combination of the bit lines BL and the source lines SL connected to the drain and the source of the memory cell MC can all be made different without increasing the layout size.

FIG. 3 shows a detailed layout of the memory cell array 26 shown in FIG. In the figure, a thick dashed line frame shows a diffusion layer formed on a semiconductor substrate. The word line WL shown by a mesh display is formed using poly-silicon (Poly-Si). The bit line BL shown by the thick solid line is formed using the 1st metal wiring layer M1 and the 2nd metal wiring layer M2. The source line SL shown by a thin solid line is formed of the 3rd metal wiring layer M3 and the 4th metal wiring layer M4. The metal wiring layer is formed on the semiconductor substrate in the order of M1, M2, M3, M4. The rectangular frame with X shows a contact portion CNT (plug) for connecting the diffusion layer to the metal wiring layer. The contact portion CNT of the bit line BL is shown by a thick rectangular frame, and the contact portion CNT of the source line SL is shown by a thin rectangular frame. An area shown by diagonal lines in the drawing shows one memory cell MC. In addition, in FIG. 3, in order to make the distinction of wiring clear, the width | variety of a part of wiring is described as thinner than actual. In practice, each wiring has a width that satisfies the layout design criteria.

The bit line pair BL intersects on the source region. The source region where the source of the memory cell MC is formed and the drain region where the drain of the memory cell MC are formed are alternately formed between the word lines WL. The thick broken line frame in the source region indicates the source diffusion layer, and the thick broken line in the drain region indicates the drain diffusion layer. Even-numbered source lines SL0, SL2, ... are formed on the drain region. Odd numbered source lines SL1, 3, ... are formed on the source region. In each cell group pair CGP, a pair of source lines SL respectively connected to the sources of memory cell pairs MCP facing each other are wired on the source region and the drain region, respectively. That is, in each cell group pair CGP, memory cell pairs MCP facing each other are connected to different source lines SL. By forming the source lines SL on the source region and the drain region, a large number of source lines can be wired without increasing the size of the memory cell array. In addition, by forming the source lines SL by using the two metal wiring layers M3 and M4, the wiring width of each source line SL can be widened without increasing the chip size, and the source resistance can be increased. Can be reduced.

The source line SL on the source region is directly connected to the diffusion layer through the contact portion CNT. The source line SL on the drain region has a protrusion PP that protrudes onto the source diffusion layer toward the source region. The source line SL on the drain region is connected to the diffusion layer through the protruding portion PP and the contact portion CNT. Each contact portion CNT is formed between the cell group pairs CGP. The contact portions CNT formed along the wiring direction (horizontal direction in the figure) of the word line WL are connected to the source line SL on the source region and the source line SL on the drain region. As described above, in the cell group pair CGP adjacent to each other, the source of each memory cell pair MCP facing each other is formed by a common diffusion layer. For this reason, the number of formation of the contact part CNT can be minimized, and the total area of a source diffusion layer can be reduced. Therefore, the chip size of the flash memory can be reduced. Further, by forming the contact portion CNT between the cell group pairs CGP, it is possible to prevent the contact portion CNT of the source line from shorting with the bit line BL.

4 shows an example of a read operation of the flash memory of the present invention. In this example, the flash memory continuously receives the address signals AD (AD0, AD1, ...) together with the read command, and executes the read operation continuously. By the execution of the read operation, the read data DQ (DQ0, DQ1, ...) are output continuously. The latency from the supply of the address signal AD to the output of the data signal DQ is "4". The present invention can also be applied to a read operation of latency other than " 4 ".

One read operation consists of four steps. The four steps are the detection step ADT of the address signal AD, the activation step WL of the word line WL, the data read step BL, SL, SA and the data output step DOUT. ATD indicates the selection and determination period (detection of transition of address signal AD) of the address signal AD. WL represents a selection period (step-up period) of the word line WL. BL indicates the selection period of the bit line BL. SL represents the selection period of the source line SL. SA represents the determination period of data by the sense amplifier. DOUT represents an output period of data.

These steps are processed independently of each other by the control of the state machine 12. By constructing one read operation by a plurality of independent steps, a pipelined process for executing a plurality of read operations in parallel becomes possible. By pipeline processing, the external read cycle which is the output cycle of the data signal DQ can be shortened, and the data transfer rate can be improved.

The word line WL needs to continue activation until data is read. For this reason, the period of the activation step of the word line WL includes the periods BL, SL, SA of the data read step. In other words, in the current read operation, the word line WL is activated, and when the data read step is executed, the separate word line WL is activated for the next read operation. For this reason, some of the activation steps of the word line WL overlap each other when the read operation is continuous. In the conventional nonvolatile semiconductor memory having a pipelined function, the pipelined operation shown in FIG. 4 cannot be executed in a random access for performing a read operation in accordance with an arbitrary arbitrary address signal AD. However, in the present invention, since the combinations of the bit lines BL and the source lines SL connected to the drain and the source of the memory cell MC are all different, the surface pipeline operation can be performed for random access.

5 shows the state of the memory cell MC when the read operation is executed continuously. The memory cell MC reading data receives a boosted voltage (eg, 5V) at the gate G, a drain voltage (eg, 1V) at the drain D, and a ground voltage (0V) at the source S. Receive. The logic held in the memory cell MC is determined according to the memory cell current flowing between the drain and the source. Here, the gate voltage is set by the word decoder 18 under the control of the state machine 12. The drain voltage is set by the column decoder 22 under the control of the state machine 12. The source voltage is set by the source decoder 20 under the control of the state machine 12.

The flash memory is used to read the memory cell MC next time when a memory cell MC is being read, that is, during a period in which a word line WL is set to a boosted voltage in order to execute a pipeline readout. The connected word line WL is set to a boosted voltage. At this time, when the memory cell current of the memory cell MC to be read next flows through the bit line BL or the source line SL connected to the memory cell MC being read, the data of the memory cell MC being read is read. Cannot be determined accurately. In order to prevent the misreading of data, the next memory cell MC (memory cell MC whose word line WL is set to a boosted voltage) is read out of states A, B, and C so that no memory cell current flows. It must be set to either. That is, the memory cell MC to read next sets at least one of the drain D and the source S in a floating state (open), or sets the voltage between the drain D and the source S to 0V. Must be set to. Specifically, in the state A, the drain D is set to open or 0V (source voltage). In state B, source S is set to open or 1V (drain voltage).

Fig. 6 shows the state of the memory cell MC when the read operation is executed continuously. In this example, a read operation is performed on the memory cell MC shown in circles. For this reason, the word line WL3, the bit line BL3, and the source line SL2 shown by the thick line are set to the boost voltage, the drain voltage, and the ground voltage, respectively. Symbols A, B, and C shown next to each memory cell MC indicate states A, B, and C (FIG. 5) when the boosted voltage is supplied to the word line WL.

When the word line WL corresponding to the memory cell MC to be read next is activated, all the memory cells MC are in any of states A, B, and C. Specifically, in the case of another memory cell MC in which the next memory cell MC to be read is connected to the source line SL2, these memory cells MC are in state A. FIG. In the case where the memory cell MC to be read next is connected to the bit line BL3, these memory cells MC are in state B. FIG. When the next memory cell MC to be read is the memory cell MC other than the above, these memory cells MC are in the state C. FIG. Therefore, in the flash memory having the pipeline function, random access (read operation) can be executed.

7 shows an example layout of a memory cell array examined by the inventor before the present invention. In this example, with respect to the conventional memory cell array, the bit lines BL are wired zigzag using the metal wiring layers M1 and M2, and the source lines SL are wired using the metal wiring layers M3 and M4. It is. The contact portion CNT connecting the source line SL to the source diffusion layer of the memory cell MC is formed for each memory cell MC. When the bit lines BL are wired in a zigzag pattern, the bit lines BL need to cross on the source region. For this reason, the bit line BL and the contact portion CNT of the source region are shorted. In order to avoid a short, when the distance between the bit line BL and the contact portion CNT is separated, the size of the memory cell array increases. As shown in FIG. 3, the contact portion CNT of the source region is commonly disposed between adjacent cell group pairs CGP, thereby increasing the size of the memory cell array and increasing the size of the bit line BL and the bit line BL. It is possible to prevent the contact portion CNT of the source region from shorting.

As described above, in the present embodiment, a new method is applied to the wiring layout of the memory cell array 26, and all combinations of the bit lines BL and the source lines SL connected to the drain and the source of the memory cell MC are entirely used. It can be different. The source decoder 20 sets the source line SL connected to the memory cell MC to be accessed to the ground voltage under the control of the state machine 12, and sets the other source line SL to the floating state. . The column decoder 22 sets the bit line BL connected to the memory cell MC to be accessed as the drain voltage under the control of the state machine 12, and sets the other bit line BL to the floating state. . For this reason, in a flash memory having a pipeline function for executing a plurality of read operations in parallel, random access (random read) can be executed.

For each cell group pair CGP, a pair of bit lines BL are wired in a zigzag form while crossing each other. The contact portion CNT of the source line SL is shared between the plurality of memory cells MC and is thus formed between adjacent cell group pairs CGP. By sharing the contact portion CNT, it is possible to construct a flash memory having a pipelined function and capable of performing random access without increasing the size of the memory cell array 26. By wiring the source line SL on the drain region and the source region using the metal wiring layers M3 and M4, a large number of source lines can be wired without increasing the size of the memory cell array.

In addition, in the above-mentioned embodiment, the example which crossed a pair of bit line BL mutually and wired in a zigzag form was mentioned. The present invention is not limited to this embodiment. For example, the bit lines BL are wired without crossing each other, and the same effect can be obtained even when the source lines are crossed with each other and wired in a zigzag form for each pair of source lines composed of two source lines.

In the above embodiment, an example in which each memory cell MC is constituted by a memory cell transistor having a floating gate has been described. The present invention is not limited to this embodiment. For example, the same effect can be obtained even when each memory cell MC is comprised with the memory cell transistor which has a trap gate.

As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only an example of invention, and this invention is not limited to this. It is apparent that modifications can be made without departing from the invention.

In the present invention, in a nonvolatile semiconductor memory having a pipeline function, random access can be executed without increasing the chip size.

Claims (10)

A plurality of nonvolatile memory cells arranged in a matrix, A plurality of word lines connected to gates of the nonvolatile memory cells; A plurality of bit lines connected to a drain of the nonvolatile memory cell, A plurality of source lines connected to the sources of the nonvolatile memory cells, And a word decoder for activating the word line in accordance with an address signal, and overlapping a part of the activation period of the word line with each other to execute access operations in parallel when different word lines are sequentially accessed, And a combination of bit lines and source lines connected to the drain and the source of the nonvolatile memory cell are all different. The nonvolatile memory cell of claim 1, wherein the nonvolatile memory cells are connected in series and provided with a plurality of cell groups arranged in a wiring direction of the word line. A nonvolatile semiconductor memory according to claim 1, wherein a pair of bit lines are wired in a zigzag form while crossing each other. The method of claim 2, wherein each cell group includes a plurality of pairs of nonvolatile memory cells having sources connected to each other. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile memory cell pairs opposed to each other are connected to different source lines. The method of claim 3, wherein a source region in which the source is formed and a drain region in which the drain are formed are alternately formed between the word lines. In each of said cell group pairs, a pair of said source lines connected to the sources of said non-volatile memory cell pairs opposed to each other are wired on said source region and said drain region, respectively. . The method of claim 4, wherein the source line on the drain region has a protrusion protruding toward the source region, The source line on the drain region is wired using a wiring layer below the source line on the source region. The method of claim 2, wherein each cell group includes a plurality of pairs of nonvolatile memory cells having sources connected to each other. A nonvolatile semiconductor memory according to claim 1, wherein the source of each of the nonvolatile memory cell pairs facing each other is formed by a common diffusion layer. The contact device according to claim 6, further comprising: a contact portion formed between the cell group pairs for connecting the source line formed using a wiring layer to the diffusion layer, And each of said source lines is connected to said diffusion layer via said contact portion. 8. The method of claim 7, wherein in each cell group pair, the nonvolatile memory cell pairs facing each other are connected to different source lines, A nonvolatile semiconductor memory, characterized in that the contact portions formed along the wiring direction of the word lines are connected to one and the other source lines every other. 2. A source decoder according to claim 1, further comprising a source decoder for setting a source line connected to a nonvolatile memory cell to be accessed to a ground voltage and setting another source line to a floating state when the memory cell is accessed. Nonvolatile semiconductor memory. 2. A column decoder according to claim 1, further comprising a column decoder for setting a bit line connected to a nonvolatile memory cell to be accessed to a drain voltage and setting another bit line to a floating state when the memory cell is accessed. Nonvolatile semiconductor memory.

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