JP2020194610A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device that writes data to second memory cells by using a write circuit for first memory cells without lowering a write margin.SOLUTION: A semiconductor storage device includes: a plurality of first memory cells that store data according to a resistance value of a first resistance element; a second memory cell that stores data set in the semiconductor storage device according to a resistance value of a second resistance element; a plurality of first bit lines and a plurality of first source lines connected to a plurality of first memory cells; a write circuit that outputs the data to be written to the plurality of first memory cells or the second memory cell; a first switch circuit that connects the write circuit to the plurality of first bit lines and the plurality of first source lines in a write operation of writing data to the second memory cell; and a second switch circuit for connecting the plurality of first bit lines and the plurality of first source lines to the second memory cell in the write operation.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor storage device.

Some semiconductor storage devices have a redundant memory cell that operates in place of a defective memory cell and an address information storage unit that stores a defective address indicating a defective memory cell in order to improve the yield, which is a non-defective rate. Have. When the address supplied from the outside matches the defective address stored in the address information storage unit, this type of semiconductor storage device accesses the redundant memory cell instead of the defective memory cell when there is a defect. Works fine.

Further, some non-volatile semiconductor storage devices having redundant memory cells have a normal memory cell for storing data supplied from the outside and an information memory cell for storing a defective address or the like. Then, the normal bit line connected to the normal memory cell and the information bit line connected to the information memory cell are connected via the selection transistor. In this type of non-volatile semiconductor storage device, writing of a bad address or the like to an information memory cell is usually performed via a bit line and a selection transistor using a data writing circuit for the normal memory cell. Further, reading of a defective address or the like from an information memory cell is executed using a reading circuit dedicated to the information memory cell (see, for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2010-17210 JP-A-2002-150789

When writing a bad address or the like to an information memory cell using a write circuit for a normal memory cell, it is not necessary to provide a write circuit dedicated to the information memory cell, so that the circuit scale of the semiconductor storage device is reduced. To. On the other hand, when a defective address or the like is transferred from a writing circuit for a normal memory cell to an information memory cell via a normal bit line and a selection transistor, the larger the load such as the wiring resistance of the normal bit line, the more information such as the defective address or the like. The write margin to the memory cell is reduced.

In one aspect, it is an object of the present invention to utilize a write circuit for a first memory cell to write data to a second memory cell without lowering the write margin.

According to one viewpoint, the semiconductor storage device includes a first resistance element whose resistance value changes due to a writing operation, and a plurality of first memories for storing data according to the resistance value of the first resistance element. A cell, a second memory cell including a second resistance element whose resistance value changes according to a writing operation, and a second memory cell for storing data set in the semiconductor storage device according to the resistance value of the second resistance element. Outputs a plurality of first bit lines and a plurality of first source lines connected to the plurality of first memory cells, and data to be written to the plurality of first memory cells or the second memory cell. A write circuit and a first switch circuit that connects the write circuit to the plurality of first bit lines and the plurality of first source lines in a write operation for writing data to the second memory cell. In a writing operation for writing data to the second memory cell, a second switch circuit for connecting the plurality of first bit lines and the plurality of first source lines to the second memory cell. Have.

In one aspect, the present invention can utilize a write circuit for a first memory cell to write data to a second memory cell without lowering the write margin.

It is a block diagram which shows an example of the semiconductor storage device in one Embodiment. It is a circuit diagram which shows an example of the semiconductor storage device in another embodiment. It is a block diagram which shows an example of the arrangement of the circuit of the semiconductor storage device of FIG. It is a block diagram which shows an example of the power supply circuit of FIG. It is a waveform diagram which shows an example of the operation of the power supply circuit of FIG. It is a circuit diagram which shows an example of the layout of the ROM column switch of FIG. It is a circuit diagram which shows an example of the control circuit which controls the ROM column switch of FIG. It is a circuit diagram which shows an example of the ROM read circuit of FIG. It is a timing diagram which shows an example of the operation of the ROM read circuit of FIG. It is a circuit diagram which shows an example of the column switch of FIG. It is a circuit diagram which shows the example in which one ROM memory cell is provided corresponding to a memory cell array. It is a circuit diagram which shows an example of the column control circuit which controls the column switch of the memory cell array of FIG. It is a circuit diagram which shows the continuation of the column control circuit of FIG. It is a circuit diagram which shows the example in which two ROM memory cells are provided corresponding to a memory cell array. It is a circuit diagram which shows an example of the column control circuit which controls the column switch of the memory cell array of FIG. It is a circuit diagram which shows the example in which 8 ROM memory cells are provided corresponding to a memory cell array. It is a circuit diagram which shows the continuation of FIG. It is a circuit diagram which shows an example of the column control circuit which controls the column switch of the memory cell array of FIG. 16 and FIG. It is explanatory drawing which shows an example of the writing operation of the ROM memory cell of the semiconductor storage device of FIG. It is explanatory drawing which shows an example of the verification operation of the ROM memory cell of the semiconductor storage device of FIG. It is explanatory drawing which shows an example of the reading operation of the ROM memory cell of the semiconductor storage device of FIG. It is a block diagram which shows an example of the arrangement of the circuit of another semiconductor storage device. It is a block diagram which shows an example of the arrangement of the circuit of the semiconductor storage device in another embodiment. It is a block diagram which shows an example of the arrangement of the circuit of another semiconductor storage device.

Hereinafter, embodiments will be described with reference to the drawings. In the following, the same code as the signal name is used for the signal line through which information such as a signal is transmitted, the same code as the voltage name is used for the voltage line, and the same code as the power supply name is used for the power supply line. ..

FIG. 1 shows an example of a semiconductor storage device according to an embodiment. For example, the semiconductor storage device 100 shown in FIG. 1 is a resistance change type memory. The semiconductor storage device 100 has a plurality of memory cells 1a, memory cells 1b, switch circuits 2a and 2b, switch control circuits 3a and 3b, write circuits 4 and read circuits 5a and 5b. Further, the semiconductor storage device 100 has a plurality of bit lines BL (BL0, BL1) and a plurality of source lines SL (SL0, SL1) connected to the memory cell 1a, respectively.

The memory cell 1a is an example of the first memory cell, and stores data written from the outside of the semiconductor storage device 100, for example. The memory cell 1b is an example of a second memory cell, and stores, for example, data for adjusting the characteristics of the internal circuit of the semiconductor storage device 100. The switch circuit 2a is an example of the first switch circuit, and the switch circuit 2b is an example of the second switch circuit. The read circuit 5a is an example of a first read circuit, and the read circuit 5b is an example of a second read circuit. The bit line BL is an example of the first bit line, and the source line SL is an example of the first source line.

The write circuit 4 and the read circuit 5a are connected to the switch circuit 2a via the global bit line GBL and the global source line GSL. The memory cell 1b is connected to the switch circuit 2b via the bit line RBL and the source line RSL. The bit line RBL is an example of a second bit line, and the source line RSL is an example of a second source line.

Each memory cell 1a includes a resistance element R whose resistance value changes due to a writing operation, and stores data according to the resistance value of the resistance element R. The memory cell 1b includes a pair of resistance elements R0 and R1 whose resistance values change depending on the writing operation, and stores data according to the resistance values of the resistance elements R0 and R1. For example, the data stored in the memory cell 1b is read out when the power supply of the semiconductor storage device 100 is started, is set in a latch circuit, a register, or the like in the semiconductor storage device 100, and is used for adjusting the characteristics of the internal circuit or the like. .. The resistance element R is an example of the first resistance element, and the resistance elements R0 and R1 are examples of the second resistance element.

The switch circuit 2a has a switch SW for connecting the bit lines BL0 and BL1 to the global bit line GBL, and a switch SW for connecting the source lines SL0 and SL1 to the global source line GSL, respectively. The switch circuit 2b has a switch SW for connecting the bit lines BL0 and BL1 to the bit line RBL, and a switch SW for connecting the source lines SL0 and SL1 to the source line RSL, respectively. The switch control circuit 3a controls the operation of each switch SW of the switch circuit 2a. The switch control circuit 3b controls the operation of each switch SW of the switch circuit 2b.

In the writing operation of writing data to the memory cell 1b, the switch circuits 2a and 2b operate as follows. The switch circuit 2a connects the writing circuit 4 to the plurality of bit lines BL0 and BL1 and the plurality of source lines SL0 and SL1. The switch circuit 2b connects the memory cell 1b to the plurality of bit lines BL0 and BL1 and the plurality of source lines SL0 and SL1 in the writing operation of writing data to the memory cell 1b. For example, the writing operation of the memory cell 1b is executed for each of the resistance elements R0 and R1.

Then, a write voltage is supplied from the write circuit 4 to the memory cell 1b via the plurality of bit lines BL0, BL1, the plurality of source lines SL0, SL1, and the plurality of switch SWs. As a result, the resistance of the write voltage supply line can be reduced as compared with the case where a single supply line is used. Therefore, even when the write voltage is supplied to the memory cell 1b via the plurality of switch circuits 2a and 2b, the desired write voltage is supplied to the resistance element R0 (or R1) while minimizing the voltage drop. be able to. For example, when the write circuit 4 for the memory cell 1a is used for the write operation of the memory cell 1b, the distance between the write circuit 4 and the memory cell 1b tends to be long. Even when the write voltage supply path is long, the desired write voltage can be supplied to the resistance element R0 (or R1). As a result, the resistance value of the resistance element R0 (or R1) can be set to a desired value, and the desired logic can be written to the memory cell 1b.

In the verification operation for verifying the logic of the data written in the memory cell 1b, the switch circuits 2a and 2b operate as follows. The switch circuit 2a connects the read circuit 5a to either the bit line BL or the source line SL. The switch circuit 2b connects the bit line RBL to any of the bit lines BL0 and BL1 and connects the source line RSL to any of the source lines SL0 and SL1.

In the read operation of reading data from the memory cell 1b, the switch circuit 2b cuts off the connection between the bit lines BL0 and BL1 and the source lines SL0 and SL1 and the memory cell 1b. Thereby, in the read operation of the memory cell 1b by the read circuit 5b described later, it is possible to prevent the load of the bit line BL and the load of the source line SL from affecting the read operation.

On the other hand, in the writing operation of writing data to any of the memory cells 1a, the switch circuits 2a and 2b operate as follows. The switch circuit 2a connects the writing circuit 4 to any of the bit lines BL0 and BL1 and the source line SL0 and SL1. The switch circuit 2b cuts off the connection between the bit lines BL0 and BL1 and the source lines SL0 and SL1 and the memory cell 1b (that is, the bit line RBL and the source line RSL). As a result, it is possible to prevent a load such as a bit line RBL and a source line RSL from being connected to the bit line BL and the source line SL during the write operation of the memory cell 1a, and it is possible to prevent a write margin such as insufficient data writing. The decline can be suppressed.

In the verification operation for verifying the logic of the data written in any of the memory cells 1a, the switch circuits 2a and 2b operate as follows. The switch circuit 2a connects the read circuit 5a to either the bit line BL or the source line SL. The switch circuit 2b cuts off the connection between the bit line RBL and the bit lines BL0 and BL1 and the connection between the source line RSL and the source lines SL0 and SL1. As a result, it is possible to prevent a load such as a bit line RBL and a source line RSL from being connected to the bit line BL and the source line SL during the verification operation of the memory cell 1a, and an error occurs in data determination or the like. It can be deterred.

In the read operation of reading data from any of the memory cells 1a, the switch circuits 2a and 2b operate as follows. The switch circuit 2a connects the read circuit 5a to either the bit line BL or the source line SL. The switch circuit 2b cuts off the connection between the bit lines BL0 and BL1 and the source lines SL0 and SL1 and the memory cell 1b. As a result, it is possible to prevent a load such as a bit line RBL and a source line RSL from being connected to the bit line BL and the source line SL during the read operation of the memory cell 1a, and prevent incorrect data from being read. can do.

In this embodiment, the writing circuit 4 for writing data to the memory cell 1a is used to write the data to the memory cell 1b. Further, the verification operation of the memory cell 1b is executed by using the read circuit 5a that reads data from the memory cell 1a. Therefore, the circuit scale of the semiconductor storage device 100 can be reduced as compared with the case where the dedicated writing circuit and verification circuit of the memory cell 1b are provided.

In the writing operation of the memory cell 1a, the writing circuit 4 sets the bit line BL and the source line SL connected to the memory cell 1a to be written to a predetermined voltage difference, and sets the resistance element R of the memory cell 1a to be written. A current is passed to change the resistance value. In the writing operation of the memory cell 1b, the writing circuit 4 sets a plurality of bit lines BL and a plurality of source lines SL to a predetermined voltage difference, and selects a resistance element R0 from the resistance elements R0 and R1 of the memory cell 1b. A current is passed through (or R1) to change the resistance value. In the writing operation of the memory cell 1b, the resistance values of the resistance elements R0 and R1 are set by the writing operation of the resistance element R0 and the writing operation of the resistance element R1, respectively, and a predetermined logic is written to the memory cell 1b.

In the read operation and verify operation of the memory cell 1a, the read circuit 5a supplies a read voltage to the memory cell 1a to be accessed via either the switch circuit 2a and the bit line BL and either the source line SL. Then, the reading circuit 5a determines the data stored in the memory cell 1a to be accessed according to the amount of current flowing through the resistance element R of the memory cell 1a to be accessed. In the verification operation of the memory cell 1b, the read circuit 5a supplies a read voltage to the memory cell 1b via either the switch circuits 2a and 2b and the bit line BL and either the source line SL. Then, the reading circuit 5a determines the logic of the data stored in the resistance element R0 (or R1) according to the amount of current flowing through the resistance element R0 (or R0) of the memory cell 1b.

For example, the readout circuit 5a determines the data stored in the resistance elements R, R0, and R1 by comparing the voltage generated according to the current flowing through the resistance elements R, R0, and R1 with a reference voltage (not shown). .. The data determined by the read circuit 5a in the read operation of the memory cell 1a is output as read data to the outside of the semiconductor storage device 100. The data determined by the read circuit 5a in the verification operation of the memory cells 1a and 1b is used to determine whether or not the resistance elements R, R0, and R1 are set to desired resistance values.

The readout circuit 5b is directly connected to, for example, the resistance elements R0 and R1. In the read operation of reading data from the memory cell 1b, the read circuit 5b sets both ends of the resistance elements R0 and R1 to predetermined voltages, and stores the data in the memory cell 1b according to the amount of current flowing through the resistance elements R0 and R1, respectively. Judge the data. For example, the resistance elements R0 and R1 are set to different resistance values and store complementary logic. In this case, the reading circuit 5b determines the data stored in the memory cell 1b according to the difference in the amount of current flowing through the resistance elements R0 and R1.

Since the data can be read by detecting the current flowing through the resistance elements R0 and R1 directly connected to the read circuit 5b by the read circuit 5b, the data stored in the memory cell 1b can be read in the minimum time. it can. Further, in the writing operation, the resistance value of the resistance element R0 (or R1) can be set to a desired value, so that the reading margin by the reading circuit 5b can be improved, and the reliability of the semiconductor storage device 100 can be improved. Can be improved.

The memory cell 1b may have one resistance element R like the memory cell 1a. In this case, the read circuit 5b determines the data stored in the memory cell 1b by comparing the voltage generated according to the current flowing through the resistance element R with the reference voltage, for example.

As described above, in the embodiment shown in FIG. 1, data is written to the memory cell 1b from the writing circuit 4 via the plurality of bit lines BL0 and BL1 and the plurality of source lines SL0 and SL1. It is executed by supplying. By using the plurality of bit lines BL0 and BL1 and the plurality of source lines SL0 and SL1, the resistance of the write voltage supply path can be reduced as compared with the case where a single supply line is used.

As a result, even when the write voltage is supplied via the plurality of switch circuits 2a and 2b, or when the supply path of the write voltage is long, the increase in the resistance of the supply path is suppressed and the desired write voltage is applied to the resistance element R0. (Or R1) can be supplied. Since the writing circuit 4 for the memory cell 1a can be used to set a desired resistance value of the resistance element R0 (or R1), data can be written to the memory cell 1b without lowering the writing margin.

The write circuit 4 for the memory cell 1a is used to write data to the memory cell 1b, and the read circuit 5a for the memory cell 1a is used to execute the verify operation of the memory cell 1b. The circuit scale of the device 100 can be reduced.

By reading data from the memory cell 1b by the read circuit 5b dedicated to the memory cell 1b directly connected to the resistance elements R0 and R1, the memory cell does not go through the bit line BL, the source line SL and the switch circuits 2a and 2b. Data can be read from 1b. As a result, the data stored in the memory cell 1b can be read out in the minimum time.

Further, by shutting off the switch SW of the switch circuit 2b during the read operation of the memory cell 1b, it is possible to prevent the load of the bit line BL and the load of the source line SL from affecting the read operation of the memory cell 1b. it can. By shutting off the switch SW of the switch circuit 2b during the writing operation of the memory cell 1a, it is possible to prevent the load of the bit line RBL and the source line RSL from being connected to the bit line BL and the source line SL, and data. It is possible to suppress the occurrence of insufficient writing of.

By shutting off the switch circuit 2b during the read operation of the memory cell 1a, it is possible to prevent loads such as the bit line RBL and the source line RSL from being connected to the bit line BL and the source line SL during the read operation. it can. Similarly, by shutting off the switch SW of the switch circuit 2b during the verification operation of the memory cell 1a, a load such as the bit line RBL and the source line RSL is connected to the bit line BL and the source line SL during the verification operation. Can be deterred. Therefore, it is possible to prevent an error in data determination or the like from occurring during the read operation and the verify operation.

FIG. 2 shows an example of a semiconductor storage device according to another embodiment. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor storage device 100A includes a memory cell array 20 including a plurality of memory cells 10 arranged in a matrix, a column switch 30, a write driver 40, and a read circuit 50. Further, the semiconductor storage device 100A includes a ROM memory cell 12, a ROM read circuit 60, and a ROM column switch 70.

The memory cell 10 is an example of a first memory cell, and the ROM memory cell 12 is an example of a second memory cell. The column switch 30 is an example of a first switch circuit, and the ROM column switch 70 is an example of a second switch circuit. The write driver 40 is an example of a writing circuit. The read circuit 50 is an example of a first read circuit, and the ROM read circuit 60 is an example of a second read circuit.

Each memory cell 10 has a resistance element R whose resistance value changes according to a writing operation and a transfer transistor T, and stores 1-bit data. That is, the semiconductor storage device 100A is a resistance change type memory. For example, the transfer transistor T is an n-channel MOS (Metal-Oxide Semiconductor) transistor. One end of the resistance element R is connected to one end (source or drain) of the transfer transistor T, and the other end of the resistance element R is connected to the source line SL (any of SL0, SL1, SL2, SL3). The other end of the transfer transistor T is connected to the bit line BL (any of BL0, BL1, BL2, BL3), and the gate of the transfer transistor T is connected to the word line WL (any of WL0, WL1, WL2, WL3). Be connected.

The number of memory cells 10 provided in the memory cell array 20 is not limited to the example shown in FIG. 2, and the number of bit lines BL and source lines SL is not limited to the example shown in FIG. 2 as long as it is 2 or more. .. The number of word line WLs is not limited to the example shown in FIG. Further, FIG. 2 shows an example of a circuit configuration corresponding to, for example, one data terminal I / O. For example, as shown in FIG. 3, it has a 64-bit data terminal I / O0-I / O63. The semiconductor storage device 100A has 64 circuit configurations shown in FIG.

In the various transistors shown in FIG. 2, the thick line shown in the channel region facing the gate indicates, for example, that the gate insulating film is a high withstand voltage type thicker than that of a standard transistor. For example, the semiconductor storage device 100A receives the power supply voltage VCS at the power supply terminal, and operates by using the same power supply voltage VPPY as the power supply voltage VCS, the power supply voltage VPPX higher than the power supply voltage, and the power supply voltage VDD lower than the power supply voltage VCS. To do. A high withstand voltage type is used for a transistor that receives either a power supply voltage VPPPY or VPPX at the gate, source, or drain.

In a state where the memory cell 10 can be accessed after the power supply of the semiconductor storage device 100A is started, for example, the power supply voltage VCS and VPPPY are 2.5V, the power supply voltage VPPX is 3.3V, and the power supply voltage VDD is 1.2V. Is. The power supply voltages VCS, VPPPY, VPPX, and VDD may have voltages different from those described above as long as the magnitude relation of the voltage values is VPPX> VPPPY = VCS> VDD. The power supply voltage VPPX is preferably higher than the power supply voltage VPPY plus the threshold voltage of the n-channel MOS transistor.

The column switch 30 includes a CMOS (Complementary MOS) transmission gate that connects the bit line BL to the global bit line GBL and a CMOS transmission gate that connects the source line SL to the global source line GSL. The CMOS transmission gate has a configuration in which the source / drain of the n-channel MOS transistor and the source / drain of the p-channel MOS transistor are connected to each other. Each CMOS transmission gate is turned on (conducting) or off (blocking) by a column selection signal YD (any of YD0, YD1, YD2, YD3). An example of the column switch 30 is shown in FIG. Examples of the column control circuit that generates the column selection signal YD are shown in FIGS. 12 and 13.

The write driver 40 has a switch 40a for connecting the global bit line GBL to the ground line VSS and a switch 40b for connecting the global source line GSL to the power supply line VPPY in response to the write control signal WR0. Further, the write driver 40 has a switch 40c for connecting the global bit line GBL to the power supply line VSS and a switch 40d for connecting the global source line GSL to the ground line VSS according to the write control signal WR1. For example, switches 40a and 40d are n-channel MOS transistors, and switches 40b and 40c have CMOS transmission gates. In FIG. 2 and the like, the p-channel MOS transistor is distinguished from the n-channel MOS transistor by marking the gate with a circle indicating negative logic. The CMOS transmission gates of the switches 40b and 40c are the same as the CMOS transmission gates of the column switch 30.

The readout circuit 50 includes a switch 50a for connecting the global bit line GBL to the ground line, a sense amplifier 52, and a switch 50b for connecting the global source line GSL to the sense amplifier 52. The switches 50a and 50b have an n-channel MOS transistor and are controlled by a read enable signal REN.

The sense amplifier 52 compares the voltage appearing in the global source line GSL with the reference voltage VREF according to the current flowing through the resistance element R of the selected memory cell 10 in the read operation and the verify operation described later, and thereby the memory cell 10 Read the logic held by. The sense amplifier 52 is also used for the verification operation of the memory cell 12. The read operation will be described with reference to FIGS. 9 and 21, and the verify operation will be described with reference to FIG.

The ROM memory cell 12 has two resistance elements R0 and R1 for storing complementary logic and two transfer transistors T0 and T1. The ROM memory cell 12 is equivalent to two memory cells 10. The gate of the transfer transistor T0 is connected to the word line RWL0, and the gate of the transfer transistor T1 is connected to the word line RWL1. In the following, when the word lines RWL0 and RWL1 will be described without distinction, they may be simply referred to as word lines RWL. The ROM memory cell 12 is connected to the ROM read circuit 60 via the bit enable lines RBE0 and RBE1. The bit enable line RBE0 is connected to the connection node between the resistance element R0 and the transfer transistor T0, and the bit enable line RBE1 is connected to the connection node between the resistance element R1 and the transfer transistor T1.

The ROM memory cell 12 stores 1 bit by two resistance elements R0 and R1. For example, the ROM memory cell 12 stores logic 1 when the resistance value of the resistance element R0 is higher than the resistance value of the resistance element R1, and logic 0 when the resistance value of the resistance element R1 is higher than the resistance value of the resistance element R0. Remember. For example, the ROM memory cell 12 is provided corresponding to four sets of bit line BL / source line SL. Hereinafter, one set of bit line BL / source line SL is also referred to as one column.

The ROM memory cell 12 may have three or more resistance elements. When the ROM memory cell 12 has an odd number of resistance elements, the logic of the data read from the ROM memory cell 12 may be determined by, for example, a majority vote. Further, when the ROM memory cell 12 has four resistance elements, complementary logic may be stored for each of the two resistance elements R. By arranging a plurality of resistance elements in the ROM memory cell 12 and increasing the amount of information stored in the ROM memory cell 12, the reliability of the data can be improved as compared with the data stored in the ROM memory cell 10. ..

For example, if the semiconductor storage device 100A has 32 data terminals I / O and 32 columns are provided for each data terminal I / O, the memory cell array 20 has 1024 columns. In this case, in the circuit configuration of FIG. 2, a maximum of 256 ROM memory cells 12 can be provided adjacent to the memory cell array 20.

For example, the ROM memory cell 12 may store trimming information for adjusting the internal voltage generated by the power supply circuit 80 (FIG. 3) provided in the semiconductor storage device 100A. Further, the semiconductor storage device 100A may have a redundant memory cell for relieving the defective memory cell 10 and may have a switching circuit (relief circuit) for operating the redundant memory cell instead of the defective memory cell 10. Good. In this case, the ROM memory cell 12 may store the address (defective address) of the defective memory cell 10. Further, the ROM memory cell 12 may store trimming information for adjusting the timing (delay amount) of various control signals, or may store an identification code, manufacturing information, or the like of the semiconductor storage device 100A.

As described with reference to FIG. 5, the ROM memory cell 12 is read-accessed when the power supply of the semiconductor storage device 100A is started, and the data stored in advance in the ROM memory cell 12 is read out by the ROM read circuit 60. The ROM read circuit 60 operates when the power supply is started, and determines the logic of the data held by the ROM memory cell 12 according to the currents flowing through the two resistance elements R0 and R1 of the ROM memory cell 12, respectively. Is output as a data output signal SAOUT. An example of the ROM read circuit 60 is shown in FIG. 8, and an example of the operation of the ROM read circuit 60 is shown in FIG.

The ROM column switch 70 has four switches 70a, 70b, 70c, and 70d that connect each bit line BL and the bit line RBL connected to the ROM memory cell 12. Further, the ROM column switch 70 has four switches 70e, 70f, 70g, and 70h for connecting each source line SL and the source line RSL connected to the ROM memory cell 12. For example, each switch 70a-70h is an n-channel MOS transistor. The switches 70a, 70b, 70c, 70e, 70f and 70g operate based on the column selection signal RYDVW, and the switches 70d and 70h operate based on the column selection signal RYDW.

For example, both the column selection signals RYDVW and RYDW are set to high levels during the write operation of the ROM memory cells 12, and the column selection signals RYDVW are set to high levels during the verify operation of the ROM memory cells 12. As a result, as described with reference to FIG. 19, the eight switches 70a-70h are turned on during the writing operation of the ROM memory cell 12, and the switch 70d, as described with reference to FIG. 20, during the verifying operation of the ROM memory cell 12. 70h turns on.

The "ROM" added to the ROM memory cell 12, the ROM read circuit 60, and the ROM column switch 70 indicates that the ROM memory cell 12 functions as a ROM (Read Only Memory) after the semiconductor storage device 100A is shipped. Shown. For example, as will be described later, data is written to the ROM memory cell 12 in the test process of the semiconductor storage device 100A. In the test process, the write operation of writing data to the ROM memory cell 12 is executed using the write driver 40, and the verify operation of confirming the data written to the ROM memory cell 12 is executed using the read circuit 50. To.

FIG. 3 shows an example of the arrangement of the circuit of the semiconductor storage device 100A of FIG. That is, FIG. 3 shows an example of the chip layout of the semiconductor storage device 100A. In FIG. 3, for example, two circuit groups including a ROM read circuit 60, a ROM memory cell 12, a memory cell array 20, a column switch 30, a read circuit 50, and a write driver 40 are a power supply circuit 80 and a data input / output circuit 90. Placed between. For example, the semiconductor storage device 100A has a circuit group corresponding to the lower 32-bit data terminal I / O0-I / O31 and a circuit group corresponding to the upper 32-bit data terminal I / O32-I / O63. Have.

Various control circuits such as a low decoder 22 for selecting a word line WL are arranged between the memory cell array 20 of the two circuit groups. For example, in the area between the low decoder 22 and the power supply circuit 80, a low decoder for selecting the word line RWL, a control signal generation circuit for operating the ROM read circuit 60, and the like may be arranged. .. Further, in the area between the low decoder 22 and the data input / output circuit 90, a column decoder for selecting the column switch 30, a control circuit for controlling the column decoder, a control circuit for controlling the read circuit 50, and a write driver 40 A control circuit for controlling the above may be arranged.

The signal line RDT connected to the power supply circuit 80 indicates a transfer path of the data RDT read from the ROM memory cell 12. For example, the data RDT may be transferred to the power supply circuit 80 as trimming information for adjusting the power supply voltages VPPX and VDD. Further, when the semiconductor storage device 100A has a redundant memory cell for relieving the defective memory cell 10, the data RDT may indicate a defective address indicating the defective memory cell 10. The defective address may indicate a word line WL or a bit line BL to which a defective memory cell 10 is connected. Then, the data RDT indicating the defective address may be transferred to a switching circuit (relief circuit) (not shown) that operates a redundant memory cell instead of the defective memory cell 10. On the other hand, the signal line DT connected to the data input / output circuit 90 indicates a transfer path of the data signal DT read / written to / from the memory cell 10.

The semiconductor storage device 100A can write data to the ROM memory cell 12 by using the write driver 40 used for the normal writing operation of the memory cell 10. Further, the semiconductor storage device 100A can execute the verification operation of the ROM memory cell 12 by using the read circuit 50 used for the read operation of the normal memory cell 10. Therefore, the chip size of the semiconductor storage device 100A can be reduced as compared with the case where the write driver for the ROM memory cell 12 and the sense amplifier for verification are provided. Further, it is possible to simplify the control of the writing operation and the verifying operation of the ROM memory cell 12.

The thick dashed line frame around the memory cell array 20, the ROM column switch 70, and the ROM memory cell 12 indicates a dummy area DMY in which the dummy memory cell is arranged. The dummy memory cell is arranged in order to reduce the influence of halation on the memory cell 10 in which the transistors T and the like are arranged densely as compared with the area around the memory cell array 20 in the exposure process. Halation generated in the exposure process may deform the pattern of the device and deteriorate the electrical characteristics of the device.

FIG. 4 shows an example of the power supply circuit 80 of FIG. The power supply circuit 80 includes a low voltage detection circuit 82, a step-down circuit 84, a ROM read control circuit 86, and a boost-up circuit 88. The low voltage detection circuit 82 is an example of a power supply detection circuit, the ROM read control circuit 86 is an example of a read control circuit, and the booster circuit 88 is an example of an internal voltage generation circuit.

When the power supply voltage VCS (external power supply voltage) supplied from the outside of the semiconductor storage device 100A is equal to or lower than a predetermined voltage, the low voltage detection circuit 82 outputs a low-level start signal STT, and the power supply voltage VCS sets the predetermined voltage. If it exceeds, a high level start signal STT is output. The start signal STT is supplied to the step-down circuit 84 and the ROM read control circuit 86. The step-down circuit 84 steps down the power supply voltage VCS while the start signal STT is at a high level to generate the power supply voltage VDD.

The ROM read control circuit 86 operates based on the power supply voltage VDD, and based on the change of the start signal STT from the low level to the high level, the latch signal LATVSS which is maintained at the low level for a predetermined period and then changes to the high level. Generate. Further, the ROM read control circuit 86 generates a precharge signal PREB, an output control signal SAOUTB, and a sense amplifier enable signal SAEN. Further, the ROM read control circuit 86 generates a permission signal VPEN based on setting the latch signal LATVSS to a high level, and outputs it to the booster circuit 88.

The booster circuit 88 starts operation based on the permission signal VPEN output from the ROM read control circuit 86, and generates the power supply voltage VPPX using the power supply voltages VCS and VDD. The power supply voltage VPPX is an example of the internal voltage. The power supply circuit 80 may generate a reference voltage VREF used in the sense amplifier 52.

The power supply circuit 80 outputs the power supply voltage VCS received at the power supply terminal as the power supply voltage VPPY to the column switch 30, the light driver 40, the sense amplifier 52, and the like. The relationship between the power supply voltages VPPX, VCS, VPPPY, and VDD is VPPX> VCS = VPPPY> VDD. For example, the power supply voltage VPPX is used for high level voltages of word lines WL, RWL, column selection signals RYDW, RYDVW. The power supply voltage VPPY is used for high level voltages such as the column selection signal YD, the write control signals WR0 and WR1, and the read enable signal REN.

When the semiconductor storage device 100A receives the power supply voltage VDD at the power supply terminal, the power supply circuit 80 may boost the power supply voltage VDD to generate the power supply voltages VPPY and VPPX. In this case, the low voltage detection circuit 82 , Operates based on power supply voltage VDD. Further, when the semiconductor storage device 100A receives the power supply voltage VPPX at the power supply terminal, the power supply circuit 80 may step down the power supply voltage VPPX to generate the power supply voltages VPPY and VDD. In this case, the low voltage detection circuit 82 , Operates based on the power supply voltage VPPX. Further, when the semiconductor storage device 100A receives the power supply voltages VCS, VDD, and VPPX at the plurality of power supply terminals, the power supply circuit 80 does not have to have the step-down circuit 84 and the step-up circuit 88.

FIG. 5 shows an example of the operation of the power supply circuit 80 of FIG. FIG. 5 shows an example of the operation of the semiconductor storage device 100A at the time of starting up the power supply. First, when the power supply voltage VCS is supplied to the semiconductor storage device 100A (PON), the power supply voltages VDD, VPPPY, VPPX and the voltage of the latch signal LATVSS rise following the power supply voltage VCS (FIG. 5A). , (B)).

For example, when the power supply voltage VCS exceeds 0.8 V, the low voltage detection circuit 82 changes the start signal STT from low level to high level (FIG. 5 (c)). Note that 0.8V is a voltage higher than the minimum voltage at which the ROM read control circuit 86 can operate by a predetermined value. After that, the voltage of the start signal STT rises following the power supply voltage VCS (FIG. 5 (d)).

The step-down circuit 84 starts operation when the power supply voltage VCS exceeds 0.8 V, and generates the power supply voltage VDD (FIG. 5 (e)). For example, the step-down circuit 84 generates the power supply voltage VDD by dividing the power supply voltage VCS into resistors.

The ROM read control circuit 86 sets the latch signal LATVSS to a low level for a predetermined period of time based on the change of the start signal STT to a high level, and then sets it to a high level (FIG. 5 (f)). The low level period of the latch signal LATVSS is the period for reading data from the ROM memory cell 12. The data read period from the ROM memory cell 12 is set before the power supply voltages VCS, VPPY, VDD, and VPPX reach the specified voltage.

As a result, before the power supply voltages VCS, VPPY, VDD, and VPPX reach the specified voltage and the access to the memory cell 10 is started by the user system or the like equipped with the semiconductor storage device 100A, trimming information, defective addresses, and the like are input. It can be set to a predetermined circuit. As a result, data can be read and written to and from the memory cell MC without causing the semiconductor storage device 100A to malfunction.

The ROM read control circuit 86 generates a precharge signal PREB, an output control signal SAOUTB, and a sense amplifier enable signal SAEN based on setting the latch signal LATVSS to a low level. Examples of the precharge signal PREB, the output control signal SAOUTB, and the sense amplifier enable signal SAEN will be described with reference to FIG. Further, the ROM read control circuit 86 generates a permission signal VIPEN based on setting the latch signal LATVSS to a high level. For example, the ROM read control circuit 86 may have a delay circuit for generating a low level period of the latch signal LATVSS.

The booster circuit 88 starts operation based on the permission signal VPEN output from the ROM read control circuit 86 after the latch signal LATVSS changes to a high level, and generates a power supply voltage VPPX (FIG. 5 (g)).

By operating the booster circuit 88 after the reading of data from the ROM memory cell 12 is completed and the latch signal LATVSS reaches a high level, the booster circuit 88 operates in a period when the power supply voltage VDD is lower than 1.2 V. Power supply fluctuation can be suppressed. As a result, for example, even when the power supply fluctuates due to the operation of the booster circuit 88, the data can be read from the ROM memory cell 12 before the power supply fluctuates, and the data read margin from the ROM memory cell 12 decreases. Can be deterred.

Further, by generating the permission signal VPEN by the ROM read control circuit 86 that controls the reading of data from the ROM memory cell 12, the permission signal VPEN can be generated in synchronization with the completion of reading. As a result, it is possible to prevent the booster circuit 88 from starting operation while reading data from the ROM memory cell 12.

FIG. 6 shows an example of the layout of the ROM column switch 70 of FIG. The switches 70a-70h and the ROM memory cell 12 are formed by utilizing the repeating pattern of the layout of the memory cell 10 in which the memory cell array 20 is arranged. That is, the switches 70a-70h and the ROM memory cell 12 are arranged in an area adjacent to the memory cell array 20 using the same layout pattern as the memory cell 10. Normally, the elements of the memory cell array 20 are arranged more densely than the elements of peripheral circuits such as control circuits provided around the memory cell array 20. Therefore, by providing the switches 70a-70h and the ROM memory cell 12 using the same layout pattern as the memory cell 10, an increase in the layout area can be minimized.

The resistance elements R0 and R1 of the ROM memory cell 12 shown in FIG. 6 and the like and the resistance element R of the memory cell 10 shown in FIG. 2 and the like are formed above the formation regions of the transfer transistors T0, T1 and T. In each figure, the resistance elements R0, R1, and R are described for the sake of clarity, but the layout of the transistor area of the ROM memory cell 12 and the memory cell 10 is the layout of the ROM column switch 70 shown in FIG. It is similar to the layout of the transistor.

The shaded area shown in FIG. 6 schematically shows a dummy area DMY in which a dummy memory cell is formed. As shown in FIG. 6, the ROM column switch 70 and the ROM memory cell 12 are formed by utilizing the repeating pattern of the layout of the memory cell 10. Therefore, the dummy region DMY can be formed so as to cover the periphery of the formation regions of the memory cell array 20, the ROM column switch 70, and the ROM memory cell 12. As a result, the layout area of the dummy memory cell can be reduced as compared with the case where the ROM column switch 70 and the memory cell array 20 are arranged apart from each other and the dummy area DMY is provided separately, and the chip of the semiconductor storage device 100A can be reduced. The size can be reduced.

FIG. 7 shows an example of a control circuit that controls the ROM column switch 70 of FIG. The control circuit 72 that controls the ROM column switch 70 includes a level shifter 74 that outputs a column selection signal RYDW, a level shifter 76 that outputs a column selection signal RYDVW, and a logic circuit 78 that is connected to the inputs of the level shifters 74 and 76.

The logic circuit 78 is a high-level ROM during a writing operation of writing data to any of the resistance elements R0 and R1 of the ROM memory cell 12 and a verification operation of verifying the data writing level of the resistance elements R0 and R1. Receive access signal RACC. Then, the logic circuit 78 outputs the control signals pRYDW and pRYDVW of the same logic level as the write signal WR to the level shifters 74 and 76, respectively, in response to the write signal WR set to a high level during the write operation. Further, the logic circuit 78 outputs a control signal pRYDVW having the same logic level as the verify signal VRFY to the level shifter 76 in response to the verify signal VRFY set to a high level during the verify operation.

The ROM access signal RACC, the write signal WR, and the verify signal VRFY are generated by the ROM access control circuit provided in the area adjacent to the ROM column switch 70 shown in FIG. The ROM access control circuit operates during the write operation period and the verify operation period of the ROM memory cell 12 shown in FIG.

The level shifter 74 converts the high level of the control signal pRYDW from the power supply voltage VDD to the power supply voltage VPPX and outputs it as the column selection signal RYDW. The level shifter 76 converts the high level of the control signal pRYDVW from the power supply voltage VDD to the power supply voltage VPPX and outputs it as the column selection signal RYDVW.

According to the logic of the logic circuit 78, the column selection signals RYDW and RYDVW are set to high levels during the writing operation of the ROM memory cell 12. During the verify operation of the ROM memory cell 12, the column selection signal RYDVW is set to a high level and the column selection signal RYDW is set to a low level. As a result, as described with reference to FIG. 19, all the column switches 70a-70h are turned on in the writing operation of the ROM memory cell 12, and as described in FIG. 20, the column switch is turned on in the verifying operation of the ROM memory cell 12. The 70d and 70h are turned on, and the column switches 70a-70c and 70e-70g are turned off.

FIG. 8 shows an example of the ROM read circuit 60 of FIG. The ROM read circuit 60 includes a latch unit 61, a power switch 62, a ground switch 63, precharge units 64 and 65, and output units 66 and 67. The resistance elements R0 and R1 of the ROM memory cell 12 are arranged between the latch portion 61 and the ground switch 63. The ROM read circuit 60 operates by receiving the power supply voltage VDD (for example, 1.2V).

The latch portion 61 has a pair of CMOS inverters 610, 611 in which one output is connected to the other input. The CMOS inverters 610 and 611 are examples of inverting circuits. The output of the CMOS inverter 610 is connected to the precharge unit 64 via the storage node XC. The output of the CMOS inverter 611 is connected to the precharge unit 65 via the storage node XT.

The source of the n-channel MOS transistor 610a of the CMOS inverter 610 is connected to the ground switch 63 via the resistance element R0 of the ROM memory cell 12 and the source line RSL. The source of the n-channel MOS transistor 611a of the CMOS inverter 611 is connected to the ground switch 63 via the resistance element R1 of the ROM memory cell 12 and the source line RSL. In this way, the resistance elements R0 and R1 are arranged in the ROM read circuit 60. It can be said that the ROM read circuit 60 includes resistance elements R0 and R1.

The latch unit 61, the power switch 62, the precharge units 64, 65, and the output units 66, 67 that operate in response to the power supply voltage VDD are the bit enable lines RBE0, RBE1, etc. that are set to the power supply voltage VPPY during the writing operation. It is electrically separated. Since the n-channel MOS transistors 610a and 611a of the latch portion 61 function as separation transistors that separate the ROM read circuit 60 from the supply line of the power supply voltage VDDY, it is not necessary to newly provide a separation switch or the like.

For example, the ground switch 63 has an n-channel MOS transistor 63a and operates based on the sense amplifier enable signal SAEN received at the gate, and connects the resistance elements R0 and R1 to the ground line VSS, or the resistance elements R0 and R1. And the ground wire VSS are cut off.

The source of the p-channel MOS transistor 610b of the CMOS inverter 610 and the source of the p-channel MOS transistor 611b of the CMOS inverter 611 are connected to the power switch 62. For example, the power switch 62 has a p-channel MOS transistor and operates based on the latch signal LATVSS received at the gate, and connects the power supply line VDD to the latch portion 61 or the power supply line VDD and the latch portion 61. To shut off. The power line VDD is an example of the first power line.

The precharge unit 64 has a p-channel MOS transistor 64a and an n-channel MOS transistor 64b connected in series between the power supply line VDD and the ground line VSS. The gate of the p-channel MOS transistor 64a receives the precharge signal PREB, and the gate of the n-channel MOS transistor 64b receives the latch signal LATVSS.

The precharge unit 65 has a p-channel MOS transistor 65a and an n-channel MOS transistor 65b connected in series between the power supply line VDD and the ground line VSS. The gate of the p-channel MOS transistor 65a receives the precharge signal PREB, and the gate of the n-channel MOS transistor 65b receives the latch signal LATVSS.

The output unit 66 has a noah gate 66a, and the output unit 67 has a noah gate 67a. The Noah Gate 66a receives the output control signal SAOUTB and the voltage of the storage node XC. Since the Noah Gate 66a is not used in the read operation of the ROM memory cell 12, the following description will be omitted. The Noah Gate 67a receives the output control signal SAOUTB and the voltage of the storage node XT, and outputs the data output signal SAOUT.

The size of the arrow attached to the n-channel MOS transistors 610a and 611a in FIG. 8 indicates the size of the amount of current flowing through the ROM read circuit 60 when reading data from the ROM memory cell 12. In this example, for example, the ROM memory cell 12 stores logic 1 (a state in which the resistance value of the resistance element R1 is lower than the resistance value of the resistance element R0), and the amount of current flowing through the resistance element R1 is the resistance element. It is larger than the amount of current flowing through R0.

In the read operation of reading data from the ROM memory cell 12, the ROM read circuit 60 does not use the word lines RWL0 and RWL1 connected to the ROM memory cell 12, and the word lines RWL0 and WRL1 are non-selected levels (low level). Is set to. Therefore, as described with reference to FIG. 5, when the power supply is started, data can be read from the ROM memory cell 12 before the power supply voltage VPPX, which is the selection level (high level) of the word lines RWL0 and RWL1, is generated. it can. Further, the time required for the power supply voltage VPPX, which is the high level voltage of the word lines RWL0 and RWL1, to reach a predetermined voltage (for example, 3.3V) is such that the other power supply voltages VDD and VPPY have a predetermined voltage (for example, 3.3V). It is longer than the time it takes to reach 1.2V and 2.5V). Therefore, by reading the data without driving the word lines RWL0 and RWL1, the reading time can be shortened as compared with the case where the word lines RWL0 and RWL1 are driven to read the data.

FIG. 9 shows an example of the operation of the ROM read circuit 60 of FIG. As described with reference to FIG. 8, the resistance value of the resistance element R1 is lower than the resistance value of the resistance element R0.

First, the latch signal LATVSS is set to the low level and the precharge signal PREB is set to the low level based on the arrival of the power supply voltage VCS of 0.8 V (FIGS. 9A and 9B).

Before the precharge signal PREB changes to the low level, the bit enable lines RBE0, RBE1 and the source line RSL are set to the low level high impedance state (Hi-Z). Further, before the power supply voltage VCS reaches 0.8 V, the latch signal LATVSS and the precharge signal PREB are set to high levels. When the voltage of the latch signal LATVSS becomes higher than the threshold voltage of the n-channel MOS transistors 64b and 65b due to the increase of the power supply voltage VDD, the n-channel MOS transistors 64b and 65b are turned on and the nodes XC and XT are set to the low level. ..

When the latch signal LATVSS and the precharge signal PREB change to the low level, the p-channel MOS transistors 64b and 65b are turned on by the low level precharge signal PREB, and the storage nodes XC and XT are set to the power supply voltage VDD (FIG. 9 (c). )). At this point, since the power supply voltage VDD is higher than the threshold voltage of the n-channel MOS transistors 610a and 611a, the n-channel MOS transistors 610a and 611a are turned on by the high level of the storage nodes XC and XT. As a result, the voltages of the bit enable lines RBE0 and RBE1 rise (FIG. 9 (d)).

When the voltage of the bit enable lines RBE0 and RBE1 rises, a current flows through the resistance elements R0 and R1 of the ROM memory cell 12, and the voltage of the source line RSL rises (FIG. 9E). The voltages of the bit enable lines RBE0, RBE1 and the source line RSL are set to a voltage lower than the power supply voltage VDD by the threshold voltage of the n-channel MOS transistors 610a and 611a.

Next, the precharge signal PREB and the sense amplifier enable signal SAEN are set to high levels (FIGS. 9 (f) and 9 (g)). The high-level precharge signal PREB turns off the p-channel MOS transistors 64a and 65a of the precharge sections 64 and 65, and the storage nodes XC and XT are set to a high-level high impedance state (FIG. 9 (h)). ). In addition, the ground switch 63 is turned on by the high-level sense amplifier enable signal SAEN.

As a result, a current flows from the storage node XC to the ground wire VSS via the n-channel MOS transistor 63a, the resistance element R0, and the n-channel MOS transistor 610a. Similarly, a current flows from the storage node XT to the ground wire VSS via the n-channel MOS transistor 63a, the resistance element R1 and the n-channel MOS transistor 611a. Then, the voltage of the source line RSL drops (FIG. 9 (i)).

Since the current flowing through the resistance element R1 having a low resistance value is larger than the current flowing through the resistance element R0 having a high resistance value, the voltage of the bit enable line RBE1 drops faster than the voltage of the bit enable line RBE0 (FIG. 9 (j). )). Further, the voltages of the storage nodes XC and XT decrease as the voltages of the bit enable lines RBE0 and RBE1 decrease (FIG. 9 (k)).

Here, similarly to the change in the voltage of the bit enable lines RBE0 and RBE1, the voltage of the storage node XT corresponding to the resistance element R1 having a relatively low resistance value drops faster than the voltage of the storage node XC. Then, when the absolute value of the difference (voltage XT- VDD) between the voltage of the storage node XT and the power supply voltage VDD exceeds the absolute value of the threshold voltage of the p-channel MOS transistor 610b, the p-channel MOS transistor 610b is turned on.

When the p-channel MOS transistor 610b is turned on, the storage node XC rises toward the power supply voltage VDD. The n-channel MOS transistor 611a is turned on by the increase in the voltage of the storage node XC, and the voltage of the storage node XT decreases toward the ground voltage VSS (FIG. 9 (l)). After the voltages of the storage nodes XC and XT become the power supply voltage VDD and the ground voltage VSS, the output control signal SAOUTB is set to a low level (FIG. 9 (m)). As a result, the Noah Gate 67a outputs a high-level data output signal SAOUT in which the logic level of the node XT is inverted (FIG. 9 (n)). That is, the ROM read circuit 60 reads the logic 1 stored in the ROM memory cell 12.

For example, the reading of data from the ROM memory cell 12 is executed at the time of starting the power supply of the semiconductor storage device 100A, before the power supply voltage VCS received from the outside reaches a predetermined voltage (for example, 2.5V). The data output signal SAOUT, which is the data read from the ROM memory cell 12, is used to set the operating state of the internal circuit, such as the power supply voltage VPPX generated by the semiconductor storage device 100A and the trimming information for adjusting VDD. To.

After the data output signal SAOUT is output, the latch signal LATVSS and the output control signal SAOUTB are set to high level, and the sense amplifier enable signal SAEN is set to low level (FIGS. 9 (o), (p), (q)). ). The data output signal SAOUT is changed to a low level by the high-level output control signal SAOUTB, and the operation of reading data from the ROM memory cell 12 by the ROM read circuit 60 is completed (FIG. 9 (r)). The high-level latch signal LATVSS turns off the p-channel MOS transistor 62a, and the low-level sense amplifier enable signal SAEN turns off the n-channel MOS transistor 63a. As a result, the current path of the ground line VSS is cut off from the power supply line VDD by the latch portion 61 and the resistance elements R0 and R1.

As shown in FIG. 8, the resistance elements R0 and R1 of the ROM memory cell 12 are directly connected between the latch portion 61 of the ROM read circuit 60 and the ground switch 63. Then, the ROM read circuit 60 determines the logic of the data stored in the ROM memory cell 12 according to the difference between the currents flowing through the resistance elements R0 and R1. As a result, data can be read from the ROM memory cell 12 without driving the word lines RWL0, RWL1 and the column selection signal RYDVW connected to the ROM memory cell 12. In other words, data can be read from the ROM memory cell 12 without using the bit line RBL and the source line RSL with the word line RWL set to the non-selection level. Therefore, data can be read out from the ROM memory cell 12 at a higher speed than in the case where the word line RWL is driven to a high level and a current is passed between the bit line RBL and the source line RSL via the resistance elements R0 and R1. ..

The voltage generated in the storage nodes XC and XT is differentially amplified by the latch portion 61 based on the current difference corresponding to the complementary logic stored in the resistance elements R0 and R1, respectively, so that the voltage is stored in one resistance element R. The read margin can be improved as compared with the case of reading the logic.

Further, since the sense amplifier 52 does not have to be operated, it is not necessary to drive the column selection signal YD0 and the read enable signal REN. Therefore, data can be read from the ROM memory cell 12 only by the power supply voltage VDD without using the power supply voltages VPPX and VPPY. As a result, for example, when the power supply of the semiconductor storage device 100A is started, data can be read from the ROM memory cell 12 even when the power supply voltages VPPX and VPPPY do not reach the specified voltage.

FIG. 10 shows an example of the column switch 30 of FIG. FIG. 10 shows the column switch 30 controlled by the column selection signal YD0 among the column switches 30 shown in the broken line frame in FIG. The column switch 30 shown by the other broken line frame in FIG. 2 is the same as that of FIG. 10 except that the numbers of the column selection signal YD, the bit line BL, and the source line SL are different.

The column switch 30 has CMOS transmission gates 30a and 30b and a CMOS inverter 30c. The thick line shown on the input side of the CMOS inverter 30c indicates that the transistor included in the CMOS inverter 30c is a high withstand voltage type. The CMOS inverter 30c inverts the logic of the column selection signal YD0, and supplies the inverted signal to the gates of the p-channel MOS transistors of the CMOS transmission gates 30a and 30b. The column selection signal YD0 is supplied to the gates of the n-channel MOS transistors of the CMOS transmission gates 30a and 30b.

The column switch 30 is turned on when the column selection signal YD0 is at a high level (VPPY), connects the bit line BL0 to the global bit line GBL, and connects the source line RSL to the global source line GSL. The column switch 30 is turned off when the column selection signal YD0 is at the low level (VSS), disconnects the bit line BL0 from the global bit line GBL, and disconnects the source line RSL and the global source line GSL.

Each of the switches 40b and 40c of the light driver 40 shown in FIG. 2 includes, for example, the same configuration as the CMOS transmission gate 30a and the CMOS inverter 30c. Then, the switch 40a (or 40b) is turned on during the period when the high-level write control signal WR0 (or WR1) is received, and is turned off during the period when the low-level write control signal WR0 (or WR1) is received.

FIG. 11 shows an example in which one ROM memory cell 12 is provided corresponding to the memory cell array 20. The same elements as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. FIG. 11 shows a circuit provided corresponding to one data terminal I / O. Therefore, for example, when the memory cell array 20 corresponds to the 32 data terminals I / O, 32 ROM memory cells 12 are provided corresponding to the memory cell array 20.

The ROM memory cell 12 is connected to four sets of bit line BL / source line SL via the ROM column switch 70 during the write operation, and one set of bit line BL / source via the ROM column switch 70 during the verify operation. Connected to line SL. FIG. 11 shows an example of writing the logic 1 to the resistance element R0, and the signal line and the circuit shown by the thick line are used for the writing operation.

In the example shown in FIG. 11, the ROM memory cell 12 is connected to the bit line BL0-BL3 and the source line SL0-SL3, but may be connected to the other four sets of bit line BL / source line SL. In this case, the column selection signal YD driven during the writing operation and the verifying operation of the ROM memory cell 12 is changed.

The writing operation and the verifying operation of the ROM memory cell 12 are executed for each of the resistance elements R0 and R1. When executing the writing operation and the verifying operation of the resistance element R0, the word line RWL0 is set to a high level, and when executing the writing operation and the verifying operation of the resistance element R1, the word line RWL1 is set to a high level.

For example, when the write control signal WR1 is set to a high level, the global bit line GBL is set to the power supply voltage VPPY, and the global source line GSL is set to the ground voltage VSS, the resistance from the bit line RBL to the source line RSL. A current flows in the element R0. As a result, the resistance element R0 is set to the low resistance state, and the resistance element R0 is in the storage state of the logic 1. An example of the writing operation will be described with reference to FIG. 19, and an example of the verifying operation will be described with reference to FIG.

When a plurality of ROM memory cells 12 corresponding to a plurality of data terminals I / O are provided corresponding to the memory cell array 20, the plurality of ROM memory cells 12 are connected to the common word lines RWL0 and RWL1. Then, in the writing operation, the data received by the plurality of data terminals I / O is written in parallel to the resistance element R0 or the resistance element R1 of the ROM memory cell 12 corresponding to the plurality of data terminals I / O. In this case, the switches 70a-70h of the plurality of ROM column switches 70 connected to the plurality of ROM memory cells 12 are turned on. In the writing operation, four column selection signals YD are set to a high level regardless of the number of data terminals I / O, and the column switch 30 (8) connected to the column selection signal YD set to a high level. CMOS transmission gates) are turned on.

12 and 13 show an example of a column control circuit 32 that controls the column switch 30 of the memory cell array 20 of FIG. The column control circuit 32 includes pre-decoders 33 and 34 (FIG. 12), a decoder 35 and a level shifter 36 (FIG. 13).

First, the operation of the column control circuit 32 when the write operation, verify operation, and read operation (hereinafter, also referred to as normal operation) of the memory cell 10 in the memory cell array 20 is executed will be described. In normal operation, the write signal WR, verify signal VRFY and ROM access signal RACC are set to low level.

In normal operation, the pre-decoder 33 decodes the 2-bit address signals A1 and A0 and sets any one of the pre-decoded signals A ## Z (A00Z, A01Z, A10Z, A11Z) to a high level (VDD). The numbers of the pre-decoded signals A ## Z indicate the bit values of the address signals A1 and A0. For example, when the address signals A1 and A0 = "01", the pre-decoded signal A01Z is set to a high level, and when the address signals A1 and A0 = "10", the pre-decoded signal A10Z is set to a high level.

In normal operation, the pre-decoder 34 decodes the 3-bit address signals A4, A3, and A2 and sets any of the pre-decoded signals A #### Z to a high level (VDD). Here, the pre-decode signal A #### Z is any one of A000Z, A001Z, A010Z, A011Z, A100Z, A101Z, A110Z, and A111Z, and "###" is a bit of the address signals A4, A3, and A2. Indicates a value. For example, when the address signals A4, A3, A2 = "001", the pre-decode signal A001Z is set to a high level, and when the address signals A4, A3, A2 = "110", the pre-decode signal A110Z is set to a high level. Will be done.

In FIG. 13, in normal operation, the decoder 35 sets one of the 32 pre-column selection signals pYD (pYD0-pYD31) at a high level (VDD) in response to the pre-decode signals A ## Z and A ## # Z. Set to. The level shifter 36 that receives each pre-column selection signal pYD converts the high level of the pre-column selection signal pYD from the power supply voltage VDD to the power supply voltage VPPY and outputs it as a high-level column selection signal YD (any of YD0-YD31). Then, the column switch 30 connected to the high-level column selection signal YD is turned on. In normal operation, one of the word line WLs is set to a high level, and data is written to and verified in the memory cell 10 corresponding to the column switch 30 turned on and the word line WL set to a high level. An operation or read operation is performed.

Returning to FIG. 12, the operation of the column control circuit 32 when the writing operation of the ROM memory cell 12 is executed will be described. In the write operation of the ROM memory cell 12, the write signal WR is set to high level (VDD), the verify signal VRFY is set to low level, and the ROM access signal RACC is set to high level (VDD).

The output of each NAND gate of the NAND gate group 33a of the pre-decoder 33 is fixed to the high level by the high-level write signal WR and the high-level ROM access signal RACC. As a result, the pre-decoder 33 fixes all four pre-decode signals A00Z, A01Z, A10Z, and A11Z to a high level.

Further, the output of each NAND gate of the NAND gate group 34a of the pre-decoder 34 is fixed to the high level by the high-level write signal WR and the high-level ROM access signal RACC, and only the pre-decode signal A000Z becomes the high level. It is fixed. The decoder 35 of FIG. 13 sets the pre-column selection signals pYD0, pYD1, pYD2, and pYD3 to a high level based on the high-level pre-decode signals A00Z, A01Z, A10Z, A11Z, and A000Z. Therefore, in the writing operation of the ROM memory cell 12, the column selection signals YD0, YD1, YD2, and YD3 are set to high levels at the same time. The signal flow when the writing operation of the ROM memory cell 12 is executed will be described with reference to FIG.

Returning to FIG. 12, the operation of the column control circuit 32 when the verification operation of the ROM memory cell 12 is executed will be described. In the verify operation of the ROM memory cell 12, the write signal WR is set to the low level, the verify signal VRFY is set to the high level (VDD), and the ROM access signal RACC is set to the high level (VDD).

Due to the high-level verify signal VRFY and the high-level ROM access signal RACC, the output of each NAND gate of the NAND gate group 33b of the pre-decoder 33 is fixed to the high level, and only the pre-decode signal A00Z is fixed to the high level. Will be done.

The operation of the pre-decoder 34 during the verify operation is the same as that during the write operation, and the pre-decoder 34 fixes only the pre-decode signal A000Z at a high level. The decoder 35 of FIG. 13 sets only the pre-column selection signal pYD0 to a high level based on the high-level pre-decode signals A00Z and A000Z, and sets only the column selection signal YD0 to a high level. The signal flow when the verification operation of the ROM memory cell 12 is executed will be described with reference to FIG.

As described above, the column control circuit 32 shown in FIGS. 12 and 13 can execute the write operation and the verify operation of the ROM memory cell 12 as described with reference to FIG.

FIG. 14 shows an example in which two ROM memory cells 12 are provided corresponding to the memory cell array 20. The same elements as those in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted. FIG. 14 shows a circuit provided corresponding to one data terminal I / O. Therefore, for example, when the memory cell array 20 corresponds to 32 data terminals I / O, 64 ROM memory cells 12 are provided corresponding to the memory cell array 20. The ROM read circuit 60 and the ROM column switch 70 are provided for each ROM memory cell 12.

When two ROM memory cells 12 are provided for each data terminal I / O corresponding to the memory cell array 20, they are connected to four sets of bit line BL / source line SL in addition to the ROM memory cell 12 shown in FIG. The ROM column switch 70 and the ROM memory cell 12 to be used are arranged. In FIG. 14, the ROM memory cell 12 shown in FIG. 11 is shown by the ROM memory cell 12A, and the ROM memory cell 12 different from the ROM memory cell 12A is shown by the ROM memory cell 12C.

The ROM memory cell 12C is connected to the bit line BL16-BL19 and the source line SL16-SL19 via the ROM column switch 70. The ROM memory cells 12A and 12C may be connected to the other four sets of bit line BL / source line SL, respectively, via the ROM column switch 70.

FIG. 14 shows an example of writing data to the resistance element R0 of the ROM memory cell 12C, and the signal lines and circuits shown by thick lines are used for the writing operation. When writing data to the ROM memory cell 12C, the column selection signal YD16-YD19 is set to a high level, the bit line BL16-BL19 is connected to the global bit line GBL, and the source line SL16-SL19 is connected to the global source line GSL. Will be done.

Further, in the writing operation, the column selection signals RYDW and RYDVW common to the ROM memory cells 12A and 12C are set to a high level. As a result, the bit line RBL and the source line RSL connected to the ROM memory cell 12C are connected to the bit line BL16-BL19 and the source line SL16-SL19 via the ROM column switch 70. Then, a current flows through the resistance element R0 selected by the word line RWL0, and data is written to the resistance element R0 of the ROM memory cell 12A.

Since the column selection signal YD0-YD3 is maintained at a low level, no current flows through the bit line BL0-BL3 and the source line SL0-SL3 even when the common column selection signals RYDW and RYDVW are set to a high level. .. Therefore, when the write operation of the ROM memory cell 12C is executed, the data is not written to the resistance element R0 of the ROM memory cell 12A. In this way, the writing operation of the ROM memory cell 12 is sequentially executed for each of the resistance elements R0 and R1 of the ROM memory cell 12. The ROM memory cells 12A and 12C may be connected to the other four sets of bit line BL / source line SL via the ROM column switch 70, respectively.

As shown in FIG. 14, when a plurality of ROM memory cells 12 corresponding to a plurality of data terminals I / O are provided corresponding to the memory cell array 20, the plurality of ROM memory cells 12 have a common word line. It is connected to RWL0 and RWL1. Then, in the writing operation, the data received by the plurality of data terminals I / O is written in parallel to the resistance element R0 or the resistance element R1 of the ROM memory cell 12 corresponding to each of the data terminals I / O. In this case, the switches 70a-70h of the plurality of ROM column switches 70 connected to the plurality of ROM memory cells 12 are turned on. In the writing operation, only the four column selection signals YD are set to the high level regardless of the number of data terminals I / O, and the column switch 30 (8) connected to the column selection signal YD set to the high level. CMOS transmission gates) are turned on.

FIG. 15 shows an example of a column control circuit that controls the column switch 30 of the memory cell array 20 of FIG. The same elements as those in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

The circuit and operation of the pre-decoder 33 are the same as in FIG. 12, and the circuit and operation of the decoder 35 (not shown) are the same as in FIG. In the normal operation of accessing the memory cell 10 of the memory cell array 20, the operation of the pre-decoder 34 of FIG. 15 is the same as that of the description of FIG. The pre-decoder 34 of FIG. 15 has an inverter IV instead of the NAND gate of FIG. 12 that receives the address signal A4. Therefore, the logic of the address signal A4 is not masked in the write operation and the verify operation of the ROM memory cell 12.

Therefore, the pre-decoder 34 of FIG. 15 sets the pre-decode signal A000Z to a high level when the address signal A4 is logic 0 in the write operation and the verify operation of the ROM memory cell 12. The pre-decoder 34 of FIG. 15 sets the pre-decode signal A100Z to a high level when the address signal A4 is logic 1.

The decoder 35 shown in FIG. 13 sets the column selection signals YD0, YD1, YD2, and YD3 high when receiving high-level pre-decode signals A00Z, A01Z, A10Z, A11Z, and A000Z in the writing operation of the ROM memory cell 12. Set to level. When the decoder 35 receives high-level pre-decode signals A00Z, A01Z, A10Z, A11Z, and A100Z in the write operation of the ROM memory cell 12, the decoder 35 sets column selection signals YD16, YD17, YD18, and YD19 (not shown) to high levels. To do.

The decoder 35 sets the column selection signal YD0 to a high level when it receives high-level pre-decode signals A00Z and A000Z in the verify operation of the ROM memory cell 12. When the decoder 35 receives the high-level pre-decode signals A00Z and A100Z in the verification operation of the ROM memory cell 12, the decoder 35 sets the column selection signal YD16 (not shown) to the high level. As a result, as shown in FIG. 14, the writing operation of the ROM memory cell 12C and the verifying operation of the ROM memory cell 12A or 12C can be executed, respectively.

16 and 17 show an example in which eight ROM memory cells 12 are provided corresponding to the memory cell array 20. The same elements as those in FIGS. 11 and 14 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIGS. 16 and 17, eight sets of four bit line BLs / source line SLs are connected to any of the eight ROM memory cells 12 for each data terminal I / O via the ROM column switch 70. To.

16 and 17 show an example of writing data to the resistance element R0 of the ROM memory cell 12C corresponding to the bit lines BL16-BL19 of FIG. 16, similarly to FIG. 14, and the signal lines and circuits shown by the thick lines are shown. Used for write operations. The state of the writing operation shown in FIGS. 16 and 17 is the same as the state of FIG.

FIG. 18 shows an example of a column control circuit that controls the column switch 30 of the memory cell array 20 of FIGS. 16 and 17. The same elements as those in FIGS. 12 and 15 are designated by the same reference numerals, and detailed description thereof will be omitted.

The circuit and operation of the pre-decoder 33 are the same as in FIG. 12, and the circuit and operation of the decoder 35 (not shown) are the same as in FIG. In the normal operation of accessing the memory cell 10 of the memory cell array 20, the operation of the pre-decoder 34 in FIG. 18 is the same as that described in FIG. The pre-decoder 34 of FIG. 18 has an inverter IV instead of the NAND gate of FIG. 12 that receives the address signals A4, A3, A2. Therefore, the logic of the address signals A4, A3, and A2 is not masked in the write operation and the verify operation of the ROM memory cell 12.

The pre-decoder 33 sets the pre-decode signals A00Z, A01Z, A10Z, and A11Z to high levels in the writing operation of the ROM memory cell 12. The pre-decoder 33 sets only the pre-decode signal A00Z to a high level in the verification operation of the ROM memory cell 12.

The pre-decoder 34 of FIG. 18 sets the pre-decode signal A #### Z (any of A000Z-A111Z) to a high level according to the logic of the address signals A4, A3, and A2. The operation of the pre-decoder 34 is the same in the normal operation, the writing operation of the ROM memory cell 12, and the verifying operation of the ROM memory cell 12.

The decoder 35 shown in FIG. 13 has four consecutive column selection signals YD (for example, YD0-YD3, YD4-) in response to the high-level pre-decode signal A ## # Z in the writing operation of the ROM memory cell 12. YD7 etc.) is set to a high level. In the verification operation of the ROM memory cell 12, the decoder 35 performs one of the column selection signals YD0, YD4, YD8, YD12, YD16, YD20, YD24, and YD28 according to the high-level pre-decode signal A ## # Z. Set to high level.

As a result, in each of the eight ROM memory cells 12, a writing operation and a verifying operation can be executed on the resistance element R0 (or R1) selected by the word line RWL0 (or RWL1).

When four ROM memory cells 12 are provided corresponding to the memory cell array 20, the column control circuit 32 has an inverter IV instead of the NAND gate of FIG. 12 that receives the address signal A3 of FIG. As a result, the writing operation and the verifying operation of each ROM memory cell 12 can be executed.

FIG. 19 shows an example of the writing operation of the ROM memory cell 12 of the semiconductor storage device 100A of FIG. Similar to FIG. 11, the signal lines and circuits shown by the thick lines are used for the writing operation of the ROM memory cell 12. As described with reference to FIG. 11, in the writing operation, the ROM memory cell 12 is connected to the four sets of bit lines BL0-BL3 / source lines SL0-SL3 via the ROM column switch 70.

FIG. 19 shows an example of writing logic 1 to the resistance element R0 of the ROM memory cell 12. In this case, the word line RWL0 is set to a high level in order to connect the resistance element R0 to the bit line RBL. Further, in the writing operation, the column selection signals RYDW and RYDVW are set to a high level, and all the switches 70a-70h of the ROM column switch 70 are turned on. When the switch 70a-70h is turned on, the bit line RBL is connected to the bit line BL0-BL3, and the source line RSL is connected to the source line SL0-SL3.

Further, in the writing operation, the column selection signal YD0-YD3 is set to a high level, and the column switch 30 that receives the column selection signal YD0-YD3 is turned on. When the column switch 30 is turned on, the bit line BL0-BL3 is connected to the global bit line GBL, and the source line SL0-SL3 is connected to the global source line GSL. Further, the write control signal WR1 is set to a high level, the switches 40c and 40d of the write driver 40 are turned on, the global bit line GBL is connected to the power supply line VPPY, and the global source line GSL is connected to the ground line VSS. To. That is, high-level and low-level write voltages are set for the global bit line GBL and the global source line GSL.

The power supply line VPPY is connected to the ground line VSS via the global source line GSL, the source line SL0-SL3, RSL, the resistance element R0, the bit line RBL, BL0-BL3 and the global bit line GBL. Then, when the writing current flows from one end to the other end of the resistance element R0, the resistance element R0 is set to the low resistance state, and the resistance element R0 is in the storage state of the logic 1.

At this time, a current is supplied to the resistance element R0 via the four bit wires BL0-BL3 connected in parallel, and flows to the resistance element R0 via the four source lines SL0-SL3 connected in parallel. Current is drawn into the ground wire VSS. Therefore, the wiring resistance of the bit line BL and the source line SL used for writing data can be reduced. For example, by arranging the bit line BL and the source line SL in parallel of four, the bit line resistance and the source line resistance can be reduced to about one-fourth as compared with the case where they are not parallelized.

Further, the current flows from the power supply line VPPY to the ground line VSS via the four switches 70a, 70b, 70c, 70d connected in parallel and the four switches 70e, 70f, 70g, 70h connected in parallel. Thereby, the on-resistance of the ROM column switch 70 can be lowered. For example, by arranging the ROM column switches 70 in parallel in four, the on-resistance can be reduced to about one-fourth as compared with the case where the ROM column switches 70 are not parallelized.

As a result, it is possible to suppress the voltage drop in the path through which the current flows through the resistance element R0, and the resistance element R0 of the ROM memory cell 12 arranged on the opposite side of the light driver 40 with the memory cell array 20 sandwiched between them can receive a desired current. You can stream and write data. In other words, data can be written to the ROM memory cell 12 by using the write driver 40 used for the normal writing operation of the memory cell 10. Further, since the resistance of the path through which the current flows through the resistance element R0 can be lowered to increase the writing current, the number of writing operations until the resistance element R0 is set to a desired resistance value can be reduced.

On the other hand, when the write operation of the ROM memory cell 12 is executed using the write driver 40 and one set of bit line BL / source line SL, the voltage drops due to the resistance and wiring resistance of the column switches 30 and 70. May occur and the write current to the resistance element R0 may be insufficient. When the number of write operations and verify operations increases due to insufficient write current, the write processing time becomes long.

The writing operation of writing the logic 0 to the resistance element R0 is the same as the state shown in FIG. 19 except that the switches 40a and 40b of the write driver 40 are turned on instead of the switches 40c and 40d. That is, in the logic 0 write operation, low level and high level write voltages are set for the global bit line GBL and the global source line GSL. In this case, since the writing current flows from the other end to one end of the resistance element R0, the resistance element R0 is set to the high resistance state, and the resistance element R1 is in the storage state of logic 0. Further, the writing operation for writing data to the resistance element R1 is the same as the state shown in FIG. 19 except that the word line RWL1 is set to a high level instead of the word line RWL0.

When writing data to the memory cell 10 of the memory cell array 20, the column switch 30 connected to the set of bit line BL / source line SL connected to the memory cell 10 to be written is turned on. Therefore, as described with reference to FIGS. 12 and 13, the operation of the column control circuit 32 that generates the column selection signal YD (YD0-YD31) is performed between the writing operation of the ROM memory cell 12 and the writing operation of the memory cell 10. different.

FIG. 20 shows an example of the verification operation of the ROM memory cell 12 of the semiconductor storage device 100A of FIG. The verify operation is an operation of determining whether or not data is normally written to the ROM memory cell 12 after the write operation shown in FIG. 19, and is executed for each of the resistance elements R0 and R1 in the same manner as the write operation. Will be done. Similar to FIGS. 11 and 19, the signal lines and circuits shown by the thick lines are used for the verification operation of the ROM memory cell 12.

FIG. 20 shows an example of confirming the logic of the data written in the resistance element R0 of the ROM memory cell 12. In this case, the word line RWL0 is set to a high level in order to connect the resistance element R0 to the bit line RBL as in the writing operation. Further, in the verify operation, the column selection signal RYDVW is set to a high level, and the column selection signal RYDW is set to a low level. As a result, the switches 70d and 70h of the ROM column switch 70 are turned on, and the switches 70a-70c and 70e-70g are turned off. When the switches 70d and 70h are turned on, the bit line RBL is connected to the bit line BL0 and the source line RSL is connected to the source line SL0.

Further, in the verify operation, the column selection signal YD0 is set to a high level, and the other column selection signals YD are set to a low level. As a result, only the column switch 30 that receives the column selection signal YD0 is turned on. When the column switch 30 is turned on, the bit line BL0 is connected to the global bit line GBL, and the source line SL0 is connected to the global source line GSL. Further, the read enable signal REN is set to a high level, the switches 50a and 50b of the read circuit 50 are turned on, the global bit line GBL is connected to the ground line VSS, and the global source line GSL is connected to the sense amplifier 52. To.

The sense amplifier 52 outputs the power supply voltage VDD (for example, 1.2V) to the global source line GSL during the verify operation. As a result, the terminal of the sense amplifier 52 that outputs the power supply voltage VDD is connected to the ground line VSS via the global source line GSL, the source line SL0, RSL, the resistance element R0, the bit line RBL, BL0 and the global bit line GBL. To. Then, the read current flows from the other end of the resistance element R0 to one end, so that the voltage of the terminal of the sense amplifier 52 drops.

When the resistance element R0 is set to the low resistance state, the current flowing through the resistance element R0 is relatively large, so that the amount of voltage drop at the terminal of the sense amplifier 52 is large. On the other hand, when the resistance element R0 is set to the high resistance state, the current flowing through the resistance element R0 is relatively small, so that the amount of voltage drop at the terminal of the sense amplifier 52 is small. Then, the sense amplifier 52 determines logic 1 (low resistance state) when the terminal voltage of the terminal connected to the global source line GSL is equal to or less than the reference voltage, and logic 0 (high) when the terminal voltage is higher than the reference voltage. (Resistance state) is judged. The read operation and the verify operation of the memory cell 10 are the same as the operation of the sense amplifier 52 in the verify operation of the memory cell 12.

In the verification operation of the ROM memory cell 12, the word line WL connected to the memory cell array 20 is set to a low level, and the transfer transistor T of the memory cell 10 is turned off. However, the off-leakage current generated by the transfer transistor T in the non-selected state flows through the bit line BL connected to the transfer transistor T. In the example shown in FIG. 20, four word line WLs are connected to the memory cell array 20, but since a large number of word line WLs (for example, 1024 lines) are connected to the actual memory cell array 20, each bit is connected. The influence of the off-leakage current flowing through the line BL may not be negligible.

In the verification operation of this embodiment, by using only one bit wire BL, the influence of the off-leakage current can be reduced as compared with the case of using, for example, four bit wire BLs, and it is more accurate. It is possible to perform various verification operations. Further, the read current flowing through the bit line BL0 or the like during the verify operation is smaller than the write current flowing during the write operation, and the wiring resistance of the bit line BL0 and the source line SL0 and the resistance of the column switches 30 and 70 give the verify operation. The impact is small. Therefore, by using one bit line BL0 and one source line SL0, the logic stored in the resistance element R0 can be determined. Therefore, the verification operation of the resistance element R0 of the ROM memory cell 12 arranged on the opposite side of the memory cell array 20 from the sense amplifier 52 can be executed. In other words, the verify operation of the ROM memory cell 12 can be executed by using the sense amplifier 52 used for the read operation and the verify operation of the memory cell 10.

The verification operation of the resistance element R1 is the same as the state shown in FIG. 20 except that the word line RWL1 is set to a high level instead of the word line RWL0 and a read current is passed through the resistance element R1. When the verification operation determines that the writing operation is insufficient, the writing operation shown in FIG. 19 is executed again. Thereby, the resistance value of each resistance element R0 and R1 can be set to a desired value.

In the verification operation of the ROM memory cell 12, by determining the logic of the data for each of the resistance elements R0 and R1, the data written in the ROM memory cell 12 is compared with the case where the verification operation is executed in the entire ROM memory cell 12. The accuracy of the can be improved. That is, the accuracy of the resistance value set in each of the resistance elements R0 and R1 can be improved.

In the write operation, read operation, and verify operation of the memory cell 10 of the memory cell array 20, the column selection signals RYDW and RYDVW are set to the low level, and the word line WL connected to the memory cell 10 to be accessed is set to the high level. Will be done. Further, the column selection signal YD for selecting the bit line BL and the source line SL connected to the memory cell 10 to be accessed is set to a high level, and the corresponding column switch 30 is turned on.

When writing data to the memory cell 10, the column switch 30 connected to the set of bit line BL / source line SL connected to the memory cell 10 to be written is turned on. Then, the write driver 40 causes a write current to flow through the resistance element R of the memory cell 10 to be accessed, so that logic 0 or logic 1 is written to the resistance element R according to the direction in which the write current flows.

By setting the column selection signals RYDW and RYDVW to low levels and turning off the ROM column switch 70 during the write operation, read operation, and verify operation of the memory cell 10, the load of the bit line RBL and the source line RSL is separated from the memory cell array 20. Is done. As a result, it is possible to prevent the load of the bit line RBL and the source line RSL from affecting the access of the memory cell 10.

The ROM memory cell 12 stores important information (trimming information for adjusting the internal voltage and internal timing, defective address, etc.) that determines the operating state of the semiconductor storage device 100A. Therefore, access to the ROM memory cell 12 by the user system on which the semiconductor storage device 100A is mounted is not permitted. For example, the writing operation of the ROM memory cell 12 and the verifying operation of the ROM memory cell 12 are executed before the shipment of the semiconductor storage device 100A.

For example, the writing operation of the ROM memory cell 12 and the verifying operation of the ROM memory cell 12 are executed in a test step which is one of the manufacturing steps of the semiconductor storage device 100A. In the test step, the power supply voltage VCS (VPPY) of a desired value can be supplied to the semiconductor storage device 100A. As a result, a stable power supply voltage VPPY can be supplied to the semiconductor storage device 100A as compared with the case where the semiconductor storage device 100A is operated on the user system. Therefore, even when the write driver 40 and the sense amplifier 52 used for the normal writing operation of the memory cell 10 are used, the writing operation and the verifying operation of the ROM memory cell 12 can be executed without lowering the operation margin. it can.

FIG. 21 shows an example of the read operation of the ROM memory cell 12 of the semiconductor storage device 100A of FIG. The read operation of the ROM memory cell 12 is executed by the ROM read circuit 60 as described with reference to FIGS. 8 and 9. Similar to FIGS. 11, 19 and 20, the signal lines and circuits shown by the thick lines are used for the read operation of the ROM memory cell 12.

The sense amplifier 52, the bit line BL, RBL, and the source line SL are not used, and the column switches 30 and 70 are maintained in the off state. Further, the word lines RWL0 and RWL1 are maintained at a low level, and the transfer transistors T0 and T1 of the ROM memory cell 12 are maintained in an off state.

As described with reference to FIG. 9, the read operation of the ROM memory cell 12 by the ROM read circuit 60 is executed using only the power supply voltage VDD without using the power supply voltages VPPX and VPPY. Therefore, data can be read from the ROM memory cell 12 even when the power supply voltages VPPX and VPPPY do not reach the specified voltage, such as when the power supply of the semiconductor storage device 100A is started. Further, since the data is read from the resistance elements R0 and R1 that store the complementary logic, the read margin can be improved as compared with the case where the logic stored in one resistance element R is read. Since the ROM column switch 70 is turned off in the read operation of the ROM memory cell 12, it is possible to prevent the load of the bit line BL and the load of the source line SL from affecting the read operation.

FIG. 22 shows an example of the arrangement of circuits of other semiconductor storage devices. The same components as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor storage device 200A shown in FIG. 22 has a memory cell array 20, a column switch 30, a write driver 40, a read circuit 50, a power supply circuit 80, and a data input / output circuit 90 similar to the semiconductor storage device 100A shown in FIG. Further, the semiconductor storage device 200A includes a ROM memory cell 12, a ROM read circuit 60, a ROM verification circuit 202, and a ROM write driver 204. The ROM memory cell 12, the ROM read circuit 60, the ROM verify circuit 202, and the ROM write driver 204 are circuit blocks dedicated to access to the ROM memory cell 12.

The ROM verification circuit 202 has a verification sense amplifier for executing the verification operation of the ROM memory cell 12 instead of the sense amplifier 52. The ROM write driver 204 supplies the power supply voltage VPPY and the ground voltage VSS to the ROM memory cell 12 instead of the write driver 40 during the writing operation of the ROM memory cell 12.

The data signal DT output from the data input / output circuit 90 to the power supply circuit 80 is, for example, data to be written to the ROM memory cell 12 and trimming information for adjusting the internal voltage generated by the power supply circuit 80. The data written to the ROM memory cell 12 is transferred to the ROM write driver 204 as write data WDT via the power supply circuit 80, and is written to the ROM memory cell 12.

In FIG. 22, the ROM memory cell 12 is formed in a dedicated circuit block different from the area where the memory cell array 20 is formed. Therefore, two dummy regions DMY in which dummy memory cells shown by a thick broken line frame in FIG. 22 are formed are provided in each of the two circuit groups. The semiconductor storage device 200A provided with the access-dedicated circuit block of the ROM memory cell 12 and the dummy area DMY for the ROM memory cell 12 has a larger chip size than the semiconductor storage device 100A shown in FIG.

As described above, even in the embodiments shown in FIGS. 2 to 21, the same effects as those in the embodiment shown in FIG. 1 can be obtained. For example, by writing data to the ROM memory cell 12 using a plurality of bit lines BL and a plurality of source lines SL, the resistance of the write voltage supply path uses a single supply path. It can be lowered compared to the case. By using the write driver 40 for the memory cell 10 for the write operation of the ROM memory cell 12, even when the distance from the write driver 40 to the ROM memory cell 12 becomes long, the desired write voltage is applied to the resistance elements R0 and R1. Can be supplied to. As a result, data can be written to the ROM memory cell 12 without lowering the write margin.

The circuit scale of the semiconductor storage device 100A can be reduced by executing the write operation and the verify operation of the ROM memory cell 12 by using the write driver 40 for the memory cell 10 and the read circuit 50, respectively. Further, it is possible to simplify the control of the writing operation and the verifying operation of the ROM memory cell 12.

By turning off the ROM column switch 70 during the read operation of the ROM memory cell 12, it is possible to prevent the load of the bit line BL and the load of the source line SL from affecting the read operation of the ROM memory cell 12. By turning off the ROM column switch 70 during the writing operation of the memory cell 10, it is possible to prevent the load of the bit line RBL and the source line RSL from being connected to the bit line BL and the source line SL, resulting in insufficient writing, etc. Can be suppressed.

By turning off the ROM column switch 70 during the read operation and the verify operation of the memory cell 10, a load such as the bit line RBL and the source line RSL is connected to the bit line BL and the source line SL during the read operation and the verify operation. Can be deterred. Therefore, it is possible to prevent an error in data determination or the like from occurring during the read operation and the verify operation.

Further, in the embodiment shown in FIGS. 2 to 21, in the ROM read circuit 60 shown in FIG. 8, the resistance elements R0 and R1 of the ROM memory cell 12 are the CMOS inverters 610 and 611 of the latch portion 61 and the ground wire VSS. Is directly connected between. Then, the ROM read circuit 60 determines the logic of the data stored in the ROM memory cell 12 according to the difference between the currents flowing through the resistance elements R0 and R1. As a result, data can be read from the ROM memory cell 12 without driving the word lines RWL0, RWL1 and the column selection signal RYDVW connected to the ROM memory cell 12. In other words, data can be read from the ROM memory cell 12 without using the bit line RBL and the source line RSL. Therefore, the data can be read out from the ROM memory cell 12 at a higher speed than when the bit line RBL is used.

The voltage generated in the storage nodes XC and XT is differentially amplified by the latch portion 61 based on the current difference corresponding to the complementary logic stored in the resistance elements R0 and R1, respectively, so that the voltage is stored in one resistance element R. The read margin can be improved as compared with the case of reading the logic.

Further, since the sense amplifier 52 does not have to be operated in the read operation of the ROM memory cell 12, the column selection signal YD0 and the read enable signal REN do not have to be driven. Therefore, data can be read from the ROM memory cell 12 only by the power supply voltage VDD without using the power supply voltages VPPX and VPPY. As a result, for example, when the power supply of the semiconductor storage device 100A is started, data can be read from the ROM memory cell 12 even when the power supply voltages VPPX and VPPPY do not reach the specified voltage.

In the read operation of reading data from the ROM memory cell 12, the ROM read circuit 60 does not use the word lines RWL0 and RWL1 connected to the ROM memory cell 12. Therefore, as described with reference to FIG. 5, data is read from the ROM memory cell 12 at the time of starting the power supply before the power supply voltage VPPX, which is the high level voltage (selection voltage) of the word lines RWL0 and RWL1, is generated. Can be done. Further, since the data can be read without driving the word line RWL whose high level is the power supply voltage VPPX, the reading time can be shortened as compared with the case of driving the word line RWL.

Since one bit line BL is used for the verification operation of the ROM memory cell 12, the influence of the off-leakage current can be reduced as compared with the case of using, for example, four bit line BLs, and more accurate verification can be performed. The action can be performed. Further, since the read current flowing through the bit line BL0 or the like during the verify operation is smaller than the write current flowing during the write operation, the wiring resistance of the bit line BL0 and the source line SL0 and the resistance of the column switches 30 and 70 are used for the verify operation. The impact is small.

As described above, in the verify operation, the logic stored in the resistance element R0 can be determined by using one bit line BL0 and one source line SL0. Therefore, the verification operation of the resistance element R0 of the ROM memory cell 12 arranged on the opposite side of the memory cell array 20 from the sense amplifier 52 can be executed. In other words, the verify operation of the ROM memory cell 12 can be executed by using the sense amplifier 52 used for the read operation and the verify operation of the memory cell 10.

The data read period from the ROM memory cell 12 is set before the power supply voltages VCS, VPPY, VDD, and VPPX reach the specified voltage. As a result, trimming information, defective addresses, and the like can be correctly set in a predetermined circuit before the access to the memory cell 10 is started by the user system or the like equipped with the semiconductor storage device 100A after the power supply is started. As a result, data can be read and written to and from the memory cell 10 without causing the semiconductor storage device 100A to malfunction.

By operating the booster circuit 88 after the latch signal LATVSS reaches a high level, it is possible to suppress power fluctuations during a period when the power supply voltage VDD is lower than 1.2V. Thereby, for example, even when the power supply fluctuation occurs with the start of the operation of the booster circuit 88, the data from the ROM memory cell 12 can be read before the power supply fluctuation occurs, and the data from the ROM memory cell 12 can be read. It is possible to prevent a decrease in the read margin of. Further, the ROM read control circuit 86 that controls the reading of data from the ROM memory cell 12 generates the permission signal VPEN, so that it is possible to prevent the booster circuit 88 from starting operation before the completion of reading.

By forming the ROM column switch 70 and the ROM memory cell 12 by utilizing the repeating pattern of the layout of the memory cell 10, the increase in area due to the provision of the ROM column switch 70 and the ROM memory cell 12 is minimized. Can be done. Further, the dummy area DMY can be formed so as to cover the periphery of the forming areas of the memory cell array 20, the ROM column switch 70, and the ROM memory cell 12. Therefore, the layout area of the dummy memory cell can be reduced as compared with the case where the ROM column switch 70 and the memory cell array 20 are arranged apart from each other and the dummy area DMY is provided separately, and the chip of the semiconductor storage device 100A can be reduced. The size can be reduced.

FIG. 23 shows an example of the arrangement of the circuit of the semiconductor storage device in another embodiment. The same elements as those in FIGS. 1 to 21 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor storage device 100B shown in FIG. 23 shows a chip image.

The semiconductor storage device 100B has two memory core blocks MCB shown by a thick frame arranged between the power supply circuit 80 and the data input / output circuit 90. Each memory core block MCB has two memory cell array 20 and two column switch 30 regions. The sense amplifier 52 and the write driver 40 are shared by two memory cell arrays 20. The write operation of the ROM memory cell 12 is executed by using the write driver 40, and the verify operation of the ROM memory cell 12 is executed by using the sense amplifier 52.

Further, the ROM memory cell 12, the ROM column switch 70, and the ROM read circuit 60 are provided adjacent to one of the memory core blocks MCB. An area for arranging another power supply circuit, a stabilizing capacitor, or the like is allocated to an empty area on the power supply circuit 80 side of the other memory core block MCB. The thick dashed line frame has a dummy area DMY in which dummy memory cells are formed. The semiconductor storage device 100B shows eight dummy regions DMY.

In the semiconductor storage device 100B shown in FIG. 23, the ROM memory cell 12, the ROM column switch 70, and the ROM read circuit 60 are arranged outside the memory core block MCB. As a result, as shown by the thick arrow between the two memory core blocks MCB, the difference in the distance from the sense amplifier 52 to the ends of the memory cell array 20 on both sides is the width of the write driver 40 (horizontal width in the figure). ) Can be suppressed. Therefore, the access characteristics of the memory cell 10 (FIG. 2) can be made substantially the same in the two memory cell arrays 20. As described above, in FIG. 23, the same effect as that of the embodiment shown in FIGS. 1 to 21 can be obtained.

FIG. 24 shows an example of the arrangement of circuits of other semiconductor storage devices. The same elements as those in FIGS. 3, 22, and 23 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor storage device 200B shown in FIG. 24 shows a chip image.

Similar to the semiconductor storage device 100B shown in FIG. 23, the semiconductor storage device 200B has two memory core block MCBs arranged between the power supply circuit 80 and the data input / output circuit 90. The ROM memory cell 12 is arranged in one memory core block MCB of FIG. 24, and the other power supply circuit, the stabilizing capacitor, and the like are arranged in the other memory core block MCB.

The ROM memory cell 12 and the ROM read circuit 60 are arranged in the memory core block MCB on the opposite side of the memory cell array 20 via the column switch 30. The write operation of the ROM memory cell 12 is executed by using the write driver 40, and the verify operation of the ROM memory cell 12 is executed by using the sense amplifier 52.

In FIG. 24, since the memory cell array 20 and the ROM memory cell 12 are not laid out continuously, a dummy area DMY dedicated to the ROM memory cell 12 is arranged around the ROM memory cell 12 as shown by a thick broken line frame. To. As a result, 10 dummy regions DMY, which are larger than those of the semiconductor storage device 100B shown in FIG. 23, are formed in the semiconductor storage device 200B.

In the semiconductor storage device 200B shown in FIG. 24, the ROM memory cell 12 and the ROM read circuit 60 are arranged in the memory core block MCB. As a result, as shown by the thick arrow, the distance from the sense amplifier 52 to the end of the memory cell array 20 is longer in the memory cell array 20 on the ROM memory cell 12 side.

In this case, the access characteristics of the memory cell 10 (FIG. 2) may differ between the two memory cell arrays 20. For example, the read cycle time and write cycle time specifications are set according to the ROM memory cell 12 having the slowest access time. Therefore, the access performance of the semiconductor storage device 200B may be lower than the access performance of the semiconductor storage device 100B shown in FIG. 23.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. Also, anyone with ordinary knowledge in the art should be able to easily come up with any improvements or changes. Therefore, there is no intention to limit the scope of the embodiments having invention to those described above, and it is possible to rely on suitable improvements and equivalents included in the scope disclosed in the embodiments.

1a Memory cell 1b Memory cell 2a, 2b Switch circuit 3a, 3b Switch control circuit 4 Write circuit 5a, 5b Read circuit 10 Memory cell 12 ROM memory cell 20 Memory cell array 22 Low decoder 30 Column switch 40 Light driver 50 Read circuit 52 Sense amplifier 60 ROM read circuit 61 Latch 62 Power switch 63 Ground switch 64, 65 Precharge 66, 67 Output 70 ROM column switch 80 Power circuit 82 Low voltage detection circuit 84 Step-down circuit 86 ROM read control circuit 88 Boost circuit 90 Data input Output circuit 100, 100A, 100B Semiconductor storage device 200A, 200B Semiconductor storage device BL Bit line DMY Dummy area GBL Global bit line GSL Global source line LATVSS Latch signal PREB Precharge signal R, R0, R1 Resistance element RACC ROM access signal RBL bit Line RSL Source line RWL0, RWL1 Word line RYDW, RYDVW Column selection signal SAEN Sense amplifier enable signal SAOUTB Output control signal SL Source line SW switch T, T0, T1 Transfer transistor VCS, VDD Power supply voltage VPPY, VPPX Power supply voltage VSS Ground voltage WL Word line WR0, WR1 Write control signal YD Column selection signal

Claims (12)

A plurality of first memory cells including a first resistance element whose resistance value changes by a writing operation and storing data according to the resistance value of the first resistance element.
A second memory cell that includes a second resistance element whose resistance value changes due to a writing operation and stores data set in the semiconductor storage device according to the resistance value of the second resistance element.
A plurality of first bit lines and a plurality of first source lines connected to the plurality of first memory cells,
A writing circuit that outputs data to be written to the plurality of first memory cells or the second memory cell, and
In the writing operation of writing data to the second memory cell, a first switch circuit for connecting the writing circuit to the plurality of first bit lines and the plurality of first source lines, and
In the writing operation of writing data to the second memory cell, a second switch circuit for connecting the plurality of first bit lines and the plurality of first source lines to the second memory cell. A semiconductor storage device characterized by having. The semiconductor storage device further
In the read operation of reading data from the first memory cell and the verify operation of verifying the data written in the first memory cell, the first determination of the data stored in the first memory cell is made. Read circuit and
In the read operation of reading data from the second memory cell, both ends of the second resistance element are set to a predetermined voltage, and the second memory cell is set according to the amount of current flowing through the second resistance element. The semiconductor storage device according to claim 1, further comprising a second read-out circuit for determining the data stored in the device. The second memory cell has a pair of the second resistance elements set to different resistance values.
The second read circuit
A latch unit containing a pair of inverting circuits in which one input is connected to the other output and having a pair of storage nodes.
A power switch that connects the pair of inverting circuits to the first power line,
It has a grounding switch that connects each of the pair of storage nodes to the grounding wire via each of the pair of the second resistance elements.
In the read operation of reading data from the second memory cell, the pair of inverting circuits are connected to the first power supply line via the power supply switch, and the pair of the second resistance elements and the ground switch are connected to each other. 2. The second aspect of the invention, wherein the pair of inverting circuits are connected to a ground wire and data is read out to the latch portion according to a difference in the amount of current flowing through the pair of the second resistance elements. Semiconductor storage device. The semiconductor storage device further
A second bit wire connected to at least one of the plurality of bit wires via the second switch circuit, and a second bit wire.
A second source line connected to at least one of the plurality of first source lines via the second switch circuit.
In the second memory cell, a pair of transfer transistors arranged between one end of the pair of resistance elements and the second bit line, and
It has a pair of word lines, each connected to the pair of transfer transistors, and
The semiconductor storage device according to claim 3, wherein the pair of word lines is set to a non-selective level in a read operation for reading data from the second memory cell. The first read circuit is a plurality of first read circuits connected to the first memory cell to be accessed via the first switch circuit in the read operation and the verify operation of the first memory cell. One of the bit lines and one of the plurality of first source lines are set to a predetermined voltage, and the access target is set according to the amount of current flowing through the first resistance element of the first memory cell to be accessed. The data stored in the first memory cell of the above is determined, and
In the verification operation for verifying the data written in the second memory cell,
The first switch circuit connects any one of the plurality of first bit lines and one of the plurality of first source lines to the first read circuit.
The second switch circuit connects the second memory cell to any one of the plurality of first bit lines and the plurality of first source lines connected to the first read circuit. And
The first reading circuit according to claim 2 to 4, wherein the first reading circuit determines data stored in the second memory cell according to the amount of current flowing through the second resistance element. The semiconductor storage device according to any one item. In the write operation of writing data to any of the plurality of first memory cells,
The first switch circuit connects the write circuit to any one of the plurality of first bit lines and the plurality of first source lines.
2. A claim, wherein the second switch circuit cuts off the connection between the plurality of first bit lines and the plurality of first source lines and the second memory cell. 5. The semiconductor storage device according to any one of 5. In the read operation of reading data from any of the plurality of first memory cells or the verification operation of verifying the data written in the plurality of first memory cells.
The first switch circuit connects the first read circuit to any one of the plurality of first bit lines and the plurality of first source lines.
2. A claim, wherein the second switch circuit cuts off the connection between the plurality of first bit lines and the plurality of first source lines and the second memory cell. 6. The semiconductor storage device according to any one of 6. The semiconductor storage device further
A power supply detection circuit that detects the startup of the power supply and
The second to seventh aspects of the present invention include a read control circuit that controls the second read circuit and reads data from the second memory cell based on the detection by the power supply detection circuit. The semiconductor storage device according to any one of the items. The semiconductor storage device further includes an internal voltage generation circuit that generates an internal voltage higher than the power supply voltage based on the power supply voltage received from the outside.
The read control circuit causes the second read circuit to read data from the second memory cell before the internal voltage generation circuit starts generating the internal voltage when the power supply is started. The semiconductor storage device according to claim 8. The read control circuit outputs a permission signal permitting the operation of the internal voltage generation circuit after the read of data from the second memory cell by the second read circuit is completed.
The semiconductor storage device according to claim 9, wherein the internal voltage generation circuit starts generation of the internal voltage based on the permission signal. The semiconductor storage device further includes a memory cell array including the plurality of first memory cells.
The claim is characterized in that the second switch circuit and the second memory cell are arranged in an area adjacent to the memory cell array using the same layout pattern as the plurality of first memory cells. The semiconductor storage device according to any one of claims 1 to 10. The semiconductor storage device further includes a pair of memory cell arrays, each containing the plurality of first memory cells.
The write circuit and the first read circuit are arranged between the pair of memory cell arrays and shared by the pair of memory cell arrays.
2. The second switch circuit, the second memory cell, and the second read circuit are arranged on one side of the pair of memory cell arrays on the side opposite to the write circuit side. The semiconductor storage device according to any one of claims 10.

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